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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_tlb.v] - Blame information for rev 482

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction TLB                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of ITLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Bugs fixed, coding style changed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Insn TLB
//
 
module or1200_immu_tlb(
        // Rst and clk
        clk, rst,
 
        // I/F for translation
        tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// I/F for translation
//
input                           tlb_en;
input   [aw-1:0]         vaddr;
output                          hit;
output  [31:`OR1200_IMMU_PS]    ppn;
output                          uxe;
output                          sxe;
output                          ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [`OR1200_ITLB_TAG]      vpn;
wire                            v;
wire    [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire                            tlb_mr_en;
wire                            tlb_mr_we;
wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_in;
wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_out;
wire                            tlb_tr_en;
wire                            tlb_tr_we;
wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_in;
wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_out;
 
// BIST
`ifdef OR1200_BIST
wire                        itlb_mr_ram_si;
wire                        itlb_mr_ram_so;
wire                        itlb_tr_ram_si;
wire                        itlb_tr_ram_so;
`endif
 
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19  v 0
// itlbwYtrX: ppn 31-13  uxe 7  sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
            {vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
                (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
                        {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
                        32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
                        spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
                        spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
                        spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
 
 
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
 
 
//
// Instantiation of ITLB Match Registers
//
   or1200_spram #
     (
      .aw(6),
      .dw(14)
      )
   itlb_mr_ram
     (
      .clk(clk),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(itlb_mr_ram_si),
      .mbist_so_o(itlb_mr_ram_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_mr_en),
      .we(tlb_mr_we),
      //.oe(1'b1),
      .addr(tlb_index),
      .di(tlb_mr_ram_in),
      .doq(tlb_mr_ram_out)
`ifdef OR1200_RAM_PARITY
      , .p_err()
`endif
      );
 
//
// Instantiation of ITLB Translate Registers
//
   or1200_spram #
     (
      .aw(6),
      .dw(22)
      )
   itlb_tr_ram
     (
      .clk(clk),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(itlb_tr_ram_si),
      .mbist_so_o(itlb_tr_ram_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_tr_en),
      .we(tlb_tr_we),
      //.oe(1'b1),
      .addr(tlb_index),
      .di(tlb_tr_ram_in),
      .doq(tlb_tr_ram_out)
`ifdef OR1200_RAM_PARITY
      , .p_err()
`endif
      );
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_tlb.v] - Blame information for rev 482

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction TLB ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of ITLB. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_immu_tlb.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Minor update:`
49			`// Bugs fixed, coding style changed.`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "or1200_defines.v"
55
56			`//`
57			`// Insn TLB`
58			`//`
59
60			`module or1200_immu_tlb(`
61			`// Rst and clk`
62			`clk, rst,`
63
64			`// I/F for translation`
65			`tlb_en, vaddr, hit, ppn, uxe, sxe, ci,`
66
67			`ifdef OR1200_BIST
68			`// RAM BIST`
69			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
70			`endif
71
72			`// SPR access`
73			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
74			`);`
75
76			parameter dw = `OR1200_OPERAND_WIDTH;
77			parameter aw = `OR1200_OPERAND_WIDTH;
78
79			`//`
80			`// I/O`
81			`//`
82
83			`//`
84			`// Clock and reset`
85			`//`
86			`input clk;`
87			`input rst;`
88
89			`//`
90			`// I/F for translation`
91			`//`
92			`input tlb_en;`
93			`input [aw-1:0] vaddr;`
94			`output hit;`
95			output [31:`OR1200_IMMU_PS] ppn;
96			`output uxe;`
97			`output sxe;`
98			`output ci;`
99
100			`ifdef OR1200_BIST
101			`//`
102			`// RAM BIST`
103			`//`
104			`input mbist_si_i;`
105			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
106			`output mbist_so_o;`
107			`endif
108
109			`//`
110			`// SPR access`
111			`//`
112			`input spr_cs;`
113			`input spr_write;`
114			`input [31:0] spr_addr;`
115			`input [31:0] spr_dat_i;`
116			`output [31:0] spr_dat_o;`
117
118			`//`
119			`// Internal wires and regs`
120			`//`
121			wire [`OR1200_ITLB_TAG] vpn;
122			`wire v;`
123			wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
124			`wire tlb_mr_en;`
125			`wire tlb_mr_we;`
126			wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
127			wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
128			`wire tlb_tr_en;`
129			`wire tlb_tr_we;`
130			wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
131			wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
132
133			`// BIST`
134			`ifdef OR1200_BIST
135			`wire itlb_mr_ram_si;`
136			`wire itlb_mr_ram_so;`
137			`wire itlb_tr_ram_si;`
138			`wire itlb_tr_ram_so;`
139			`endif
140
141			`//`
142			`// Implemented bits inside match and translate registers`
143			`//`
144			`// itlbwYmrX: vpn 31-19 v 0`
145			`// itlbwYtrX: ppn 31-13 uxe 7 sxe 6`
146			`//`
147			`// itlb memory width:`
148			`// 19 bits for ppn`
149			`// 13 bits for vpn`
150			`// 1 bit for valid`
151			`// 2 bits for protection`
152			`// 1 bit for cache inhibit`
153
154			`//`
155			`// Enable for Match registers`
156			`//`
157			assign tlb_mr_en = tlb_en \| (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
158
159			`//`
160			`// Write enable for Match registers`
161			`//`
162			assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
163
164			`//`
165			`// Enable for Translate registers`
166			`//`
167			assign tlb_tr_en = tlb_en \| (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
168
169			`//`
170			`// Write enable for Translate registers`
171			`//`
172			assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
173
174			`//`
175			`// Output to SPRS unit`
176			`//`
177			assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
178			{vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
179			(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
180			{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
181			`32'h00000000;`
182
183			`//`
184			`// Assign outputs from Match registers`
185			`//`
186			`assign {vpn, v} = tlb_mr_ram_out;`
187
188			`//`
189			`// Assign to Match registers inputs`
190			`//`
191			assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
192
193			`//`
194			`// Assign outputs from Translate registers`
195			`//`
196			`assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;`
197
198			`//`
199			`// Assign to Translate registers inputs`
200			`//`
201			assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
202			spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
203			spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
204			spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
205
206			`//`
207			`// Generate hit`
208			`//`
209			assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
210
211			`//`
212			`// TLB index is normally vaddr[18:13]. If it is SPR access then index is`
213			`// spr_addr[5:0].`
214			`//`
215			assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
216
217
218			`ifdef OR1200_BIST
219			`assign itlb_mr_ram_si = mbist_si_i;`
220			`assign itlb_tr_ram_si = itlb_mr_ram_so;`
221			`assign mbist_so_o = itlb_tr_ram_so;`
222			`endif
223
224
225			`//`
226			`// Instantiation of ITLB Match Registers`
227			`//`
228			`or1200_spram #`
229			`(`
230			`.aw(6),`
231			`.dw(14)`
232			`)`
233			`itlb_mr_ram`
234			`(`
235			`.clk(clk),`
236			`ifdef OR1200_BIST
237			`// RAM BIST`
238			`.mbist_si_i(itlb_mr_ram_si),`
239			`.mbist_so_o(itlb_mr_ram_so),`
240			`.mbist_ctrl_i(mbist_ctrl_i),`
241			`endif
242			`.ce(tlb_mr_en),`
243			`.we(tlb_mr_we),`
244			`//.oe(1'b1),`
245			`.addr(tlb_index),`
246			`.di(tlb_mr_ram_in),`
247			`.doq(tlb_mr_ram_out)`
248	482	julius	`ifdef OR1200_RAM_PARITY
249			`, .p_err()`
250			`endif
251	350	julius	`);`
252
253			`//`
254			`// Instantiation of ITLB Translate Registers`
255			`//`
256			`or1200_spram #`
257			`(`
258			`.aw(6),`
259			`.dw(22)`
260			`)`
261			`itlb_tr_ram`
262			`(`
263			`.clk(clk),`
264			`ifdef OR1200_BIST
265			`// RAM BIST`
266			`.mbist_si_i(itlb_tr_ram_si),`
267			`.mbist_so_o(itlb_tr_ram_so),`
268			`.mbist_ctrl_i(mbist_ctrl_i),`
269			`endif
270			`.ce(tlb_tr_en),`
271			`.we(tlb_tr_we),`
272			`//.oe(1'b1),`
273			`.addr(tlb_index),`
274			`.di(tlb_tr_ram_in),`
275			`.doq(tlb_tr_ram_out)`
276	482	julius	`ifdef OR1200_RAM_PARITY
277			`, .p_err()`
278			`endif
279	350	julius	`);`
280
281			`endmodule`