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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction TLB                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of ITLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Bugs fixed, coding style changed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Insn TLB
//
 
module or1200_immu_tlb(
        // Rst and clk
        clk, rst,
 
        // I/F for translation
        tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
`ifdef OR1200_RAM_PARITY
        // Parity error indicator
        p_err,
`endif
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// I/F for translation
//
input                           tlb_en;
input   [aw-1:0]         vaddr;
output                          hit;
output  [31:`OR1200_IMMU_PS]    ppn;
output                          uxe;
output                          sxe;
output                          ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_RAM_PARITY
output [1:0]                     p_err;
`endif
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [`OR1200_ITLB_TAG]      vpn;
wire                            v;
wire    [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire                            tlb_mr_en;
wire                            tlb_mr_we;
wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_in;
wire                            tlb_tr_en;
wire                            tlb_tr_we;
wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_in;
`ifdef OR1200_RAM_PARITY
wire    [`OR1200_ITLBMRW-1+2:0]  tlb_mr_ram_out;
wire    [`OR1200_ITLBTRW-1+2:0]  tlb_tr_ram_out;
`else
wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_out;
wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_out;
`endif
 
 
// BIST
`ifdef OR1200_BIST
wire                        itlb_mr_ram_si;
wire                        itlb_mr_ram_so;
wire                        itlb_tr_ram_si;
wire                        itlb_tr_ram_so;
`endif
 
`ifdef OR1200_RAM_PARITY
wire [1:0]                       p_err_wire;
reg                             p_err_en;
`endif
 
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19  v 0
// itlbwYtrX: ppn 31-13  uxe 7  sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
            {vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
                (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
            {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
                        32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out[`OR1200_ITLBMRW-1:0];
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG],
                        spr_dat_i[`OR1200_ITLBMR_V_BITS]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out[`OR1200_ITLBTRW-1:0];
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
                        spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
                        spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
                        spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v
`ifdef OR1200_RAM_PARITY
                         & !p_err
`endif
                           ;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] :
                   vaddr[`OR1200_ITLB_INDX];
 
 
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
 
`ifdef OR1200_RAM_PARITY
   always @(posedge clk)
     if (rst)
       p_err_en <= 0;
     else
       p_err_en <= (tlb_mr_en & !tlb_mr_we) | (tlb_tr_en & !tlb_tr_we);
 
   assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) |
                   (tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0;
`endif
 
 
//
// Instantiation of ITLB Match Registers
//
   or1200_spram #
     (
      .aw(6),
 `ifdef OR1200_RAM_PARITY
      .dw(16)
 `else
      .dw(14)
 `endif
      )
   itlb_mr_ram
     (
      .clk(clk),
      .rst(rst),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(itlb_mr_ram_si),
      .mbist_so_o(itlb_mr_ram_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_mr_en),
      .we(tlb_mr_we),
      //.oe(1'b1),
      .addr(tlb_index),
`ifdef OR1200_RAM_PARITY
      .p_err(p_err_wire[0]),
      .di({2'b00,tlb_mr_ram_in}),
`else
      .di(tlb_mr_ram_in),
`endif
      .doq(tlb_mr_ram_out)
      );
 
//
// Instantiation of ITLB Translate Registers
//
   or1200_spram #
     (
      .aw(6),
`ifdef OR1200_RAM_PARITY
      .dw(24)
`else
      .dw(22)
`endif
      )
   itlb_tr_ram
     (
      .clk(clk),
      .rst(rst),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(itlb_tr_ram_si),
      .mbist_so_o(itlb_tr_ram_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_tr_en),
      .we(tlb_tr_we),
      //.oe(1'b1),
      .addr(tlb_index),
`ifdef OR1200_RAM_PARITY
      .p_err(p_err_wire[1]),
      .di({2'b00,tlb_tr_ram_in}),
`else
      .di(tlb_tr_ram_in),
`endif
      .doq(tlb_tr_ram_out)
      );
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction TLB ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of ITLB. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: or1200_immu_tlb.v,v $`
47			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
48			`// Minor update:`
49			`// Bugs fixed, coding style changed.`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "or1200_defines.v"
55
56			`//`
57			`// Insn TLB`
58			`//`
59
60			`module or1200_immu_tlb(`
61			`// Rst and clk`
62			`clk, rst,`
63
64			`// I/F for translation`
65			`tlb_en, vaddr, hit, ppn, uxe, sxe, ci,`
66
67			`ifdef OR1200_BIST
68			`// RAM BIST`
69			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
70			`endif
71
72	483	julius	`ifdef OR1200_RAM_PARITY
73			`// Parity error indicator`
74			`p_err,`
75			`endif
76
77	350	julius	`// SPR access`
78			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
79			`);`
80
81			parameter dw = `OR1200_OPERAND_WIDTH;
82			parameter aw = `OR1200_OPERAND_WIDTH;
83
84			`//`
85			`// I/O`
86			`//`
87
88			`//`
89			`// Clock and reset`
90			`//`
91			`input clk;`
92			`input rst;`
93
94			`//`
95			`// I/F for translation`
96			`//`
97			`input tlb_en;`
98			`input [aw-1:0] vaddr;`
99			`output hit;`
100			output [31:`OR1200_IMMU_PS] ppn;
101			`output uxe;`
102			`output sxe;`
103			`output ci;`
104
105			`ifdef OR1200_BIST
106			`//`
107			`// RAM BIST`
108			`//`
109			`input mbist_si_i;`
110			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
111			`output mbist_so_o;`
112			`endif
113
114	483	julius	`ifdef OR1200_RAM_PARITY
115			`output [1:0] p_err;`
116			`endif
117
118	350	julius	`//`
119			`// SPR access`
120			`//`
121			`input spr_cs;`
122			`input spr_write;`
123			`input [31:0] spr_addr;`
124			`input [31:0] spr_dat_i;`
125			`output [31:0] spr_dat_o;`
126
127			`//`
128			`// Internal wires and regs`
129			`//`
130			wire [`OR1200_ITLB_TAG] vpn;
131			`wire v;`
132			wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
133			`wire tlb_mr_en;`
134			`wire tlb_mr_we;`
135			wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
136			`wire tlb_tr_en;`
137			`wire tlb_tr_we;`
138			wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
139	483	julius	`ifdef OR1200_RAM_PARITY
140			wire [`OR1200_ITLBMRW-1+2:0] tlb_mr_ram_out;
141			wire [`OR1200_ITLBTRW-1+2:0] tlb_tr_ram_out;
142			`else
143			wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
144			wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
145			`endif
146	350	julius
147	483	julius
148	350	julius	`// BIST`
149			`ifdef OR1200_BIST
150			`wire itlb_mr_ram_si;`
151			`wire itlb_mr_ram_so;`
152			`wire itlb_tr_ram_si;`
153			`wire itlb_tr_ram_so;`
154			`endif
155
156	483	julius	`ifdef OR1200_RAM_PARITY
157			`wire [1:0] p_err_wire;`
158			`reg p_err_en;`
159			`endif
160
161	350	julius	`//`
162			`// Implemented bits inside match and translate registers`
163			`//`
164			`// itlbwYmrX: vpn 31-19 v 0`
165			`// itlbwYtrX: ppn 31-13 uxe 7 sxe 6`
166			`//`
167			`// itlb memory width:`
168			`// 19 bits for ppn`
169			`// 13 bits for vpn`
170			`// 1 bit for valid`
171			`// 2 bits for protection`
172			`// 1 bit for cache inhibit`
173
174			`//`
175			`// Enable for Match registers`
176			`//`
177			assign tlb_mr_en = tlb_en \| (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
178
179			`//`
180			`// Write enable for Match registers`
181			`//`
182			assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
183
184			`//`
185			`// Enable for Translate registers`
186			`//`
187			assign tlb_tr_en = tlb_en \| (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
188
189			`//`
190			`// Write enable for Translate registers`
191			`//`
192			assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
193
194			`//`
195			`// Output to SPRS unit`
196			`//`
197			assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
198			{vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
199			(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
200	483	julius	{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
201	350	julius	`32'h00000000;`
202
203			`//`
204			`// Assign outputs from Match registers`
205			`//`
206	483	julius	assign {vpn, v} = tlb_mr_ram_out[`OR1200_ITLBMRW-1:0];
207	350	julius
208			`//`
209			`// Assign to Match registers inputs`
210			`//`
211	483	julius	assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG],
212			spr_dat_i[`OR1200_ITLBMR_V_BITS]};
213	350	julius
214			`//`
215			`// Assign outputs from Translate registers`
216			`//`
217	483	julius	assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out[`OR1200_ITLBTRW-1:0];
218	350	julius
219			`//`
220			`// Assign to Translate registers inputs`
221			`//`
222			assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
223			spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
224			spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
225			spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
226
227			`//`
228			`// Generate hit`
229			`//`
230	483	julius	assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v
231			`ifdef OR1200_RAM_PARITY
232			`& !p_err`
233			`endif
234			`;`
235	350	julius
236			`//`
237			`// TLB index is normally vaddr[18:13]. If it is SPR access then index is`
238			`// spr_addr[5:0].`
239			`//`
240	483	julius	assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] :
241			vaddr[`OR1200_ITLB_INDX];
242	350	julius
243
244			`ifdef OR1200_BIST
245			`assign itlb_mr_ram_si = mbist_si_i;`
246			`assign itlb_tr_ram_si = itlb_mr_ram_so;`
247			`assign mbist_so_o = itlb_tr_ram_so;`
248			`endif
249
250	483	julius	`ifdef OR1200_RAM_PARITY
251			`always @(posedge clk)`
252			`if (rst)`
253			`p_err_en <= 0;`
254			`else`
255			`p_err_en <= (tlb_mr_en & !tlb_mr_we) \| (tlb_tr_en & !tlb_tr_we);`
256	350	julius
257	483	julius	`assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) \|`
258			`(tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0;`
259			`endif
260
261
262	350	julius	`//`
263			`// Instantiation of ITLB Match Registers`
264			`//`
265			`or1200_spram #`
266			`(`
267			`.aw(6),`
268	483	julius	`ifdef OR1200_RAM_PARITY
269			`.dw(16)`
270			`else
271	350	julius	`.dw(14)`
272	483	julius	`endif
273	350	julius	`)`
274			`itlb_mr_ram`
275			`(`
276			`.clk(clk),`
277	483	julius	`.rst(rst),`
278	350	julius	`ifdef OR1200_BIST
279			`// RAM BIST`
280			`.mbist_si_i(itlb_mr_ram_si),`
281			`.mbist_so_o(itlb_mr_ram_so),`
282			`.mbist_ctrl_i(mbist_ctrl_i),`
283			`endif
284			`.ce(tlb_mr_en),`
285			`.we(tlb_mr_we),`
286			`//.oe(1'b1),`
287			`.addr(tlb_index),`
288	483	julius	`ifdef OR1200_RAM_PARITY
289			`.p_err(p_err_wire[0]),`
290			`.di({2'b00,tlb_mr_ram_in}),`
291			`else
292	350	julius	`.di(tlb_mr_ram_in),`
293	483	julius	`endif
294	350	julius	`.doq(tlb_mr_ram_out)`
295			`);`
296
297			`//`
298			`// Instantiation of ITLB Translate Registers`
299			`//`
300			`or1200_spram #`
301			`(`
302			`.aw(6),`
303	483	julius	`ifdef OR1200_RAM_PARITY
304			`.dw(24)`
305			`else
306	350	julius	`.dw(22)`
307	483	julius	`endif
308	350	julius	`)`
309			`itlb_tr_ram`
310			`(`
311			`.clk(clk),`
312	483	julius	`.rst(rst),`
313	350	julius	`ifdef OR1200_BIST
314			`// RAM BIST`
315			`.mbist_si_i(itlb_tr_ram_si),`
316			`.mbist_so_o(itlb_tr_ram_so),`
317			`.mbist_ctrl_i(mbist_ctrl_i),`
318			`endif
319			`.ce(tlb_tr_en),`
320			`.we(tlb_tr_we),`
321			`//.oe(1'b1),`
322			`.addr(tlb_index),`
323	483	julius	`ifdef OR1200_RAM_PARITY
324			`.p_err(p_err_wire[1]),`
325			`.di({2'b00,tlb_tr_ram_in}),`
326			`else
327	350	julius	`.di(tlb_tr_ram_in),`
328	483	julius	`endif
329	350	julius	`.doq(tlb_tr_ram_out)`
330			`);`
331
332			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_tlb.v] - Blame information for rev 483