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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_top.v] - Blame information for rev 415

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1 350 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Instruction MMU top level                          ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6 415 julius
////  http://www.opencores.org/project,or1k                       ////
7 350 julius
////                                                              ////
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////  Description                                                 ////
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////  Instantiation of all IMMU blocks.                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - cache inhibit                                            ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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44
// synopsys translate_off
45
`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
48
 
49
//
50
// Insn MMU
51
//
52
 
53
module or1200_immu_top(
54
        // Rst and clk
55
        clk, rst,
56
 
57
        // CPU i/f
58
        ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
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        icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
60
 
61
        // SR Interface
62
        boot_adr_sel_i,
63
 
64
        // SPR access
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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67
`ifdef OR1200_BIST
68
        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
71
 
72
        // QMEM i/f
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        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
74
);
75
 
76
parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
78
 
79
//
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// I/O
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//
82
 
83
//
84
// Clock and reset
85
//
86
input                           clk;
87
input                           rst;
88
 
89
//
90
// CPU I/F
91
//
92
input                           ic_en;
93
input                           immu_en;
94
input                           supv;
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input   [aw-1:0]         icpu_adr_i;
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input                           icpu_cycstb_i;
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output  [aw-1:0]         icpu_adr_o;
98
output  [3:0]                    icpu_tag_o;
99
output                          icpu_rty_o;
100
output                          icpu_err_o;
101
 
102
//
103
// SR Interface
104
//
105
input                           boot_adr_sel_i;
106
 
107
//
108
// SPR access
109
//
110
input                           spr_cs;
111
input                           spr_write;
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input   [aw-1:0]         spr_addr;
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input   [31:0]                   spr_dat_i;
114
output  [31:0]                   spr_dat_o;
115
 
116
`ifdef OR1200_BIST
117
//
118
// RAM BIST
119
//
120
input mbist_si_i;
121
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
122
output mbist_so_o;
123
`endif
124
 
125
//
126
// IC I/F
127
//
128
input                           qmemimmu_rty_i;
129
input                           qmemimmu_err_i;
130
input   [3:0]                    qmemimmu_tag_i;
131
output  [aw-1:0]         qmemimmu_adr_o;
132
output                          qmemimmu_cycstb_o;
133
output                          qmemimmu_ci_o;
134
 
135
//
136
// Internal wires and regs
137
//
138
wire                            itlb_spr_access;
139
wire    [31:`OR1200_IMMU_PS]    itlb_ppn;
140
wire                            itlb_hit;
141
wire                            itlb_uxe;
142
wire                            itlb_sxe;
143
wire    [31:0]                   itlb_dat_o;
144
wire                            itlb_en;
145
wire                            itlb_ci;
146
wire                            itlb_done;
147
wire                            fault;
148
wire                            miss;
149
wire                            page_cross;
150
reg     [31:0]                   icpu_adr_default;
151
wire    [31:0]                   icpu_adr_boot;
152
reg                             icpu_adr_select;
153
reg             [31:0]           icpu_adr_o;
154
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
155
`ifdef OR1200_NO_IMMU
156
`else
157
reg                             itlb_en_r;
158
reg                             dis_spr_access_frst_clk;
159
reg                             dis_spr_access_scnd_clk;
160
`endif
161
 
162
//
163
// Implemented bits inside match and translate registers
164
//
165
// itlbwYmrX: vpn 31-10  v 0
166
// itlbwYtrX: ppn 31-10  uxe 7  sxe 6
167
//
168
// itlb memory width:
169
// 19 bits for ppn
170
// 13 bits for vpn
171
// 1 bit for valid
172
// 2 bits for protection
173
// 1 bit for cache inhibit
174
 
175
//
176
// icpu_adr_o
177
//
178
`ifdef OR1200_REGISTERED_OUTPUTS
179 358 julius
always @(`OR1200_RST_EVENT rst or posedge clk)
180 350 julius
        // default value 
181 358 julius
        if (rst == `OR1200_RST_VALUE) begin
182 415 julius
                // select async. value due to reset state
183 350 julius
                icpu_adr_default <=  32'h0000_0100;
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                icpu_adr_select  <=  1'b1;
185 350 julius
        end
186 415 julius
        // selected value (different from default) is written 
187
        // into FF after reset state
188 350 julius
        else if (icpu_adr_select) begin
189 415 julius
                // dynamic value can only be assigned to FF out of reset!
190
                icpu_adr_default <=  icpu_adr_boot;
191
                // select FF value 
192
                icpu_adr_select  <=  1'b0;
193 350 julius
        end
194
        else begin
195
                icpu_adr_default <=  icpu_adr_i;
196
        end
197
 
198 415 julius
// select async. value for boot address after reset - PC jumps to the address 
199
// selected after boot! 
200
   //assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : 
201
   // `OR1200_EXCEPT_EPH0_P), 12'h100} ;
202 350 julius
   assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
203
 
204
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
205
        if (icpu_adr_select)
206 415 julius
                // async. value is selected due to reset state 
207
                icpu_adr_o = icpu_adr_boot ;
208 350 julius
        else
209 415 julius
                // FF value is selected 2nd clock after reset state 
210
                icpu_adr_o = icpu_adr_default ;
211 350 julius
`else
212
Unsupported !!!
213
`endif
214
 
215
//
216
// Page cross
217
//
218
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
219
//
220
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
221
 
222
//
223
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is expected to come
224
// one clock cycle after offset part.
225
//
226 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
227
        if (rst == `OR1200_RST_VALUE)
228 350 julius
                icpu_vpn_r <=  {32-`OR1200_IMMU_PS{1'b0}};
229
        else
230
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
231
 
232
`ifdef OR1200_NO_IMMU
233
 
234
//
235
// Put all outputs in inactive state
236
//
237
assign spr_dat_o = 32'h00000000;
238
assign qmemimmu_adr_o = icpu_adr_i;
239
assign icpu_tag_o = qmemimmu_tag_i;
240
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
241
assign icpu_rty_o = qmemimmu_rty_i;
242
assign icpu_err_o = qmemimmu_err_i;
243
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
244
`ifdef OR1200_BIST
245
assign mbist_so_o = mbist_si_i;
246
`endif
247
`else
248
 
249
//
250
// ITLB SPR access
251
//
252
// 1200 - 12FF  itlbmr w0
253
// 1200 - 123F  itlbmr w0 [63:0]
254
//
255
// 1300 - 13FF  itlbtr w0
256
// 1300 - 133F  itlbtr w0 [63:0]
257
//
258
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
259
 
260
//
261
// Disable ITLB SPR access
262
//
263
// This flops are used to mask ITLB miss/fault exception
264
// during first & second clock cycles of accessing ITLB SPR. In
265
// subsequent clock cycles it is assumed that ITLB SPR
266
// access was accomplished and that normal instruction fetching
267
// can proceed.
268
//
269
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
270
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
271
// icpu_rty_o clears it.
272
//
273 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
274
        if (rst == `OR1200_RST_VALUE)
275 350 julius
                dis_spr_access_frst_clk  <=  1'b0;
276
        else if (!icpu_rty_o)
277
                dis_spr_access_frst_clk  <=  1'b0;
278
        else if (spr_cs)
279
                dis_spr_access_frst_clk  <=  1'b1;
280
 
281 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
282
        if (rst == `OR1200_RST_VALUE)
283 350 julius
                dis_spr_access_scnd_clk  <=  1'b0;
284
        else if (!icpu_rty_o)
285
                dis_spr_access_scnd_clk  <=  1'b0;
286
        else if (dis_spr_access_frst_clk)
287
                dis_spr_access_scnd_clk  <=  1'b1;
288
 
289
//
290
// Tags:
291
//
292
// OR1200_ITAG_TE - TLB miss Exception
293
// OR1200_ITAG_PE - Page fault Exception
294
//
295
assign icpu_tag_o = miss ? `OR1200_ITAG_TE : fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
296
 
297
//
298
// icpu_rty_o
299
//
300
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
301
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
302
assign icpu_rty_o = qmemimmu_rty_i;
303
 
304
//
305
// icpu_err_o
306
//
307
assign icpu_err_o = miss | fault | qmemimmu_err_i;
308
 
309
//
310
// Assert itlb_en_r after one clock cycle and when there is no
311
// ITLB SPR access
312
//
313 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
314
        if (rst == `OR1200_RST_VALUE)
315 350 julius
                itlb_en_r <=  1'b0;
316
        else
317
                itlb_en_r <=  itlb_en & ~itlb_spr_access;
318
 
319
//
320
// ITLB lookup successful
321
//
322
assign itlb_done = itlb_en_r & ~page_cross;
323
 
324
//
325
// Cut transfer when access (mtspr/mfspr) to/from ITLB occure or if something goes 
326
// wrong with translation. If IC is disabled, use delayed signals.
327
//
328
// assign qmemimmu_cycstb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cycstb_i & ~page_cross : (miss | fault) ? 1'b0 : icpu_cycstb_i & ~page_cross; // DL
329
//assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done : icpu_cycstb_i & ~page_cross;
330
assign qmemimmu_cycstb_o = immu_en ? ~(miss | fault) & icpu_cycstb_i & ~page_cross & itlb_done & ~itlb_spr_access : icpu_cycstb_i & ~page_cross;
331
 
332
//
333
// Cache Inhibit
334
//
335
// Cache inhibit is not really needed for instruction memory subsystem.
336
// If we would doq it, we would doq it like this.
337
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
338
// However this causes an async combinatorial loop so we stick to
339
// no cache inhibit.
340
//assign qmemimmu_ci_o = `OR1200_IMMU_CI;
341
// Cache inhibit without an async combinatorial loop 
342
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
343
 
344
 
345
//
346
// Physical address is either translated virtual address or
347
// simply equal when IMMU is disabled
348
//
349
//assign qmemimmu_adr_o = itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:0]} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:0]}; // DL: immu_en
350
assign qmemimmu_adr_o = immu_en & itlb_done ? {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} : {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
351
 
352
reg     [31:0]                  spr_dat_reg;
353
//
354
// Output to SPRS unit
355
//
356
// spr_dat_o is registered on the 1st clock of spr read 
357
// so itlb can continue with process during execution of mfspr.
358 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
359
        if (rst == `OR1200_RST_VALUE)
360 350 julius
                spr_dat_reg <=  32'h0000_0000;
361
        else if (spr_cs & !dis_spr_access_scnd_clk)
362
                spr_dat_reg <=  itlb_dat_o;
363
 
364
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
365
 
366
//
367
// Page fault exception logic
368
//
369
assign fault = itlb_done &
370
                        (  (!supv & !itlb_uxe)          // Execute in user mode not enabled
371
                        || (supv & !itlb_sxe));         // Execute in supv mode not enabled
372
 
373
//
374
// TLB Miss exception logic
375
//
376
assign miss = itlb_done & !itlb_hit;
377
 
378
//
379
// ITLB Enable
380
//
381
assign itlb_en = immu_en & icpu_cycstb_i;
382
 
383
//
384
// Instantiation of ITLB
385
//
386
or1200_immu_tlb or1200_immu_tlb(
387
        // Rst and clk
388
        .clk(clk),
389
        .rst(rst),
390
 
391
        // I/F for translation
392
        .tlb_en(itlb_en),
393
        .vaddr(icpu_adr_i),
394
        .hit(itlb_hit),
395
        .ppn(itlb_ppn),
396
        .uxe(itlb_uxe),
397
        .sxe(itlb_sxe),
398
        .ci(itlb_ci),
399
 
400
`ifdef OR1200_BIST
401
        // RAM BIST
402
        .mbist_si_i(mbist_si_i),
403
        .mbist_so_o(mbist_so_o),
404
        .mbist_ctrl_i(mbist_ctrl_i),
405
`endif
406
 
407
        // SPR access
408
        .spr_cs(itlb_spr_access),
409
        .spr_write(spr_write),
410
        .spr_addr(spr_addr),
411
        .spr_dat_i(spr_dat_i),
412
        .spr_dat_o(itlb_dat_o)
413
);
414
 
415
`endif
416
 
417
endmodule

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