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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Instruction MMU top level                          ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all IMMU blocks.                           ////
////                                                              ////
////  To Do:                                                      ////
////   - cache inhibit                                            ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Insn MMU
//
 
module or1200_immu_top(
        // Rst and clk
        clk, rst,
 
        // CPU i/f
        ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,
        icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
 
        // SR Interface
        boot_adr_sel_i,
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
`ifdef OR1200_RAM_PARITY
        // Parity error indicator
        p_err,
`endif
 
        // QMEM i/f
        qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// CPU I/F
//
input                           ic_en;
input                           immu_en;
input                           supv;
input   [aw-1:0]         icpu_adr_i;
input                           icpu_cycstb_i;
output  [aw-1:0]         icpu_adr_o;
output  [3:0]                    icpu_tag_o;
output                          icpu_rty_o;
output                          icpu_err_o;
 
//
// SR Interface
//
input                           boot_adr_sel_i;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [aw-1:0]         spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_RAM_PARITY
output [1:0]                     p_err;
`endif
 
//
// IC I/F
//
input                           qmemimmu_rty_i;
input                           qmemimmu_err_i;
input   [3:0]                    qmemimmu_tag_i;
output  [aw-1:0]         qmemimmu_adr_o;
output                          qmemimmu_cycstb_o;
output                          qmemimmu_ci_o;
 
//
// Internal wires and regs
//
wire                            itlb_spr_access;
wire    [31:`OR1200_IMMU_PS]    itlb_ppn;
wire                            itlb_hit;
wire                            itlb_uxe;
wire                            itlb_sxe;
wire    [31:0]                   itlb_dat_o;
wire                            itlb_en;
wire                            itlb_ci;
wire                            itlb_done;
wire                            fault;
wire                            miss;
wire                            page_cross;
reg     [31:0]                   icpu_adr_default;
wire    [31:0]                   icpu_adr_boot;
reg                             icpu_adr_select;
reg             [31:0]           icpu_adr_o;
reg     [31:`OR1200_IMMU_PS]    icpu_vpn_r;
`ifdef OR1200_NO_IMMU
`else
reg                             itlb_en_r;
reg                             dis_spr_access_frst_clk;
reg                             dis_spr_access_scnd_clk;
`endif
reg     [31:0]                  spr_dat_reg;
 
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-10  v 0
// itlbwYtrX: ppn 31-10  uxe 7  sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
 
 
   assign icpu_adr_boot = `OR1200_BOOT_ADR;
 
//
// icpu_adr_o
//
`ifdef OR1200_REGISTERED_OUTPUTS
always @(`OR1200_RST_EVENT rst or posedge clk)
        // default value 
        if (rst == `OR1200_RST_VALUE) begin
                // select async. value due to reset state
                icpu_adr_o <=  32'h0000_0100;
                icpu_adr_select  <=  1'b1;
        end
        // selected value (different from default) is written 
        // into FF after reset state
        else if (icpu_adr_select) begin
                // dynamic value can only be assigned to FF out of reset!
                icpu_adr_o <=  icpu_adr_boot;
                // select FF value 
                icpu_adr_select  <=  1'b0;
        end
        else begin
                icpu_adr_o <=  icpu_adr_i;
        end
`else
Unsupported !!!
`endif
 
//
// Page cross
//
// Asserted when CPU address crosses page boundary. Most of the time it is zero.
//
assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
 
//
// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is 
// expected to come one clock cycle after offset part.
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                icpu_vpn_r <=  {32-`OR1200_IMMU_PS{1'b0}};
        else
                icpu_vpn_r <=  icpu_adr_i[31:`OR1200_IMMU_PS];
 
`ifdef OR1200_NO_IMMU
 
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemimmu_adr_o = icpu_adr_i;
assign icpu_tag_o = qmemimmu_tag_i;
assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;
assign icpu_rty_o = qmemimmu_rty_i;
assign icpu_err_o = qmemimmu_err_i;
assign qmemimmu_ci_o = `OR1200_IMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`ifdef OR1200_RAM_PARITY
assign p_err = 0;
`endif
 
`else
 
//
// ITLB SPR access
//
// 1200 - 12FF  itlbmr w0
// 1200 - 123F  itlbmr w0 [63:0]
//
// 1300 - 13FF  itlbtr w0
// 1300 - 133F  itlbtr w0 [63:0]
//
assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;
 
//
// Disable ITLB SPR access
//
// This flops are used to mask ITLB miss/fault exception
// during first & second clock cycles of accessing ITLB SPR. In
// subsequent clock cycles it is assumed that ITLB SPR
// access was accomplished and that normal instruction fetching
// can proceed.
//
// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.
// dis_spr_access_frst_clk  sets dis_spr_access_scnd_clk and 
// icpu_rty_o clears it.
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                dis_spr_access_frst_clk  <=  1'b0;
        else if (!icpu_rty_o)
                dis_spr_access_frst_clk  <=  1'b0;
        else if (spr_cs)
                dis_spr_access_frst_clk  <=  1'b1;
 
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                dis_spr_access_scnd_clk  <=  1'b0;
        else if (!icpu_rty_o)
                dis_spr_access_scnd_clk  <=  1'b0;
        else if (dis_spr_access_frst_clk)
                dis_spr_access_scnd_clk  <=  1'b1;
 
//
// Tags:
//
// OR1200_ITAG_TE - TLB miss Exception
// OR1200_ITAG_PE - Page fault Exception
//
assign icpu_tag_o = miss ? `OR1200_ITAG_TE :
                    fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
 
//
// icpu_rty_o
//
// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;
//assign icpu_rty_o = qmemimmu_rty_i | itlb_spr_access & immu_en;
assign icpu_rty_o = qmemimmu_rty_i;
 
//
// icpu_err_o
//
assign icpu_err_o = miss | fault | qmemimmu_err_i
 `ifdef OR1200_RAM_PARITY
                    | (|p_err)
 `endif
                               ;
 
//
// Assert itlb_en_r after one clock cycle and when there is no
// ITLB SPR access
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                itlb_en_r <=  1'b0;
        else
                itlb_en_r <= itlb_en & ~itlb_spr_access;
 
//
// ITLB lookup successful
//
assign itlb_done = itlb_en_r & ~page_cross;
 
//
// Cut transfer when access (mtspr/mfspr) to/from ITLB occurs or if something 
// goes wrong with translation. If IC is disabled, use delayed signals.
//
assign qmemimmu_cycstb_o = immu_en ?
                           ~(miss | fault) & icpu_cycstb_i & ~page_cross &
                           itlb_done & ~itlb_spr_access :
                           icpu_cycstb_i & ~page_cross;
 
//
// Cache Inhibit
//
// Cache inhibit is not really needed for instruction memory subsystem.
// If we would doq it, we would doq it like this.
// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
// However this causes an async combinatorial loop so we stick to
// no cache inhibit.
assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
 
 
//
// Physical address is either translated virtual address or
// simply equal when IMMU is disabled
//
assign qmemimmu_adr_o = immu_en & itlb_done ?
                        {itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} :
                        {icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
 
//
// Output to SPRS unit
//
// spr_dat_o is registered on the 1st clock of spr read 
// so itlb can continue with process during execution of mfspr.
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                spr_dat_reg <=  32'h0000_0000;
        else if (spr_cs & !dis_spr_access_scnd_clk)
                spr_dat_reg <=  itlb_dat_o;
 
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;
 
//
// Page fault exception logic
//
assign fault = itlb_done &
                        ((!supv & !itlb_uxe) // Execute in user mode not enabled
                        || (supv & !itlb_sxe));// Execute in supv mode not en.
 
//
// TLB Miss exception logic
//
assign miss = itlb_done & !itlb_hit;
 
//
// ITLB Enable
//
assign itlb_en = immu_en & icpu_cycstb_i;
 
//
// Instantiation of ITLB
//
or1200_immu_tlb or1200_immu_tlb(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // I/F for translation
        .tlb_en(itlb_en),
        .vaddr(icpu_adr_i),
        .hit(itlb_hit),
        .ppn(itlb_ppn),
        .uxe(itlb_uxe),
        .sxe(itlb_sxe),
        .ci(itlb_ci),
 
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
 
`ifdef OR1200_RAM_PARITY
        .p_err(p_err),
`endif
 
        // SPR access
        .spr_cs(itlb_spr_access),
        .spr_write(spr_write),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_i),
        .spr_dat_o(itlb_dat_o)
);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Instruction MMU top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6	415	julius	`//// http://www.opencores.org/project,or1k ////`
7	350	julius	`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all IMMU blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - cache inhibit ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43
44			`// synopsys translate_off`
45			`include "timescale.v"
46			`// synopsys translate_on`
47			`include "or1200_defines.v"
48
49			`//`
50			`// Insn MMU`
51			`//`
52
53			`module or1200_immu_top(`
54			`// Rst and clk`
55			`clk, rst,`
56
57			`// CPU i/f`
58			`ic_en, immu_en, supv, icpu_adr_i, icpu_cycstb_i,`
59			`icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,`
60
61			`// SR Interface`
62			`boot_adr_sel_i,`
63
64			`// SPR access`
65			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
66
67			`ifdef OR1200_BIST
68			`// RAM BIST`
69			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
70			`endif
71
72	483	julius	`ifdef OR1200_RAM_PARITY
73			`// Parity error indicator`
74			`p_err,`
75			`endif
76
77	350	julius	`// QMEM i/f`
78			`qmemimmu_rty_i, qmemimmu_err_i, qmemimmu_tag_i, qmemimmu_adr_o, qmemimmu_cycstb_o, qmemimmu_ci_o`
79			`);`
80
81			parameter dw = `OR1200_OPERAND_WIDTH;
82			parameter aw = `OR1200_OPERAND_WIDTH;
83
84			`//`
85			`// I/O`
86			`//`
87
88			`//`
89			`// Clock and reset`
90			`//`
91			`input clk;`
92			`input rst;`
93
94			`//`
95			`// CPU I/F`
96			`//`
97			`input ic_en;`
98			`input immu_en;`
99			`input supv;`
100			`input [aw-1:0] icpu_adr_i;`
101			`input icpu_cycstb_i;`
102			`output [aw-1:0] icpu_adr_o;`
103			`output [3:0] icpu_tag_o;`
104			`output icpu_rty_o;`
105			`output icpu_err_o;`
106
107			`//`
108			`// SR Interface`
109			`//`
110			`input boot_adr_sel_i;`
111
112			`//`
113			`// SPR access`
114			`//`
115			`input spr_cs;`
116			`input spr_write;`
117			`input [aw-1:0] spr_addr;`
118			`input [31:0] spr_dat_i;`
119			`output [31:0] spr_dat_o;`
120
121			`ifdef OR1200_BIST
122			`//`
123			`// RAM BIST`
124			`//`
125			`input mbist_si_i;`
126			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
127			`output mbist_so_o;`
128			`endif
129
130	483	julius	`ifdef OR1200_RAM_PARITY
131			`output [1:0] p_err;`
132			`endif
133
134	350	julius	`//`
135			`// IC I/F`
136			`//`
137			`input qmemimmu_rty_i;`
138			`input qmemimmu_err_i;`
139			`input [3:0] qmemimmu_tag_i;`
140			`output [aw-1:0] qmemimmu_adr_o;`
141			`output qmemimmu_cycstb_o;`
142			`output qmemimmu_ci_o;`
143
144			`//`
145			`// Internal wires and regs`
146			`//`
147			`wire itlb_spr_access;`
148			wire [31:`OR1200_IMMU_PS] itlb_ppn;
149			`wire itlb_hit;`
150			`wire itlb_uxe;`
151			`wire itlb_sxe;`
152			`wire [31:0] itlb_dat_o;`
153			`wire itlb_en;`
154			`wire itlb_ci;`
155			`wire itlb_done;`
156			`wire fault;`
157			`wire miss;`
158			`wire page_cross;`
159			`reg [31:0] icpu_adr_default;`
160			`wire [31:0] icpu_adr_boot;`
161			`reg icpu_adr_select;`
162			`reg [31:0] icpu_adr_o;`
163			reg [31:`OR1200_IMMU_PS] icpu_vpn_r;
164			`ifdef OR1200_NO_IMMU
165			`else
166			`reg itlb_en_r;`
167			`reg dis_spr_access_frst_clk;`
168			`reg dis_spr_access_scnd_clk;`
169			`endif
170	483	julius	`reg [31:0] spr_dat_reg;`
171
172	350	julius	`//`
173			`// Implemented bits inside match and translate registers`
174			`//`
175			`// itlbwYmrX: vpn 31-10 v 0`
176			`// itlbwYtrX: ppn 31-10 uxe 7 sxe 6`
177			`//`
178			`// itlb memory width:`
179			`// 19 bits for ppn`
180			`// 13 bits for vpn`
181			`// 1 bit for valid`
182			`// 2 bits for protection`
183			`// 1 bit for cache inhibit`
184
185	483	julius
186			assign icpu_adr_boot = `OR1200_BOOT_ADR;
187
188	350	julius	`//`
189			`// icpu_adr_o`
190			`//`
191			`ifdef OR1200_REGISTERED_OUTPUTS
192	358	julius	always @(`OR1200_RST_EVENT rst or posedge clk)
193	350	julius	`// default value`
194	358	julius	if (rst == `OR1200_RST_VALUE) begin
195	415	julius	`// select async. value due to reset state`
196	483	julius	`icpu_adr_o <= 32'h0000_0100;`
197	415	julius	`icpu_adr_select <= 1'b1;`
198	350	julius	`end`
199	415	julius	`// selected value (different from default) is written`
200			`// into FF after reset state`
201	350	julius	`else if (icpu_adr_select) begin`
202	415	julius	`// dynamic value can only be assigned to FF out of reset!`
203	483	julius	`icpu_adr_o <= icpu_adr_boot;`
204	415	julius	`// select FF value`
205			`icpu_adr_select <= 1'b0;`
206	350	julius	`end`
207			`else begin`
208	483	julius	`icpu_adr_o <= icpu_adr_i;`
209	350	julius	`end`
210			`else
211			`Unsupported !!!`
212			`endif
213
214			`//`
215			`// Page cross`
216			`//`
217			`// Asserted when CPU address crosses page boundary. Most of the time it is zero.`
218			`//`
219			assign page_cross = icpu_adr_i[31:`OR1200_IMMU_PS] != icpu_vpn_r;
220
221			`//`
222	483	julius	`// Register icpu_adr_i's VPN for use when IMMU is not enabled but PPN is`
223			`// expected to come one clock cycle after offset part.`
224	350	julius	`//`
225	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
226			if (rst == `OR1200_RST_VALUE)
227	350	julius	icpu_vpn_r <= {32-`OR1200_IMMU_PS{1'b0}};
228			`else`
229			icpu_vpn_r <= icpu_adr_i[31:`OR1200_IMMU_PS];
230
231			`ifdef OR1200_NO_IMMU
232
233			`//`
234			`// Put all outputs in inactive state`
235			`//`
236			`assign spr_dat_o = 32'h00000000;`
237			`assign qmemimmu_adr_o = icpu_adr_i;`
238			`assign icpu_tag_o = qmemimmu_tag_i;`
239			`assign qmemimmu_cycstb_o = icpu_cycstb_i & ~page_cross;`
240			`assign icpu_rty_o = qmemimmu_rty_i;`
241			`assign icpu_err_o = qmemimmu_err_i;`
242			assign qmemimmu_ci_o = `OR1200_IMMU_CI;
243			`ifdef OR1200_BIST
244			`assign mbist_so_o = mbist_si_i;`
245			`endif
246	483	julius	`ifdef OR1200_RAM_PARITY
247			`assign p_err = 0;`
248			`endif
249
250	350	julius	`else
251
252			`//`
253			`// ITLB SPR access`
254			`//`
255			`// 1200 - 12FF itlbmr w0`
256			`// 1200 - 123F itlbmr w0 [63:0]`
257			`//`
258			`// 1300 - 13FF itlbtr w0`
259			`// 1300 - 133F itlbtr w0 [63:0]`
260			`//`
261			`assign itlb_spr_access = spr_cs & ~dis_spr_access_scnd_clk;`
262
263			`//`
264			`// Disable ITLB SPR access`
265			`//`
266			`// This flops are used to mask ITLB miss/fault exception`
267			`// during first & second clock cycles of accessing ITLB SPR. In`
268			`// subsequent clock cycles it is assumed that ITLB SPR`
269			`// access was accomplished and that normal instruction fetching`
270			`// can proceed.`
271			`//`
272			`// spr_cs sets dis_spr_access_frst_clk and icpu_rty_o clears it.`
273			`// dis_spr_access_frst_clk sets dis_spr_access_scnd_clk and`
274			`// icpu_rty_o clears it.`
275			`//`
276	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
277			if (rst == `OR1200_RST_VALUE)
278	350	julius	`dis_spr_access_frst_clk <= 1'b0;`
279			`else if (!icpu_rty_o)`
280			`dis_spr_access_frst_clk <= 1'b0;`
281			`else if (spr_cs)`
282			`dis_spr_access_frst_clk <= 1'b1;`
283
284	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
285			if (rst == `OR1200_RST_VALUE)
286	350	julius	`dis_spr_access_scnd_clk <= 1'b0;`
287			`else if (!icpu_rty_o)`
288			`dis_spr_access_scnd_clk <= 1'b0;`
289			`else if (dis_spr_access_frst_clk)`
290			`dis_spr_access_scnd_clk <= 1'b1;`
291
292			`//`
293			`// Tags:`
294			`//`
295			`// OR1200_ITAG_TE - TLB miss Exception`
296			`// OR1200_ITAG_PE - Page fault Exception`
297			`//`
298	483	julius	assign icpu_tag_o = miss ? `OR1200_ITAG_TE :
299			fault ? `OR1200_ITAG_PE : qmemimmu_tag_i;
300	350	julius
301			`//`
302			`// icpu_rty_o`
303			`//`
304			`// assign icpu_rty_o = !icpu_err_o & qmemimmu_rty_i;`
305			`//assign icpu_rty_o = qmemimmu_rty_i \| itlb_spr_access & immu_en;`
306			`assign icpu_rty_o = qmemimmu_rty_i;`
307
308			`//`
309			`// icpu_err_o`
310			`//`
311	483	julius	`assign icpu_err_o = miss \| fault \| qmemimmu_err_i`
312			`ifdef OR1200_RAM_PARITY
313			`\| (\|p_err)`
314			`endif
315			`;`
316	350	julius
317			`//`
318			`// Assert itlb_en_r after one clock cycle and when there is no`
319			`// ITLB SPR access`
320			`//`
321	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
322			if (rst == `OR1200_RST_VALUE)
323	350	julius	`itlb_en_r <= 1'b0;`
324			`else`
325	483	julius	`itlb_en_r <= itlb_en & ~itlb_spr_access;`
326	350	julius
327			`//`
328			`// ITLB lookup successful`
329			`//`
330			`assign itlb_done = itlb_en_r & ~page_cross;`
331
332			`//`
333	483	julius	`// Cut transfer when access (mtspr/mfspr) to/from ITLB occurs or if something`
334			`// goes wrong with translation. If IC is disabled, use delayed signals.`
335	350	julius	`//`
336	483	julius	`assign qmemimmu_cycstb_o = immu_en ?`
337			`~(miss \| fault) & icpu_cycstb_i & ~page_cross &`
338			`itlb_done & ~itlb_spr_access :`
339			`icpu_cycstb_i & ~page_cross;`
340	350	julius
341			`//`
342			`// Cache Inhibit`
343			`//`
344			`// Cache inhibit is not really needed for instruction memory subsystem.`
345			`// If we would doq it, we would doq it like this.`
346			// assign qmemimmu_ci_o = immu_en ? itlb_done & itlb_ci : `OR1200_IMMU_CI;
347			`// However this causes an async combinatorial loop so we stick to`
348			`// no cache inhibit.`
349			assign qmemimmu_ci_o = immu_en ? itlb_ci : `OR1200_IMMU_CI;
350
351
352			`//`
353			`// Physical address is either translated virtual address or`
354			`// simply equal when IMMU is disabled`
355			`//`
356	483	julius	`assign qmemimmu_adr_o = immu_en & itlb_done ?`
357			{itlb_ppn, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0} :
358			{icpu_vpn_r, icpu_adr_i[`OR1200_IMMU_PS-1:2], 2'h0};
359	350	julius
360			`//`
361			`// Output to SPRS unit`
362			`//`
363			`// spr_dat_o is registered on the 1st clock of spr read`
364			`// so itlb can continue with process during execution of mfspr.`
365	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
366			if (rst == `OR1200_RST_VALUE)
367	350	julius	`spr_dat_reg <= 32'h0000_0000;`
368			`else if (spr_cs & !dis_spr_access_scnd_clk)`
369			`spr_dat_reg <= itlb_dat_o;`
370
371			`assign spr_dat_o = itlb_spr_access ? itlb_dat_o : spr_dat_reg;`
372
373			`//`
374			`// Page fault exception logic`
375			`//`
376			`assign fault = itlb_done &`
377	483	julius	`((!supv & !itlb_uxe) // Execute in user mode not enabled`
378			`\|\| (supv & !itlb_sxe));// Execute in supv mode not en.`
379	350	julius
380			`//`
381			`// TLB Miss exception logic`
382			`//`
383			`assign miss = itlb_done & !itlb_hit;`
384
385			`//`
386			`// ITLB Enable`
387			`//`
388			`assign itlb_en = immu_en & icpu_cycstb_i;`
389
390			`//`
391			`// Instantiation of ITLB`
392			`//`
393			`or1200_immu_tlb or1200_immu_tlb(`
394			`// Rst and clk`
395			`.clk(clk),`
396			`.rst(rst),`
397
398			`// I/F for translation`
399			`.tlb_en(itlb_en),`
400			`.vaddr(icpu_adr_i),`
401			`.hit(itlb_hit),`
402			`.ppn(itlb_ppn),`
403			`.uxe(itlb_uxe),`
404			`.sxe(itlb_sxe),`
405			`.ci(itlb_ci),`
406
407			`ifdef OR1200_BIST
408			`// RAM BIST`
409			`.mbist_si_i(mbist_si_i),`
410			`.mbist_so_o(mbist_so_o),`
411			`.mbist_ctrl_i(mbist_ctrl_i),`
412			`endif
413
414	483	julius	`ifdef OR1200_RAM_PARITY
415			`.p_err(p_err),`
416			`endif
417
418	350	julius	`// SPR access`
419			`.spr_cs(itlb_spr_access),`
420			`.spr_write(spr_write),`
421			`.spr_addr(spr_addr),`
422			`.spr_dat_i(spr_dat_i),`
423			`.spr_dat_o(itlb_dat_o)`
424			`);`
425
426			`endif
427
428			`endmodule`

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