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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_rf.v] - Blame information for rev 584

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1 350 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's register file inside CPU                           ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/project,or1k                       ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of register file memories                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// $Log: or1200_rf.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update: 
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// Bugs fixed, coding style changed. 
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_rf(
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        // Clock and reset
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        clk, rst,
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59
        // Write i/f
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        cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
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62
        // Read i/f
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        id_freeze, addra, addrb, dataa, datab, rda, rdb,
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65
        // Debug
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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//
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// Write i/f
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//
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input                           cy_we_i;
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output                          cy_we_o;
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input                           supv;
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input                           wb_freeze;
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input   [aw-1:0]         addrw;
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input   [dw-1:0]         dataw;
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input                           we;
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input                           flushpipe;
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94
//
95
// Read i/f
96
//
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input                           id_freeze;
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input   [aw-1:0]         addra;
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input   [aw-1:0]         addrb;
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output  [dw-1:0]         dataa;
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output  [dw-1:0]         datab;
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input                           rda;
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input                           rdb;
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//
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// SPR access for debugging purposes
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//
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input                           spr_cs;
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input                           spr_write;
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input   [31:0]                   spr_addr;
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input   [31:0]                   spr_dat_i;
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output  [31:0]                   spr_dat_o;
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input                           du_read;
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115
//
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// Internal wires and regs
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//
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wire    [dw-1:0]         from_rfa;
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wire    [dw-1:0]         from_rfb;
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wire    [aw-1:0]         rf_addra;
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wire    [aw-1:0]         rf_addrw;
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wire    [dw-1:0]         rf_dataw;
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wire                            rf_we;
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wire                            spr_valid;
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wire                            rf_ena;
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wire                            rf_enb;
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reg                             rf_we_allow;
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129
   // Logic to restore output on RFA after debug unit has read out via SPR if.
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   // Problem was that the incorrect output would be on RFA after debug unit
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   // had read out  - this is bad if that output is relied upon by execute
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   // stage for next instruction. We simply save the last address for rf A and
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   // and re-read it whenever the SPR select goes low, so we must remember
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   // the last address and generate a signal for falling edge of SPR cs.
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   // -- Julius
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137
   // Detect falling edge of SPR select 
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   reg                          spr_du_cs;
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   wire                         spr_cs_fe;
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   // Track RF A's address each time it's enabled
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   reg  [aw-1:0]         addra_last;
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143
 
144
   always @(posedge clk)
145
     if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
146
       addra_last <= addra;
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148
   always @(posedge clk)
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     spr_du_cs <= spr_cs & du_read;
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151
   assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
152
 
153
 
154
//
155
// SPR access is valid when spr_cs is asserted and
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// SPR address matches GPR addresses
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//
158
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
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//
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// SPR data output is always from RF A
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//
163
assign spr_dat_o = from_rfa;
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165
//
166
// Operand A comes from RF or from saved A register
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//
168
assign dataa = from_rfa;
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//
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// Operand B comes from RF or from saved B register
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//
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assign datab = from_rfb;
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175
//
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// RF A read address is either from SPRS or normal from CPU control
177
//
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assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
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                  spr_cs_fe ? addra_last : addra;
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//
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// RF write address is either from SPRS or normal from CPU control
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//
184
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
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186
//
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// RF write data is either from SPRS or normal from CPU datapath
188
//
189
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
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191
//
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// RF write enable is either from SPRS or normal from CPU control
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//
194 358 julius
always @(`OR1200_RST_EVENT rst or posedge clk)
195
        if (rst == `OR1200_RST_VALUE)
196 350 julius
                rf_we_allow <=  1'b1;
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        else if (~wb_freeze)
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                rf_we_allow <=  ~flushpipe;
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assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
201 504 julius
 
202 350 julius
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
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//
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// CS RF A asserted when instruction reads operand A and ID stage
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// is not stalled
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//
208 504 julius
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
209 350 julius
 
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//
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// CS RF B asserted when instruction reads operand B and ID stage
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// is not stalled
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//
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assign rf_enb = rdb & ~id_freeze;
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`ifdef OR1200_RFRAM_TWOPORT
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//
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// Instantiation of register file two-port RAM A
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//
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or1200_tpram_32x32 rf_a(
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        // Port A
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        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_ena),
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        .we_a(1'b0),
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        .oe_a(1'b1),
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        .addr_a(rf_addra),
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        .di_a(32'h0000_0000),
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        .do_a(from_rfa),
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        // Port B
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        .clk_b(clk),
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        .rst_b(rst),
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        .ce_b(rf_we),
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        .we_b(rf_we),
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        .oe_b(1'b0),
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        .addr_b(rf_addrw),
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        .di_b(rf_dataw),
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        .do_b()
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);
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//
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// Instantiation of register file two-port RAM B
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//
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or1200_tpram_32x32 rf_b(
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        // Port A
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        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_enb),
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        .we_a(1'b0),
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        .oe_a(1'b1),
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        .addr_a(addrb),
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        .di_a(32'h0000_0000),
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        .do_a(from_rfb),
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        // Port B
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        .clk_b(clk),
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        .rst_b(rst),
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        .ce_b(rf_we),
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        .we_b(rf_we),
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        .oe_b(1'b0),
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        .addr_b(rf_addrw),
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        .di_b(rf_dataw),
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        .do_b()
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);
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`else
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`ifdef OR1200_RFRAM_DUALPORT
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//
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// Instantiation of register file two-port RAM A
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//
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   or1200_dpram #
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     (
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      .aw(5),
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      .dw(32)
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      )
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   rf_a
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     (
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      // Port A
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      .clk_a(clk),
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      .ce_a(rf_ena),
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      .addr_a(rf_addra),
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      .do_a(from_rfa),
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      // Port B
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      .clk_b(clk),
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      .ce_b(rf_we),
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      .we_b(rf_we),
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      .addr_b(rf_addrw),
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      .di_b(rf_dataw)
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      );
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   //
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   // Instantiation of register file two-port RAM B
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   //
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   or1200_dpram #
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     (
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      .aw(5),
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      .dw(32)
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      )
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   rf_b
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     (
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      // Port A
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      .clk_a(clk),
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      .ce_a(rf_enb),
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      .addr_a(addrb),
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      .do_a(from_rfb),
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      // Port B
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      .clk_b(clk),
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      .ce_b(rf_we),
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      .we_b(rf_we),
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      .addr_b(rf_addrw),
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      .di_b(rf_dataw)
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      );
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320
`else
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322
`ifdef OR1200_RFRAM_GENERIC
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324
//
325
// Instantiation of generic (flip-flop based) register file
326
//
327
or1200_rfram_generic rf_a(
328
        // Clock and reset
329
        .clk(clk),
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        .rst(rst),
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332
        // Port A
333
        .ce_a(rf_ena),
334
        .addr_a(rf_addra),
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        .do_a(from_rfa),
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337
        // Port B
338
        .ce_b(rf_enb),
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        .addr_b(addrb),
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        .do_b(from_rfb),
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342
        // Port W
343
        .ce_w(rf_we),
344
        .we_w(rf_we),
345
        .addr_w(rf_addrw),
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        .di_w(rf_dataw)
347
);
348
 
349
`else
350
 
351
//
352
// RFRAM type not specified
353
//
354
initial begin
355
        $display("Define RFRAM type.");
356
        $finish;
357
end
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359
`endif
360
`endif
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`endif
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endmodule

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