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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// New 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram
  (
`ifdef OR1200_BIST
   // RAM BIST
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
   // Generic synchronous single-port RAM interface
   clk, rst, ce, we, addr, di, doq
`ifdef OR1200_RAM_PARITY
   , p_err
`endif
   );
 
   //
   // Default address and data buses width
   //
   parameter aw = 10;
   parameter dw = 32;
 
`ifdef OR1200_BIST
   //
   // RAM BIST
   //
   input mbist_si_i;
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
   output                                 mbist_so_o;
`endif
 
   //
   // Generic synchronous single-port RAM interface
   //
   input                                  clk;  // Clock
   input                                  rst; // Reset
   input                                  ce;   // Chip enable input
   input                                  we;   // Write enable input
   input [aw-1:0]                          addr; // address bus inputs
   input [dw-1:0]                          di;   // input data bus
   output [dw-1:0]                         doq;  // output data bus
`ifdef OR1200_RAM_PARITY
   output                                 p_err; // parity error indicator
`endif
 
   //
   // Internal wires and registers
   //
 
   //
   // Generic single-port synchronous RAM model
   //
 
   //
   // Generic RAM's registers and wires
   //
`ifdef OR1200_RAM_PARITY
   parameter par_w = (dw/8);
   reg [(dw+par_w)-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
   reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`endif
 
   reg [aw-1:0] addr_reg;                // RAM address register
 
`ifdef OR1200_RAM_PARITY
   wire [(dw+par_w)-1:0]         doq_wire;
   wire [par_w-1:0]              di_p;
   wire [par_w-1:0]              do_p;
   wire [par_w-1:0]              parity_err;
   reg                          ce_r;
`else
   wire [dw-1:0]                 doq_wire;
`endif
 
`ifdef OR1200_RAM_PARITY
   genvar                       i;
   generate
      for (i=0;i<par_w;i=i+1) begin: paritygen
         or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
         or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
                                .p_i(do_p[i]), .err_o(parity_err[i]));
      end
   endgenerate
 
   // Extract parity bits of data out
   assign do_p = doq_wire[(dw+par_w)-1:dw];
 
   always @(posedge clk)
     if (rst)
       ce_r <= 0;
     else
       ce_r <= ce;
 
   // Indicate error
   assign p_err = (|parity_err) & ce_r;
 
   // Inject a parity error.
   task gen_parity_err;
      input [aw-1:0]             addr;
      input [31:0]               parity_bit_no;
      input [31:0]               data_bit_no;
      reg [(dw+par_w)-1:0]       do_temp;
      begin
         do_temp = mem[addr];
         // Switch parity bit
         if (parity_bit_no >= 0 && parity_bit_no < par_w)
           do_temp[dw+parity_bit_no] = ~do_temp[dw+parity_bit_no];
         // Switch data bit
         if (data_bit_no >= 0 && data_bit_no < dw)
           do_temp[data_bit_no] = ~do_temp[data_bit_no];
         // Write word back
         mem[addr] = do_temp;
      end
   endtask // gen_parity_err
`endif
 
 
   //
   // Data output drivers
   //
   assign doq_wire = mem[addr_reg];
   assign doq = doq_wire[dw-1:0];
 
   //
   // RAM read address register
   //
   always @(posedge clk)
     if (ce)
       addr_reg <=  addr;
 
   //
   // RAM write
   //
   always @(posedge clk)
`ifdef OR1200_RAM_PARITY
     if (we && ce)
       mem[addr] <=  {di_p,di};
`else
     if (we && ce)
       mem[addr] <=  di;
`endif
 
endmodule // or1200_spram

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Michael Unneback, unneback@opencores.org ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from http://www.opencores.org/lgpl.shtml ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`// CVS Revision History`
49			`//`
50			`// $Log: or1200_dpram_32x32.v,v $`
51			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
52			`// New`
53			`//`
54
55			`// synopsys translate_off`
56			`include "timescale.v"
57			`// synopsys translate_on`
58			`include "or1200_defines.v"
59
60			`module or1200_spram`
61			`(`
62			`ifdef OR1200_BIST
63			`// RAM BIST`
64			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
65			`endif
66			`// Generic synchronous single-port RAM interface`
67	483	julius	`clk, rst, ce, we, addr, di, doq`
68	482	julius	`ifdef OR1200_RAM_PARITY
69			`, p_err`
70			`endif
71	350	julius	`);`
72
73			`//`
74			`// Default address and data buses width`
75			`//`
76			`parameter aw = 10;`
77			`parameter dw = 32;`
78
79			`ifdef OR1200_BIST
80			`//`
81			`// RAM BIST`
82			`//`
83			`input mbist_si_i;`
84			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
85	482	julius	`output mbist_so_o;`
86	350	julius	`endif
87
88			`//`
89			`// Generic synchronous single-port RAM interface`
90			`//`
91			`input clk; // Clock`
92	483	julius	`input rst; // Reset`
93	350	julius	`input ce; // Chip enable input`
94			`input we; // Write enable input`
95			`input [aw-1:0] addr; // address bus inputs`
96			`input [dw-1:0] di; // input data bus`
97			`output [dw-1:0] doq; // output data bus`
98	482	julius	`ifdef OR1200_RAM_PARITY
99			`output p_err; // parity error indicator`
100			`endif
101	350	julius
102			`//`
103			`// Internal wires and registers`
104			`//`
105
106			`//`
107			`// Generic single-port synchronous RAM model`
108			`//`
109
110			`//`
111			`// Generic RAM's registers and wires`
112			`//`
113	482	julius	`ifdef OR1200_RAM_PARITY
114	483	julius	`parameter par_w = (dw/8);`
115			`reg [(dw+par_w)-1:0] mem [(1<<aw)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
116	482	julius	`else
117	483	julius	`reg [dw-1:0] mem [(1<<aw)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
118	482	julius	`endif
119
120	483	julius	`reg [aw-1:0] addr_reg; // RAM address register`
121	482	julius
122			`ifdef OR1200_RAM_PARITY
123	483	julius	`wire [(dw+par_w)-1:0] doq_wire;`
124			`wire [par_w-1:0] di_p;`
125			`wire [par_w-1:0] do_p;`
126			`wire [par_w-1:0] parity_err;`
127			`reg ce_r;`
128	350	julius	`else
129	482	julius	`wire [dw-1:0] doq_wire;`
130	350	julius	`endif
131	482	julius
132			`ifdef OR1200_RAM_PARITY
133			`genvar i;`
134			`generate`
135	483	julius	`for (i=0;i<par_w;i=i+1) begin: paritygen`
136	482	julius	`or1200_parity_gen pgen(.d_i(di[(i8)+7:(i8)]), .p_o(di_p[i]));`
137			`or1200_parity_chk pchk(.d_i(doq_wire[(i8)+7:(i8)]),`
138			`.p_i(do_p[i]), .err_o(parity_err[i]));`
139			`end`
140			`endgenerate`
141
142			`// Extract parity bits of data out`
143	483	julius	`assign do_p = doq_wire[(dw+par_w)-1:dw];`
144
145			`always @(posedge clk)`
146			`if (rst)`
147			`ce_r <= 0;`
148			`else`
149			`ce_r <= ce;`
150
151			`// Indicate error`
152			`assign p_err = (\|parity_err) & ce_r;`
153	350	julius
154	483	julius	`// Inject a parity error.`
155	482	julius	`task gen_parity_err;`
156	483	julius	`input [aw-1:0] addr;`
157	482	julius	`input [31:0] parity_bit_no;`
158			`input [31:0] data_bit_no;`
159	483	julius	`reg [(dw+par_w)-1:0] do_temp;`
160	482	julius	`begin`
161	483	julius	`do_temp = mem[addr];`
162	482	julius	`// Switch parity bit`
163	483	julius	`if (parity_bit_no >= 0 && parity_bit_no < par_w)`
164			`do_temp[dw+parity_bit_no] = ~do_temp[dw+parity_bit_no];`
165	482	julius	`// Switch data bit`
166	483	julius	`if (data_bit_no >= 0 && data_bit_no < dw)`
167			`do_temp[data_bit_no] = ~do_temp[data_bit_no];`
168	482	julius	`// Write word back`
169	483	julius	`mem[addr] = do_temp;`
170	482	julius	`end`
171			`endtask // gen_parity_err`
172			`endif
173
174
175	350	julius	`//`
176			`// Data output drivers`
177			`//`
178	482	julius	`assign doq_wire = mem[addr_reg];`
179			`assign doq = doq_wire[dw-1:0];`
180	350	julius
181			`//`
182			`// RAM read address register`
183			`//`
184			`always @(posedge clk)`
185			`if (ce)`
186			`addr_reg <= addr;`
187
188			`//`
189			`// RAM write`
190			`//`
191			`always @(posedge clk)`
192	483	julius	`ifdef OR1200_RAM_PARITY
193	350	julius	`if (we && ce)`
194	482	julius	`mem[addr] <= {di_p,di};`
195	483	julius	`else
196			`if (we && ce)`
197	350	julius	`mem[addr] <= di;`
198	482	julius	`endif
199	350	julius
200			`endmodule // or1200_spram`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram.v] - Blame information for rev 483