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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_1024x32.v] - Blame information for rev 854

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Line No. Rev Author Line
1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
4
////                                                              ////
5
////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  This block is a wrapper with common single-port             ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  single-port synchronous RAM.                                ////
14
////  It should be used in all OPENCORES designs that want to be  ////
15
////  portable accross different target technologies and          ////
16
////  independent of target memory.                               ////
17
////                                                              ////
18
////  Supported ASIC RAMs are:                                    ////
19
////  - Artisan Single-Port Sync RAM                              ////
20
////  - Avant! Two-Port Sync RAM (*)                              ////
21
////  - Virage Single-Port Sync RAM                               ////
22
////  - Virtual Silicon Single-Port Sync RAM                      ////
23
////                                                              ////
24
////  Supported FPGA RAMs are:                                    ////
25
////  - Xilinx Virtex RAMB16                                      ////
26
////  - Xilinx Virtex RAMB4                                       ////
27
////  - Altera LPM                                                ////
28
////                                                              ////
29
////  To Do:                                                      ////
30
////   - xilinx rams need external tri-state logic                ////
31
////   - fix avant! two-port ram                                  ////
32
////   - add additional RAMs                                      ////
33
////                                                              ////
34
////  Author(s):                                                  ////
35
////      - Damjan Lampret, lampret@opencores.org                 ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
////                                                              ////
39
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
40
////                                                              ////
41
//// This source file may be used and distributed without         ////
42
//// restriction provided that this copyright statement is not    ////
43
//// removed from the file and that any derivative work contains  ////
44
//// the original copyright notice and the associated disclaimer. ////
45
////                                                              ////
46
//// This source file is free software; you can redistribute it   ////
47
//// and/or modify it under the terms of the GNU Lesser General   ////
48
//// Public License as published by the Free Software Foundation; ////
49
//// either version 2.1 of the License, or (at your option) any   ////
50
//// later version.                                               ////
51
////                                                              ////
52
//// This source is distributed in the hope that it will be       ////
53
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
54
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
55
//// PURPOSE.  See the GNU Lesser General Public License for more ////
56
//// details.                                                     ////
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////                                                              ////
58
//// You should have received a copy of the GNU Lesser General    ////
59
//// Public License along with this source; if not, download it   ////
60
//// from http://www.opencores.org/lgpl.shtml                     ////
61
////                                                              ////
62
//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66
// $Log: or1200_spram_1024x32.v,v $
67
// Revision 2.0  2010/06/30 11:00:00  ORSoC
68
// Minor update: 
69
// Coding style changed.
70
//
71
// Revision 1.9  2005/10/19 11:37:56  jcastillo
72
// Added support for RAMB16 Xilinx4/Spartan3 primitives
73
//
74
// Revision 1.8  2004/06/08 18:15:32  lampret
75
// Changed behavior of the simulation generic models
76
//
77
// Revision 1.7  2004/04/05 08:29:57  lampret
78
// Merged branch_qmem into main tree.
79
//
80
// Revision 1.3.4.2  2003/12/09 11:46:48  simons
81
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
82
//
83
// Revision 1.3.4.1  2003/07/08 15:36:37  lampret
84
// Added embedded memory QMEM.
85
//
86
// Revision 1.3  2003/04/07 01:19:07  lampret
87
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
88
//
89
// Revision 1.2  2002/10/17 20:04:40  lampret
90
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
91
//
92
// Revision 1.1  2002/01/03 08:16:15  lampret
93
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
94
//
95
// Revision 1.8  2001/11/02 18:57:14  lampret
96
// Modified virtual silicon instantiations.
97
//
98
// Revision 1.7  2001/10/21 17:57:16  lampret
99
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
100
//
101
// Revision 1.6  2001/10/14 13:12:09  lampret
102
// MP3 version.
103
//
104
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
105
// no message
106
//
107
// Revision 1.1  2001/08/09 13:39:33  lampret
108
// Major clean-up.
109
//
110
// Revision 1.2  2001/07/30 05:38:02  lampret
111
// Adding empty directories required by HDL coding guidelines
112
//
113
//
114
 
115
// synopsys translate_off
116
`include "timescale.v"
117
// synopsys translate_on
118
`include "or1200_defines.v"
119
 
120
module or1200_spram_1024x32(
121
`ifdef OR1200_BIST
122
        // RAM BIST
123
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
124
`endif
125
        // Generic synchronous single-port RAM interface
126
        clk, rst, ce, we, oe, addr, di, doq
127
);
128
 
129
//
130
// Default address and data buses width
131
//
132
parameter aw = 10;
133
parameter dw = 32;
134
 
135
`ifdef OR1200_BIST
136
//
137
// RAM BIST
138
//
139
input mbist_si_i;
140
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
141
output mbist_so_o;
142
`endif
143
 
144
//
145
// Generic synchronous single-port RAM interface
146
//
147
input                   clk;    // Clock
148
input                   rst;    // Reset
149
input                   ce;     // Chip enable input
150
input                   we;     // Write enable input
151
input                   oe;     // Output enable input
152
input   [aw-1:0] addr;   // address bus inputs
153
input   [dw-1:0] di;     // input data bus
154
output  [dw-1:0] doq;    // output data bus
155
 
156
//
157
// Internal wires and registers
158
//
159
 
160
`ifdef OR1200_ARTISAN_SSP
161
`else
162
`ifdef OR1200_VIRTUALSILICON_SSP
163
`else
164
`ifdef OR1200_BIST
165
assign mbist_so_o = mbist_si_i;
166
`endif
167
`endif
168
`endif
169
 
170
`ifdef OR1200_ARTISAN_SSP
171
 
172
//
173
// Instantiation of ASIC memory:
174
//
175
// Artisan Synchronous Single-Port RAM (ra1sh)
176
//
177
`ifdef UNUSED
178
art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
179
`else
180
`ifdef OR1200_BIST
181
art_hssp_1024x32_bist artisan_ssp(
182
`else
183
art_hssp_1024x32 artisan_ssp(
184
`endif
185
`endif
186
`ifdef OR1200_BIST
187
        // RAM BIST
188
        .mbist_si_i(mbist_si_i),
189
        .mbist_so_o(mbist_so_o),
190
        .mbist_ctrl_i(mbist_ctrl_i),
191
`endif
192
        .CLK(clk),
193
        .CEN(~ce),
194
        .WEN(~we),
195
        .A(addr),
196
        .D(di),
197
        .OEN(~oe),
198
        .Q(doq)
199
);
200
 
201
`else
202
 
203
`ifdef OR1200_AVANT_ATP
204
 
205
//
206
// Instantiation of ASIC memory:
207
//
208
// Avant! Asynchronous Two-Port RAM
209
//
210
avant_atp avant_atp(
211
        .web(~we),
212
        .reb(),
213
        .oeb(~oe),
214
        .rcsb(),
215
        .wcsb(),
216
        .ra(addr),
217
        .wa(addr),
218
        .di(di),
219
        .doq(doq)
220
);
221
 
222
`else
223
 
224
`ifdef OR1200_VIRAGE_SSP
225
 
226
//
227
// Instantiation of ASIC memory:
228
//
229
// Virage Synchronous 1-port R/W RAM
230
//
231
virage_ssp virage_ssp(
232
        .clk(clk),
233
        .adr(addr),
234
        .d(di),
235
        .we(we),
236
        .oe(oe),
237
        .me(ce),
238
        .q(doq)
239
);
240
 
241
`else
242
 
243
`ifdef OR1200_VIRTUALSILICON_SSP
244
 
245
//
246
// Instantiation of ASIC memory:
247
//
248
// Virtual Silicon Single-Port Synchronous SRAM
249
//
250
`ifdef UNUSED
251
vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
252
`else
253
`ifdef OR1200_BIST
254
vs_hdsp_1024x32_bist vs_ssp(
255
`else
256
vs_hdsp_1024x32 vs_ssp(
257
`endif
258
`endif
259
`ifdef OR1200_BIST
260
        // RAM BIST
261
        .mbist_si_i(mbist_si_i),
262
        .mbist_so_o(mbist_so_o),
263
        .mbist_ctrl_i(mbist_ctrl_i),
264
`endif
265
        .CK(clk),
266
        .ADR(addr),
267
        .DI(di),
268
        .WEN(~we),
269
        .CEN(~ce),
270
        .OEN(~oe),
271
        .DOUT(doq)
272
);
273
 
274
`else
275
 
276
`ifdef OR1200_XILINX_RAMB4
277
 
278
//
279
// Instantiation of FPGA memory:
280
//
281
// Virtex/Spartan2
282
//
283
 
284
//
285
// Block 0
286
//
287
RAMB4_S4 ramb4_s4_0(
288
        .CLK(clk),
289
        .RST(1'b0),
290
        .ADDR(addr),
291
        .DI(di[3:0]),
292
        .EN(ce),
293
        .WE(we),
294
        .DO(doq[3:0])
295
);
296
 
297
//
298
// Block 1
299
//
300
RAMB4_S4 ramb4_s4_1(
301
        .CLK(clk),
302
        .RST(1'b0),
303
        .ADDR(addr),
304
        .DI(di[7:4]),
305
        .EN(ce),
306
        .WE(we),
307
        .DO(doq[7:4])
308
);
309
 
310
//
311
// Block 2
312
//
313
RAMB4_S4 ramb4_s4_2(
314
        .CLK(clk),
315
        .RST(1'b0),
316
        .ADDR(addr),
317
        .DI(di[11:8]),
318
        .EN(ce),
319
        .WE(we),
320
        .DO(doq[11:8])
321
);
322
 
323
//
324
// Block 3
325
//
326
RAMB4_S4 ramb4_s4_3(
327
        .CLK(clk),
328
        .RST(1'b0),
329
        .ADDR(addr),
330
        .DI(di[15:12]),
331
        .EN(ce),
332
        .WE(we),
333
        .DO(doq[15:12])
334
);
335
 
336
//
337
// Block 4
338
//
339
RAMB4_S4 ramb4_s4_4(
340
        .CLK(clk),
341
        .RST(1'b0),
342
        .ADDR(addr),
343
        .DI(di[19:16]),
344
        .EN(ce),
345
        .WE(we),
346
        .DO(doq[19:16])
347
);
348
 
349
//
350
// Block 5
351
//
352
RAMB4_S4 ramb4_s4_5(
353
        .CLK(clk),
354
        .RST(1'b0),
355
        .ADDR(addr),
356
        .DI(di[23:20]),
357
        .EN(ce),
358
        .WE(we),
359
        .DO(doq[23:20])
360
);
361
 
362
//
363
// Block 6
364
//
365
RAMB4_S4 ramb4_s4_6(
366
        .CLK(clk),
367
        .RST(1'b0),
368
        .ADDR(addr),
369
        .DI(di[27:24]),
370
        .EN(ce),
371
        .WE(we),
372
        .DO(doq[27:24])
373
);
374
 
375
//
376
// Block 7
377
//
378
RAMB4_S4 ramb4_s4_7(
379
        .CLK(clk),
380
        .RST(1'b0),
381
        .ADDR(addr),
382
        .DI(di[31:28]),
383
        .EN(ce),
384
        .WE(we),
385
        .DO(doq[31:28])
386
);
387
 
388
`else
389
 
390
`ifdef OR1200_XILINX_RAMB16
391
 
392
//
393
// Instantiation of FPGA memory:
394
//
395
// Virtex4/Spartan3E
396
//
397
// Added By Nir Mor
398
//
399
 
400
//
401
// Block 0
402
//
403
RAMB16_S9 ramb16_s9_0(
404
        .CLK(clk),
405
        .SSR(1'b0),
406
        .ADDR({1'b0,addr}),
407
        .DI(di[7:0]),
408
        .DIP(1'b0),
409
        .EN(ce),
410
        .WE(we),
411
        .DO(doq[7:0]),
412
        .DOP()
413
);
414
 
415
//
416
// Block 1
417
//
418
RAMB16_S9 ramb16_s9_1(
419
        .CLK(clk),
420
        .SSR(1'b0),
421
        .ADDR({1'b0,addr}),
422
        .DI(di[15:8]),
423
        .DIP(1'b0),
424
        .EN(ce),
425
        .WE(we),
426
        .DO(doq[15:8]),
427
        .DOP()
428
);
429
 
430
//
431
// Block 2
432
//
433
RAMB16_S9 ramb16_s9_2(
434
        .CLK(clk),
435
        .SSR(1'b0),
436
        .ADDR({1'b0,addr}),
437
        .DI(di[23:16]),
438
        .DIP(1'b0),
439
        .EN(ce),
440
        .WE(we),
441
        .DO(doq[23:16]),
442
        .DOP()
443
);
444
 
445
//
446
// Block 3
447
//
448
RAMB16_S9 ramb16_s9_3(
449
        .CLK(clk),
450
        .SSR(1'b0),
451
        .ADDR({1'b0,addr}),
452
        .DI(di[31:24]),
453
        .DIP(1'b0),
454
        .EN(ce),
455
        .WE(we),
456
        .DO(doq[31:24]),
457
        .DOP()
458
);
459
 
460
`else
461
 
462
`ifdef OR1200_ALTERA_LPM
463
 
464
//
465
// Instantiation of FPGA memory:
466
//
467
// Altera LPM
468
//
469
// Added By Jamil Khatib
470
//
471
 
472
wire    wr;
473
 
474
assign  wr = ce & we;
475
 
476
initial $display("Using Altera LPM.");
477
 
478
lpm_ram_dq lpm_ram_dq_component (
479
        .address(addr),
480
        .inclock(clk),
481
        .outclock(clk),
482
        .data(di),
483
        .we(wr),
484
        .q(doq)
485
);
486
 
487
defparam lpm_ram_dq_component.lpm_width = dw,
488
        lpm_ram_dq_component.lpm_widthad = aw,
489
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
490
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
491
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
492
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
493
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
494
 
495
`else
496
 
497
//
498
// Generic single-port synchronous RAM model
499
//
500
 
501
//
502
// Generic RAM's registers and wires
503
//
504
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
505
reg     [aw-1:0] addr_reg;               // RAM address register
506
 
507
//
508
// Data output drivers
509
//
510
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
511
 
512
//
513
// RAM address register
514
//
515 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
516
        if (rst == `OR1200_RST_VALUE)
517 350 julius
                addr_reg <=  {aw{1'b0}};
518
        else if (ce)
519
                addr_reg <=  addr;
520
 
521
//
522
// RAM write
523
//
524
always @(posedge clk)
525
        if (ce && we)
526
                mem[addr] <=  di;
527
 
528
`endif  // !OR1200_ALTERA_LPM
529
`endif  // !OR1200_XILINX_RAMB16
530
`endif  // !OR1200_XILINX_RAMB4
531
`endif  // !OR1200_VIRTUALSILICON_SSP
532
`endif  // !OR1200_VIRAGE_SSP
533
`endif  // !OR1200_AVANT_ATP
534
`endif  // !OR1200_ARTISAN_SSP
535
 
536
endmodule

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