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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_2048x32_bw.v] - Blame information for rev 751

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Generic Single-Port Synchronous RAM with byte write signals ////
4
////                                                              ////
5
////  This file is part of memory library available from          ////
6
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  This block is a wrapper with common single-port             ////
10
////  synchronous memory interface for different                  ////
11
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12
////  interface it also provides behavioral model of generic      ////
13
////  single-port synchronous RAM.                                ////
14
////  It should be used in all OPENCORES designs that want to be  ////
15
////  portable accross different target technologies and          ////
16
////  independent of target memory.                               ////
17
////                                                              ////
18
////  Supported ASIC RAMs are:                                    ////
19
////  - Artisan Single-Port Sync RAM                              ////
20
////  - Avant! Two-Port Sync RAM (*)                              ////
21
////  - Virage Single-Port Sync RAM                               ////
22
////  - Virtual Silicon Single-Port Sync RAM                      ////
23
////                                                              ////
24
////  Supported FPGA RAMs are:                                    ////
25
////  - Xilinx Virtex RAMB16                                      ////
26
////  - Xilinx Virtex RAMB4                                       ////
27
////                                                              ////
28
////  To Do:                                                      ////
29
////   - xilinx rams need external tri-state logic                ////
30
////   - fix avant! two-port ram                                  ////
31
////   - add additional RAMs                                      ////
32
////                                                              ////
33
////  Author(s):                                                  ////
34
////      - Damjan Lampret, lampret@opencores.org                 ////
35
////                                                              ////
36
//////////////////////////////////////////////////////////////////////
37
////                                                              ////
38
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
39
////                                                              ////
40
//// This source file may be used and distributed without         ////
41
//// restriction provided that this copyright statement is not    ////
42
//// removed from the file and that any derivative work contains  ////
43
//// the original copyright notice and the associated disclaimer. ////
44
////                                                              ////
45
//// This source file is free software; you can redistribute it   ////
46
//// and/or modify it under the terms of the GNU Lesser General   ////
47
//// Public License as published by the Free Software Foundation; ////
48
//// either version 2.1 of the License, or (at your option) any   ////
49
//// later version.                                               ////
50
////                                                              ////
51
//// This source is distributed in the hope that it will be       ////
52
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55
//// details.                                                     ////
56
////                                                              ////
57
//// You should have received a copy of the GNU Lesser General    ////
58
//// Public License along with this source; if not, download it   ////
59
//// from http://www.opencores.org/lgpl.shtml                     ////
60
////                                                              ////
61
//////////////////////////////////////////////////////////////////////
62
//
63
// CVS Revision History
64
//
65
// $Log: or1200_spram_2048x32_bw.v,v $
66
// Revision 2.0  2010/06/30 11:00:00  ORSoC
67
// Minor update: 
68
// Coding style changed.
69
//
70
// Revision 1.5  2005/10/19 11:37:56  jcastillo
71
// Added support for RAMB16 Xilinx4/Spartan3 primitives
72
//
73
// Revision 1.4  2004/06/08 18:15:32  lampret
74
// Changed behavior of the simulation generic models
75
//
76
// Revision 1.3  2003/10/17 07:59:44  markom
77
// mbist signals updated according to newest convention
78
//
79
// Revision 1.2  2003/09/12 09:03:54  dries
80
// correct all the syntax errors
81
//
82
// Revision 1.1  2003/08/26 09:37:02  simons
83
// Added support for rams with byte write access.
84
//
85
//
86
 
87
// synopsys translate_off
88
`include "timescale.v"
89
// synopsys translate_on
90
`include "or1200_defines.v"
91
 
92
module or1200_spram_2048x32_bw(
93
`ifdef OR1200_BIST
94
        // RAM BIST
95
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
96
`endif
97
        // Generic synchronous single-port RAM interface
98
        clk, rst, ce, we, oe, addr, di, doq
99
);
100
 
101
`ifdef OR1200_BIST
102
//
103
// RAM BIST
104
//
105
input                   mbist_si_i;
106
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
107
output                  mbist_so_o;
108
`endif
109
 
110
//
111
// Generic synchronous single-port RAM interface
112
//
113
input                   clk;    // Clock
114
input                   rst;    // Reset
115
input                   ce;     // Chip enable input
116
input   [3:0]           we;     // Write enable input
117
input                   oe;     // Output enable input
118
input   [10:0]          addr;   // address bus inputs
119
input   [31:0]          di;     // input data bus
120
output  [31:0]          doq;     // output data bus
121
 
122
//
123
// Internal wires and registers
124
//
125
 
126
`ifdef OR1200_ARTISAN_SSP
127
`else
128
`ifdef OR1200_VIRTUALSILICON_SSP
129
`else
130
`ifdef OR1200_BIST
131
assign mbist_so_o = mbist_si_i;
132
`endif
133
`endif
134
`endif
135
 
136
 
137
`ifdef OR1200_ARTISAN_SSP
138
 
139
//
140
// Instantiation of ASIC memory:
141
//
142
// Artisan Synchronous Single-Port RAM (ra1sh)
143
//
144
`ifdef UNUSED
145
art_hssp_2048x32_bw artisan_ssp(
146
`else
147
`ifdef OR1200_BIST
148
art_hssp_2048x32_bw_bist artisan_ssp(
149
`else
150
art_hssp_2048x32_bw artisan_ssp(
151
`endif
152
`endif
153
`ifdef OR1200_BIST
154
        // RAM BIST
155
        .mbist_si_i(mbist_si_i),
156
        .mbist_so_o(mbist_so_o),
157
        .mbist_ctrl_i(mbist_ctrl_i),
158
`endif
159
        .CLK(clk),
160
        .CEN(~ce),
161
        .WEN(~we),
162
        .A(addr),
163
        .D(di),
164
        .OEN(~oe),
165
        .Q(doq)
166
);
167
 
168
`else
169
 
170
`ifdef OR1200_AVANT_ATP
171
 
172
//
173
// Instantiation of ASIC memory:
174
//
175
// Avant! Asynchronous Two-Port RAM
176
//
177
avant_atp avant_atp(
178
        .web(~we),
179
        .reb(),
180
        .oeb(~oe),
181
        .rcsb(),
182
        .wcsb(),
183
        .ra(addr),
184
        .wa(addr),
185
        .di(di),
186
        .doq(doq)
187
);
188
 
189
`else
190
 
191
`ifdef OR1200_VIRAGE_SSP
192
 
193
//
194
// Instantiation of ASIC memory:
195
//
196
// Virage Synchronous 1-port R/W RAM
197
//
198
virage_ssp virage_ssp(
199
        .clk(clk),
200
        .adr(addr),
201
        .d(di),
202
        .we(we),
203
        .oe(oe),
204
        .me(ce),
205
        .q(doq)
206
);
207
 
208
`else
209
 
210
`ifdef OR1200_VIRTUALSILICON_SSP
211
 
212
//
213
// Instantiation of ASIC memory:
214
//
215
// Virtual Silicon Single-Port Synchronous SRAM
216
//
217
`ifdef OR1200_BIST
218
wire mbist_si_i_ram_0;
219
wire mbist_si_i_ram_1;
220
wire mbist_si_i_ram_2;
221
wire mbist_si_i_ram_3;
222
wire mbist_so_o_ram_0;
223
wire mbist_so_o_ram_1;
224
wire mbist_so_o_ram_2;
225
wire mbist_so_o_ram_3;
226
assign mbist_si_i_ram_0 = mbist_si_i;
227
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
228
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
229
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
230
assign mbist_so_o = mbist_so_o_ram_3;
231
`endif
232
 
233
`ifdef UNUSED
234
vs_hdsp_2048x8 vs_ssp_0(
235
`else
236
`ifdef OR1200_BIST
237
vs_hdsp_2048x8_bist vs_ssp_0(
238
`else
239
vs_hdsp_2048x8 vs_ssp_0(
240
`endif
241
`endif
242
`ifdef OR1200_BIST
243
        // RAM BIST
244
        .mbist_si_i(mbist_si_i_ram_0),
245
        .mbist_so_o(mbist_so_o_ram_0),
246
        .mbist_ctrl_i(mbist_ctrl_i),
247
`endif
248
        .CK(clk),
249
        .ADR(addr),
250
        .DI(di[7:0]),
251
        .WEN(~we[0]),
252
        .CEN(~ce),
253
        .OEN(~oe),
254
        .DOUT(doq[7:0])
255
);
256
 
257
`ifdef UNUSED
258
vs_hdsp_2048x8 vs_ssp_1(
259
`else
260
`ifdef OR1200_BIST
261
vs_hdsp_2048x8_bist vs_ssp_1(
262
`else
263
vs_hdsp_2048x8 vs_ssp_1(
264
`endif
265
`endif
266
`ifdef OR1200_BIST
267
        // RAM BIST
268
        .mbist_si_i(mbist_si_i_ram_1),
269
        .mbist_so_o(mbist_so_o_ram_1),
270
        .mbist_ctrl_i(mbist_ctrl_i),
271
`endif
272
        .CK(clk),
273
        .ADR(addr),
274
        .DI(di[15:8]),
275
        .WEN(~we[1]),
276
        .CEN(~ce),
277
        .OEN(~oe),
278
        .DOUT(doq[15:8])
279
);
280
 
281
`ifdef UNUSED
282
vs_hdsp_2048x8 vs_ssp_2(
283
`else
284
`ifdef OR1200_BIST
285
vs_hdsp_2048x8_bist vs_ssp_2(
286
`else
287
vs_hdsp_2048x8 vs_ssp_2(
288
`endif
289
`endif
290
`ifdef OR1200_BIST
291
        // RAM BIST
292
        .mbist_si_i(mbist_si_i_ram_2),
293
        .mbist_so_o(mbist_so_o_ram_2),
294
        .mbist_ctrl_i(mbist_ctrl_i),
295
`endif
296
        .CK(clk),
297
        .ADR(addr),
298
        .DI(di[23:16]),
299
        .WEN(~we[2]),
300
        .CEN(~ce),
301
        .OEN(~oe),
302
        .DOUT(doq[23:16])
303
);
304
 
305
`ifdef UNUSED
306
vs_hdsp_2048x8 vs_ssp_3(
307
`else
308
`ifdef OR1200_BIST
309
vs_hdsp_2048x8_bist vs_ssp_3(
310
`else
311
vs_hdsp_2048x8 vs_ssp_3(
312
`endif
313
`endif
314
`ifdef OR1200_BIST
315
        // RAM BIST
316
        .mbist_si_i(mbist_si_i_ram_3),
317
        .mbist_so_o(mbist_so_o_ram_3),
318
        .mbist_ctrl_i(mbist_ctrl_i),
319
`endif
320
        .CK(clk),
321
        .ADR(addr),
322
        .DI(di[31:24]),
323
        .WEN(~we[3]),
324
        .CEN(~ce),
325
        .OEN(~oe),
326
        .DOUT(doq[31:24])
327
);
328
 
329
`else
330
 
331
`ifdef OR1200_XILINX_RAMB4
332
 
333
//
334
// Instantiation of FPGA memory:
335
//
336
// Virtex/Spartan2
337
//
338
 
339
//
340
// Block 0
341
//
342
RAMB4_S2 ramb4_s2_0(
343
        .CLK(clk),
344
        .RST(1'b0),
345
        .ADDR(addr),
346
        .DI(di[1:0]),
347
        .EN(ce),
348
        .WE(we[0]),
349
        .DO(doq[1:0])
350
);
351
 
352
//
353
// Block 1
354
//
355
RAMB4_S2 ramb4_s2_1(
356
        .CLK(clk),
357
        .RST(1'b0),
358
        .ADDR(addr),
359
        .DI(di[3:2]),
360
        .EN(ce),
361
        .WE(we[0]),
362
        .DO(doq[3:2])
363
);
364
 
365
//
366
// Block 2
367
//
368
RAMB4_S2 ramb4_s2_2(
369
        .CLK(clk),
370
        .RST(1'b0),
371
        .ADDR(addr),
372
        .DI(di[5:4]),
373
        .EN(ce),
374
        .WE(we[0]),
375
        .DO(doq[5:4])
376
);
377
 
378
//
379
// Block 3
380
//
381
RAMB4_S2 ramb4_s2_3(
382
        .CLK(clk),
383
        .RST(1'b0),
384
        .ADDR(addr),
385
        .DI(di[7:6]),
386
        .EN(ce),
387
        .WE(we[0]),
388
        .DO(doq[7:6])
389
);
390
//
391
// Block 4
392
//
393
RAMB4_S2 ramb4_s2_4(
394
        .CLK(clk),
395
        .RST(1'b0),
396
        .ADDR(addr),
397
        .DI(di[9:8]),
398
        .EN(ce),
399
        .WE(we[1]),
400
        .DO(doq[9:8])
401
);
402
 
403
//
404
// Block 5
405
//
406
RAMB4_S2 ramb4_s2_5(
407
        .CLK(clk),
408
        .RST(1'b0),
409
        .ADDR(addr),
410
        .DI(di[11:10]),
411
        .EN(ce),
412
        .WE(we[1]),
413
        .DO(doq[11:10])
414
);
415
 
416
//
417
// Block 6
418
//
419
RAMB4_S2 ramb4_s2_6(
420
        .CLK(clk),
421
        .RST(1'b0),
422
        .ADDR(addr),
423
        .DI(di[13:12]),
424
        .EN(ce),
425
        .WE(we[1]),
426
        .DO(doq[13:12])
427
);
428
 
429
//
430
// Block 7
431
//
432
RAMB4_S2 ramb4_s2_7(
433
        .CLK(clk),
434
        .RST(1'b0),
435
        .ADDR(addr),
436
        .DI(di[15:14]),
437
        .EN(ce),
438
        .WE(we[1]),
439
        .DO(doq[15:14])
440
);
441
//
442
// Block 8
443
//
444
RAMB4_S2 ramb4_s2_8(
445
        .CLK(clk),
446
        .RST(1'b0),
447
        .ADDR(addr),
448
        .DI(di[17:16]),
449
        .EN(ce),
450
        .WE(we[2]),
451
        .DO(doq[17:16])
452
);
453
 
454
//
455
// Block 9
456
//
457
RAMB4_S2 ramb4_s2_9(
458
        .CLK(clk),
459
        .RST(1'b0),
460
        .ADDR(addr),
461
        .DI(di[19:18]),
462
        .EN(ce),
463
        .WE(we[2]),
464
        .DO(doq[19:18])
465
);
466
 
467
//
468
// Block 10
469
//
470
RAMB4_S2 ramb4_s2_10(
471
        .CLK(clk),
472
        .RST(1'b0),
473
        .ADDR(addr),
474
        .DI(di[21:20]),
475
        .EN(ce),
476
        .WE(we[2]),
477
        .DO(doq[21:20])
478
);
479
 
480
//
481
// Block 11
482
//
483
RAMB4_S2 ramb4_s2_11(
484
        .CLK(clk),
485
        .RST(1'b0),
486
        .ADDR(addr),
487
        .DI(di[23:22]),
488
        .EN(ce),
489
        .WE(we[2]),
490
        .DO(doq[23:22])
491
);
492
//
493
// Block 12
494
//
495
RAMB4_S2 ramb4_s2_12(
496
        .CLK(clk),
497
        .RST(1'b0),
498
        .ADDR(addr),
499
        .DI(di[25:24]),
500
        .EN(ce),
501
        .WE(we[3]),
502
        .DO(doq[25:24])
503
);
504
 
505
//
506
// Block 13
507
//
508
RAMB4_S2 ramb4_s2_13(
509
        .CLK(clk),
510
        .RST(1'b0),
511
        .ADDR(addr),
512
        .DI(di[27:26]),
513
        .EN(ce),
514
        .WE(we[3]),
515
        .DO(doq[27:26])
516
);
517
 
518
//
519
// Block 14
520
//
521
RAMB4_S2 ramb4_s2_14(
522
        .CLK(clk),
523
        .RST(1'b0),
524
        .ADDR(addr),
525
        .DI(di[29:28]),
526
        .EN(ce),
527
        .WE(we[3]),
528
        .DO(doq[29:28])
529
);
530
 
531
//
532
// Block 15
533
//
534
RAMB4_S2 ramb4_s2_15(
535
        .CLK(clk),
536
        .RST(1'b0),
537
        .ADDR(addr),
538
        .DI(di[31:30]),
539
        .EN(ce),
540
        .WE(we[3]),
541
        .DO(doq[31:30])
542
);
543
 
544
`else
545
 
546
`ifdef OR1200_XILINX_RAMB16
547
 
548
//
549
// Instantiation of FPGA memory:
550
//
551
// Virtex4/Spartan3E
552
//
553
// Added By Nir Mor
554
//
555
 
556
//
557
// Block 0
558
//
559
RAMB16_S9 ramb16_s9_0(
560
        .CLK(clk),
561
        .SSR(1'b0),
562
        .ADDR(addr),
563
        .DI(di[7:0]),
564
        .DIP(1'b0),
565
        .EN(ce),
566
        .WE(we[0]),
567
        .DO(doq[7:0]),
568
        .DOP()
569
);
570
 
571
//
572
// Block 1
573
//
574
RAMB16_S9 ramb16_s9_1(
575
        .CLK(clk),
576
        .SSR(1'b0),
577
        .ADDR(addr),
578
        .DI(di[15:8]),
579
        .DIP(1'b0),
580
        .EN(ce),
581
        .WE(we[1]),
582
        .DO(doq[15:8]),
583
        .DOP()
584
);
585
 
586
//
587
// Block 2
588
//
589
RAMB16_S9 ramb16_s9_2(
590
        .CLK(clk),
591
        .SSR(1'b0),
592
        .ADDR(addr),
593
        .DI(di[23:16]),
594
        .DIP(1'b0),
595
        .EN(ce),
596
        .WE(we[2]),
597
        .DO(doq[23:16]),
598
        .DOP()
599
);
600
 
601
//
602
// Block 3
603
//
604
RAMB16_S9 ramb16_s9_3(
605
        .CLK(clk),
606
        .SSR(1'b0),
607
        .ADDR(addr),
608
        .DI(di[31:24]),
609
        .DIP(1'b0),
610
        .EN(ce),
611
        .WE(we[3]),
612
        .DO(doq[31:24]),
613
        .DOP()
614
);
615
 
616
`else
617
 
618
//
619
// Generic single-port synchronous RAM model
620
//
621
 
622
//
623
// Generic RAM's registers and wires
624
//
625
reg     [7:0]        mem_0 [2047:0];              // RAM content
626
reg     [7:0]        mem_1 [2047:0];              // RAM content
627
reg     [7:0]        mem_2 [2047:0];              // RAM content
628
reg     [7:0]        mem_3 [2047:0];              // RAM content
629
reg     [10:0]       addr_reg;                    // RAM address register
630
 
631
//
632
// Data output drivers
633
//
634
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
635
 
636
//
637
// RAM address register
638
//
639 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
640
        if (rst == `OR1200_RST_VALUE)
641 350 julius
                addr_reg <=  11'h000;
642
        else if (ce)
643
                addr_reg <=  addr;
644
 
645
//
646
// RAM write byte 0
647
//
648
always @(posedge clk)
649
        if (ce && we[0])
650
                mem_0[addr] <=  di[7:0];
651
 
652
//
653
// RAM write byte 1
654
//
655
always @(posedge clk)
656
        if (ce && we[1])
657
                mem_1[addr] <=  di[15:8];
658
 
659
//
660
// RAM write byte 2
661
//
662
always @(posedge clk)
663
        if (ce && we[2])
664
                mem_2[addr] <=  di[23:16];
665
 
666
//
667
// RAM write byte 3
668
//
669
always @(posedge clk)
670
        if (ce && we[3])
671
                mem_3[addr] <=  di[31:24];
672
 
673
`endif  // !OR1200_XILINX_RAMB16
674
`endif  // !OR1200_XILINX_RAMB4
675
`endif  // !OR1200_VIRTUALSILICON_SSP
676
`endif  // !OR1200_VIRAGE_SSP
677
`endif  // !OR1200_AVANT_ATP
678
`endif  // !OR1200_ARTISAN_SSP
679
 
680
endmodule

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