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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_32_bw.v] - Blame information for rev 822

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM 32-bit Byte-Write       ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Tadej Markovic, tadej.markovic@gmail.com              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// New 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_32_bw
  (
`ifdef OR1200_BIST
   // RAM BIST
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
   // Generic synchronous single-port RAM interface
   clk, ce, we, addr, di, doq
   );
 
   //
   // Default address and data buses width
   //
   parameter aw = 10;
   parameter dw = 32;
 
`ifdef OR1200_BIST
   //
   // RAM BIST
   //
   input mbist_si_i;
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
   output                                 mbist_so_o;
`endif
 
   //
   // Generic synchronous single-port RAM interface
   //
   input                                  clk;  // Clock
   input                                  ce;   // Chip enable input
   input [3:0]                             we;   // Write enable input
   input [aw-1:0]                          addr; // address bus inputs
   input [dw-1:0]                          di;   // input data bus
   output [dw-1:0]                         doq;  // output data bus
 
   //
   // Internal wires and registers
   //
 
   //
   // Generic single-port synchronous RAM model
   //
 
   //
   // Generic RAM's registers and wires
   //
`ifdef OR1200_GENERIC
   reg [7:0]                               mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
   reg [7:0]                               mem0 [(1<<aw)-1:0];
   reg [7:0]                               mem1 [(1<<aw)-1:0];
   reg [7:0]                               mem2 [(1<<aw)-1:0];
   reg [7:0]                               mem3 [(1<<aw)-1:0];
`endif
   reg [aw-1:0]                    addr_reg;             // RAM address register
 
   //
   // Data output drivers
   //
   assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
 
   //
   // RAM read address register
   //
   always @(posedge clk)
     if (ce)
       addr_reg <=  addr;
 
   //
   // RAM write - big endian selection
   //
   always @(posedge clk)
     if (ce) begin
       if (we[3])
         mem0[addr] <=  di[31:24];
       if (we[2])
         mem1[addr] <=  di[23:16];
       if (we[1])
         mem2[addr] <=  di[15:08];
       if (we[0])
         mem3[addr] <=  di[07:00];
     end
 
endmodule // or1200_spram

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM 32-bit Byte-Write ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Michael Unneback, unneback@opencores.org ////`
20			`//// - Tadej Markovic, tadej.markovic@gmail.com ////`
21			`//// ////`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from http://www.opencores.org/lgpl.shtml ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48			`//`
49			`// CVS Revision History`
50			`//`
51			`// $Log: or1200_dpram_32x32.v,v $`
52			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
53			`// New`
54			`//`
55
56			`// synopsys translate_off`
57			`include "timescale.v"
58			`// synopsys translate_on`
59			`include "or1200_defines.v"
60
61			`module or1200_spram_32_bw`
62			`(`
63			`ifdef OR1200_BIST
64			`// RAM BIST`
65			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
66			`endif
67			`// Generic synchronous single-port RAM interface`
68			`clk, ce, we, addr, di, doq`
69			`);`
70
71			`//`
72			`// Default address and data buses width`
73			`//`
74			`parameter aw = 10;`
75			`parameter dw = 32;`
76
77			`ifdef OR1200_BIST
78			`//`
79			`// RAM BIST`
80			`//`
81			`input mbist_si_i;`
82			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
83			`output mbist_so_o;`
84			`endif
85
86			`//`
87			`// Generic synchronous single-port RAM interface`
88			`//`
89			`input clk; // Clock`
90			`input ce; // Chip enable input`
91			`input [3:0] we; // Write enable input`
92			`input [aw-1:0] addr; // address bus inputs`
93			`input [dw-1:0] di; // input data bus`
94			`output [dw-1:0] doq; // output data bus`
95
96			`//`
97			`// Internal wires and registers`
98			`//`
99
100			`//`
101			`// Generic single-port synchronous RAM model`
102			`//`
103
104			`//`
105			`// Generic RAM's registers and wires`
106			`//`
107			`ifdef OR1200_GENERIC
108			`reg [7:0] mem0 [(1<<aw)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
109			`reg [7:0] mem1 [(1<<aw)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
110			`reg [7:0] mem2 [(1<<aw)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
111			`reg [7:0] mem3 [(1<<aw)-1:0] /synthesis syn_ramstyle = "no_rw_check"/;`
112			`else
113			`reg [7:0] mem0 [(1<<aw)-1:0];`
114			`reg [7:0] mem1 [(1<<aw)-1:0];`
115			`reg [7:0] mem2 [(1<<aw)-1:0];`
116			`reg [7:0] mem3 [(1<<aw)-1:0];`
117			`endif
118			`reg [aw-1:0] addr_reg; // RAM address register`
119
120			`//`
121			`// Data output drivers`
122			`//`
123			`assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};`
124
125			`//`
126			`// RAM read address register`
127			`//`
128			`always @(posedge clk)`
129			`if (ce)`
130			`addr_reg <= addr;`
131
132			`//`
133			`// RAM write - big endian selection`
134			`//`
135			`always @(posedge clk)`
136			`if (ce) begin`
137			`if (we[3])`
138			`mem0[addr] <= di[31:24];`
139			`if (we[2])`
140			`mem1[addr] <= di[23:16];`
141			`if (we[1])`
142			`mem2[addr] <= di[15:08];`
143			`if (we[0])`
144			`mem3[addr] <= di[07:00];`
145			`end`
146
147			`endmodule // or1200_spram`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_32_bw.v] - Blame information for rev 822