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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_512x20.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
// Revision 1.9  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_512x20(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire    [3:0]            unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire    [11:0]           unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
        .CLK(clk),
        .RST(1'b0),
        .ADDR(addr),
        .DI(di[7:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[7:0])
);
 
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
        .CLK(clk),
        .RST(1'b0),
        .ADDR(addr),
        .DI(di[15:8]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:8])
);
 
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
        .CLK(clk),
        .RST(1'b0),
        .ADDR(addr),
        .DI({4'b0000, di[19:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[19:16]})
);
 
`else
 
`ifdef OR1200_XILINX_RAMB16
 
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
 
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .SSR(1'b0),
        .ADDR(addr),
        .DI({12'h000,di}),
        .DIP(4'h0),
        .EN(ce),
        .WE(we),
        .DO({unconnected,doq}),
        .DOP()
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                addr_reg <=  {aw{1'b0}};
        else if (ce)
                addr_reg <=  addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <=  di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_512x20.v] - Blame information for rev 751

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB16 ////`
26			`//// - Xilinx Virtex RAMB4 ////`
27			`//// - Altera LPM ////`
28			`//// ////`
29			`//// To Do: ////`
30			`//// - xilinx rams need external tri-state logic ////`
31			`//// - fix avant! two-port ram ////`
32			`//// - add additional RAMs ////`
33			`//// ////`
34			`//// Author(s): ////`
35			`//// - Damjan Lampret, lampret@opencores.org ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//// ////`
39			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
40			`//// ////`
41			`//// This source file may be used and distributed without ////`
42			`//// restriction provided that this copyright statement is not ////`
43			`//// removed from the file and that any derivative work contains ////`
44			`//// the original copyright notice and the associated disclaimer. ////`
45			`//// ////`
46			`//// This source file is free software; you can redistribute it ////`
47			`//// and/or modify it under the terms of the GNU Lesser General ////`
48			`//// Public License as published by the Free Software Foundation; ////`
49			`//// either version 2.1 of the License, or (at your option) any ////`
50			`//// later version. ////`
51			`//// ////`
52			`//// This source is distributed in the hope that it will be ////`
53			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
54			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
55			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
56			`//// details. ////`
57			`//// ////`
58			`//// You should have received a copy of the GNU Lesser General ////`
59			`//// Public License along with this source; if not, download it ////`
60			`//// from http://www.opencores.org/lgpl.shtml ////`
61			`//// ////`
62			`//////////////////////////////////////////////////////////////////////`
63			`//`
64			`// CVS Revision History`
65			`//`
66			`// $Log: or1200_spram_512x20.v,v $`
67			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
68			`// Minor update:`
69			`// Coding style changed.`
70			`//`
71			`// Revision 1.9 2005/10/19 11:37:56 jcastillo`
72			`// Added support for RAMB16 Xilinx4/Spartan3 primitives`
73			`//`
74			`// Revision 1.8 2004/06/08 18:15:32 lampret`
75			`// Changed behavior of the simulation generic models`
76			`//`
77			`// Revision 1.7 2004/04/05 08:29:57 lampret`
78			`// Merged branch_qmem into main tree.`
79			`//`
80			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
81			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
82			`//`
83			`// Revision 1.3 2003/04/07 01:19:07 lampret`
84			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
85			`//`
86			`// Revision 1.2 2002/10/17 20:04:40 lampret`
87			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
88			`//`
89			`// Revision 1.1 2002/01/03 08:16:15 lampret`
90			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
91			`//`
92			`// Revision 1.10 2001/11/27 21:24:04 lampret`
93			`// Changed instantiation name of VS RAMs.`
94			`//`
95			`// Revision 1.9 2001/11/27 19:45:04 lampret`
96			`// Fixed VS RAM instantiation - again.`
97			`//`
98			`// Revision 1.8 2001/11/23 21:42:31 simons`
99			`// Program counter divided to PPC and NPC.`
100			`//`
101			`// Revision 1.6 2001/10/21 17:57:16 lampret`
102			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
103			`//`
104			`// Revision 1.5 2001/10/14 13:12:09 lampret`
105			`// MP3 version.`
106			`//`
107			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
108			`// no message`
109			`//`
110			`// Revision 1.1 2001/08/09 13:39:33 lampret`
111			`// Major clean-up.`
112			`//`
113			`// Revision 1.2 2001/07/30 05:38:02 lampret`
114			`// Adding empty directories required by HDL coding guidelines`
115			`//`
116			`//`
117
118			`// synopsys translate_off`
119			`include "timescale.v"
120			`// synopsys translate_on`
121			`include "or1200_defines.v"
122
123			`module or1200_spram_512x20(`
124			`ifdef OR1200_BIST
125			`// RAM BIST`
126			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
127			`endif
128			`// Generic synchronous single-port RAM interface`
129			`clk, rst, ce, we, oe, addr, di, doq`
130			`);`
131
132			`//`
133			`// Default address and data buses width`
134			`//`
135			`parameter aw = 9;`
136			`parameter dw = 20;`
137
138			`ifdef OR1200_BIST
139			`//`
140			`// RAM BIST`
141			`//`
142			`input mbist_si_i;`
143			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
144			`output mbist_so_o;`
145			`endif
146
147			`//`
148			`// Generic synchronous single-port RAM interface`
149			`//`
150			`input clk; // Clock`
151			`input rst; // Reset`
152			`input ce; // Chip enable input`
153			`input we; // Write enable input`
154			`input oe; // Output enable input`
155			`input [aw-1:0] addr; // address bus inputs`
156			`input [dw-1:0] di; // input data bus`
157			`output [dw-1:0] doq; // output data bus`
158
159			`//`
160			`// Internal wires and registers`
161			`//`
162			`ifdef OR1200_XILINX_RAMB4
163			`wire [3:0] unconnected;`
164			`else
165			`ifdef OR1200_XILINX_RAMB16
166			`wire [11:0] unconnected;`
167			`endif // !OR1200_XILINX_RAMB16
168			`endif // !OR1200_XILINX_RAMB4
169
170			`ifdef OR1200_ARTISAN_SSP
171			`else
172			`ifdef OR1200_VIRTUALSILICON_SSP
173			`else
174			`ifdef OR1200_BIST
175			`assign mbist_so_o = mbist_si_i;`
176			`endif
177			`endif
178			`endif
179
180			`ifdef OR1200_ARTISAN_SSP
181
182			`//`
183			`// Instantiation of ASIC memory:`
184			`//`
185			`// Artisan Synchronous Single-Port RAM (ra1sh)`
186			`//`
187			`ifdef UNUSED
188			`art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(`
189			`else
190			`ifdef OR1200_BIST
191			`art_hssp_512x20_bist artisan_ssp(`
192			`else
193			`art_hssp_512x20 artisan_ssp(`
194			`endif
195			`endif
196			`ifdef OR1200_BIST
197			`// RAM BIST`
198			`.mbist_si_i(mbist_si_i),`
199			`.mbist_so_o(mbist_so_o),`
200			`.mbist_ctrl_i(mbist_ctrl_i),`
201			`endif
202			`.CLK(clk),`
203			`.CEN(~ce),`
204			`.WEN(~we),`
205			`.A(addr),`
206			`.D(di),`
207			`.OEN(~oe),`
208			`.Q(doq)`
209			`);`
210
211			`else
212
213			`ifdef OR1200_AVANT_ATP
214
215			`//`
216			`// Instantiation of ASIC memory:`
217			`//`
218			`// Avant! Asynchronous Two-Port RAM`
219			`//`
220			`avant_atp avant_atp(`
221			`.web(~we),`
222			`.reb(),`
223			`.oeb(~oe),`
224			`.rcsb(),`
225			`.wcsb(),`
226			`.ra(addr),`
227			`.wa(addr),`
228			`.di(di),`
229			`.doq(doq)`
230			`);`
231
232			`else
233
234			`ifdef OR1200_VIRAGE_SSP
235
236			`//`
237			`// Instantiation of ASIC memory:`
238			`//`
239			`// Virage Synchronous 1-port R/W RAM`
240			`//`
241			`virage_ssp virage_ssp(`
242			`.clk(clk),`
243			`.adr(addr),`
244			`.d(di),`
245			`.we(we),`
246			`.oe(oe),`
247			`.me(ce),`
248			`.q(doq)`
249			`);`
250
251			`else
252
253			`ifdef OR1200_VIRTUALSILICON_SSP
254
255			`//`
256			`// Instantiation of ASIC memory:`
257			`//`
258			`// Virtual Silicon Single-Port Synchronous SRAM`
259			`//`
260			`ifdef UNUSED
261			`vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(`
262			`else
263			`ifdef OR1200_BIST
264			`vs_hdsp_512x20_bist vs_ssp(`
265			`else
266			`vs_hdsp_512x20 vs_ssp(`
267			`endif
268			`endif
269			`ifdef OR1200_BIST
270			`// RAM BIST`
271			`.mbist_si_i(mbist_si_i),`
272			`.mbist_so_o(mbist_so_o),`
273			`.mbist_ctrl_i(mbist_ctrl_i),`
274			`endif
275			`.CK(clk),`
276			`.ADR(addr),`
277			`.DI(di),`
278			`.WEN(~we),`
279			`.CEN(~ce),`
280			`.OEN(~oe),`
281			`.DOUT(doq)`
282			`);`
283
284			`else
285
286			`ifdef OR1200_XILINX_RAMB4
287
288			`//`
289			`// Instantiation of FPGA memory:`
290			`//`
291			`// Virtex/Spartan2`
292			`//`
293
294			`//`
295			`// Block 0`
296			`//`
297			`RAMB4_S8 ramb4_s8_0(`
298			`.CLK(clk),`
299			`.RST(1'b0),`
300			`.ADDR(addr),`
301			`.DI(di[7:0]),`
302			`.EN(ce),`
303			`.WE(we),`
304			`.DO(doq[7:0])`
305			`);`
306
307			`//`
308			`// Block 1`
309			`//`
310			`RAMB4_S8 ramb4_s8_1(`
311			`.CLK(clk),`
312			`.RST(1'b0),`
313			`.ADDR(addr),`
314			`.DI(di[15:8]),`
315			`.EN(ce),`
316			`.WE(we),`
317			`.DO(doq[15:8])`
318			`);`
319
320			`//`
321			`// Block 2`
322			`//`
323			`RAMB4_S8 ramb4_s8_2(`
324			`.CLK(clk),`
325			`.RST(1'b0),`
326			`.ADDR(addr),`
327			`.DI({4'b0000, di[19:16]}),`
328			`.EN(ce),`
329			`.WE(we),`
330			`.DO({unconnected, doq[19:16]})`
331			`);`
332
333			`else
334
335			`ifdef OR1200_XILINX_RAMB16
336
337			`//`
338			`// Instantiation of FPGA memory:`
339			`//`
340			`// Virtex4/Spartan3E`
341			`//`
342			`// Added By Nir Mor`
343			`//`
344
345			`RAMB16_S36 ramb16_s36(`
346			`.CLK(clk),`
347			`.SSR(1'b0),`
348			`.ADDR(addr),`
349			`.DI({12'h000,di}),`
350			`.DIP(4'h0),`
351			`.EN(ce),`
352			`.WE(we),`
353			`.DO({unconnected,doq}),`
354			`.DOP()`
355			`);`
356
357			`else
358
359			`ifdef OR1200_ALTERA_LPM
360
361			`//`
362			`// Instantiation of FPGA memory:`
363			`//`
364			`// Altera LPM`
365			`//`
366			`// Added By Jamil Khatib`
367			`//`
368
369			`wire wr;`
370
371			`assign wr = ce & we;`
372
373			`initial $display("Using Altera LPM.");`
374
375			`lpm_ram_dq lpm_ram_dq_component (`
376			`.address(addr),`
377			`.inclock(clk),`
378			`.outclock(clk),`
379			`.data(di),`
380			`.we(wr),`
381			`.q(doq)`
382			`);`
383
384			`defparam lpm_ram_dq_component.lpm_width = dw,`
385			`lpm_ram_dq_component.lpm_widthad = aw,`
386			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
387			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
388			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
389			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
390			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
391
392			`else
393
394			`//`
395			`// Generic single-port synchronous RAM model`
396			`//`
397
398			`//`
399			`// Generic RAM's registers and wires`
400			`//`
401			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
402			`reg [aw-1:0] addr_reg; // RAM address register`
403
404			`//`
405			`// Data output drivers`
406			`//`
407			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
408
409			`//`
410			`// RAM address register`
411			`//`
412	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
413			if (rst == `OR1200_RST_VALUE)
414	350	julius	`addr_reg <= {aw{1'b0}};`
415			`else if (ce)`
416			`addr_reg <= addr;`
417
418			`//`
419			`// RAM write`
420			`//`
421			`always @(posedge clk)`
422			`if (ce && we)`
423			`mem[addr] <= di;`
424
425			`endif // !OR1200_ALTERA_LPM
426			`endif // !OR1200_XILINX_RAMB16
427			`endif // !OR1200_XILINX_RAMB4
428			`endif // !OR1200_VIRTUALSILICON_SSP
429			`endif // !OR1200_VIRAGE_SSP
430			`endif // !OR1200_AVANT_ATP
431			`endif // !OR1200_ARTISAN_SSP
432
433			`endmodule`