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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_spram_64x14.v] - Blame information for rev 618

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Line No. Rev Author Line
1 350 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Single-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common single-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  single-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Supported ASIC RAMs are:                                    ////
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////  - Artisan Single-Port Sync RAM                              ////
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////  - Avant! Two-Port Sync RAM (*)                              ////
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////  - Virage Single-Port Sync RAM                               ////
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////  - Virtual Silicon Single-Port Sync RAM                      ////
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////                                                              ////
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////  Supported FPGA RAMs are:                                    ////
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////  - Xilinx Virtex RAMB16                                      ////
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////  - Xilinx Virtex RAMB4                                       ////
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////  - Altera LPM                                                ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - xilinx rams need external tri-state logic                ////
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////   - fix avant! two-port ram                                  ////
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////   - add additional RAMs                                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66
// $Log: or1200_spram_64x14.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
68
// Minor update: 
69
// Coding style changed.
70
//
71
// Revision 1.9  2005/10/19 11:37:56  jcastillo
72
// Added support for RAMB16 Xilinx4/Spartan3 primitives
73
//
74
// Revision 1.8  2004/06/08 18:15:32  lampret
75
// Changed behavior of the simulation generic models
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//
77
// Revision 1.7  2004/04/05 08:29:57  lampret
78
// Merged branch_qmem into main tree.
79
//
80
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
81
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
82
//
83
// Revision 1.3  2003/04/07 01:19:07  lampret
84
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
85
//
86
// Revision 1.2  2002/10/17 20:04:41  lampret
87
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
88
//
89
// Revision 1.1  2002/01/03 08:16:15  lampret
90
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
91
//
92
// Revision 1.7  2001/11/02 18:57:14  lampret
93
// Modified virtual silicon instantiations.
94
//
95
// Revision 1.6  2001/10/21 17:57:16  lampret
96
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
97
//
98
// Revision 1.5  2001/10/14 13:12:09  lampret
99
// MP3 version.
100
//
101
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
102
// no message
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//
104
// Revision 1.1  2001/08/09 13:39:33  lampret
105
// Major clean-up.
106
//
107
// Revision 1.2  2001/07/30 05:38:02  lampret
108
// Adding empty directories required by HDL coding guidelines
109
//
110
//
111
 
112
// synopsys translate_off
113
`include "timescale.v"
114
// synopsys translate_on
115
`include "or1200_defines.v"
116
 
117
module or1200_spram_64x14(
118
`ifdef OR1200_BIST
119
        // RAM BIST
120
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
121
`endif
122
        // Generic synchronous single-port RAM interface
123
        clk, rst, ce, we, oe, addr, di, doq
124
);
125
 
126
//
127
// Default address and data buses width
128
//
129
parameter aw = 6;
130
parameter dw = 14;
131
 
132
`ifdef OR1200_BIST
133
//
134
// RAM BIST
135
//
136
input mbist_si_i;
137
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
138
output mbist_so_o;
139
`endif
140
 
141
//
142
// Generic synchronous single-port RAM interface
143
//
144
input                   clk;    // Clock
145
input                   rst;    // Reset
146
input                   ce;     // Chip enable input
147
input                   we;     // Write enable input
148
input                   oe;     // Output enable input
149
input   [aw-1:0] addr;   // address bus inputs
150
input   [dw-1:0] di;     // input data bus
151
output  [dw-1:0] doq;    // output data bus
152
 
153
//
154
// Internal wires and registers
155
//
156
 
157
`ifdef OR1200_XILINX_RAMB4
158
wire    [1:0]            unconnected;
159
`else
160
`ifdef OR1200_XILINX_RAMB16
161
wire    [1:0]            unconnected;
162
`endif // !OR1200_XILINX_RAMB16
163
`endif // !OR1200_XILINX_RAMB4
164
 
165
`ifdef OR1200_ARTISAN_SSP
166
`else
167
`ifdef OR1200_VIRTUALSILICON_SSP
168
`else
169
`ifdef OR1200_BIST
170
assign mbist_so_o = mbist_si_i;
171
`endif
172
`endif
173
`endif
174
 
175
`ifdef OR1200_ARTISAN_SSP
176
 
177
//
178
// Instantiation of ASIC memory:
179
//
180
// Artisan Synchronous Single-Port RAM (ra1sh)
181
//
182
`ifdef UNUSED
183
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
184
`else
185
`ifdef OR1200_BIST
186
art_hssp_64x14_bist artisan_ssp(
187
`else
188
art_hssp_64x14 artisan_ssp(
189
`endif
190
`endif
191
`ifdef OR1200_BIST
192
        // RAM BIST
193
        .mbist_si_i(mbist_si_i),
194
        .mbist_so_o(mbist_so_o),
195
        .mbist_ctrl_i(mbist_ctrl_i),
196
`endif
197
        .CLK(clk),
198
        .CEN(~ce),
199
        .WEN(~we),
200
        .A(addr),
201
        .D(di),
202
        .OEN(~oe),
203
        .Q(doq)
204
);
205
 
206
`else
207
 
208
`ifdef OR1200_AVANT_ATP
209
 
210
//
211
// Instantiation of ASIC memory:
212
//
213
// Avant! Asynchronous Two-Port RAM
214
//
215
avant_atp avant_atp(
216
        .web(~we),
217
        .reb(),
218
        .oeb(~oe),
219
        .rcsb(),
220
        .wcsb(),
221
        .ra(addr),
222
        .wa(addr),
223
        .di(di),
224
        .doq(doq)
225
);
226
 
227
`else
228
 
229
`ifdef OR1200_VIRAGE_SSP
230
 
231
//
232
// Instantiation of ASIC memory:
233
//
234
// Virage Synchronous 1-port R/W RAM
235
//
236
virage_ssp virage_ssp(
237
        .clk(clk),
238
        .adr(addr),
239
        .d(di),
240
        .we(we),
241
        .oe(oe),
242
        .me(ce),
243
        .q(doq)
244
);
245
 
246
`else
247
 
248
`ifdef OR1200_VIRTUALSILICON_SSP
249
 
250
//
251
// Instantiation of ASIC memory:
252
//
253
// Virtual Silicon Single-Port Synchronous SRAM
254
//
255
`ifdef UNUSED
256
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
257
`else
258
`ifdef OR1200_BIST
259
vs_hdsp_64x14_bist vs_ssp(
260
`else
261
vs_hdsp_64x14 vs_ssp(
262
`endif
263
`endif
264
`ifdef OR1200_BIST
265
        // RAM BIST
266
        .mbist_si_i(mbist_si_i),
267
        .mbist_so_o(mbist_so_o),
268
        .mbist_ctrl_i(mbist_ctrl_i),
269
`endif
270
        .CK(clk),
271
        .ADR(addr),
272
        .DI(di),
273
        .WEN(~we),
274
        .CEN(~ce),
275
        .OEN(~oe),
276
        .DOUT(doq)
277
);
278
 
279
`else
280
 
281
`ifdef OR1200_XILINX_RAMB4
282
 
283
//
284
// Instantiation of FPGA memory:
285
//
286
// Virtex/Spartan2
287
//
288
 
289
//
290
// Block 0
291
//
292
RAMB4_S16 ramb4_s16_0(
293
        .CLK(clk),
294
        .RST(1'b0),
295
        .ADDR({2'b00, addr}),
296
        .DI({2'b00, di[13:0]}),
297
        .EN(ce),
298
        .WE(we),
299
        .DO({unconnected, doq[13:0]})
300
);
301
 
302
`else
303
 
304
`ifdef OR1200_XILINX_RAMB16
305
 
306
//
307
// Instantiation of FPGA memory:
308
//
309
// Virtex4/Spartan3E
310
//
311
 
312
RAMB16_S18 ramb16_s18(
313
        .CLK(clk),
314
        .SSR(1'b0),
315
        .ADDR({4'b0000, addr}),
316
        .DI({2'b00, di[13:0]}),
317
        .DIP(2'b00),
318
        .EN(ce),
319
        .WE(we),
320
        .DO({unconnected, doq[13:0]}),
321
        .DOP()
322
);
323
 
324
`else
325
 
326
`ifdef OR1200_ALTERA_LPM
327
 
328
//
329
// Instantiation of FPGA memory:
330
//
331
// Altera LPM
332
//
333
// Added By Jamil Khatib
334
//
335
 
336
wire    wr;
337
 
338
assign  wr = ce & we;
339
 
340
initial $display("Using Altera LPM.");
341
 
342
lpm_ram_dq lpm_ram_dq_component (
343
        .address(addr),
344
        .inclock(clk),
345
        .outclock(clk),
346
        .data(di),
347
        .we(wr),
348
        .q(doq)
349
);
350
 
351
defparam lpm_ram_dq_component.lpm_width = dw,
352
        lpm_ram_dq_component.lpm_widthad = aw,
353
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
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        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
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        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
356
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
357
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
358
 
359
`else
360
 
361
//
362
// Generic single-port synchronous RAM model
363
//
364
 
365
//
366
// Generic RAM's registers and wires
367
//
368
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
369
reg     [aw-1:0] addr_reg;               // RAM address register
370
 
371
//
372
// Data output drivers
373
//
374
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
375
 
376
//
377
// RAM address register
378
//
379 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
380
        if (rst == `OR1200_RST_VALUE)
381 350 julius
                addr_reg <=  {aw{1'b0}};
382
        else if (ce)
383
                addr_reg <=  addr;
384
 
385
//
386
// RAM write
387
//
388
always @(posedge clk)
389
        if (ce && we)
390
                mem[addr] <=  di;
391
 
392
`endif  // !OR1200_ALTERA_LPM
393
`endif  // !OR1200_XILINX_RAMB16
394
`endif  // !OR1200_XILINX_RAMB4
395
`endif  // !OR1200_VIRTUALSILICON_SSP
396
`endif  // !OR1200_VIRAGE_SSP
397
`endif  // !OR1200_AVANT_ATP
398
`endif  // !OR1200_ARTISAN_SSP
399
 
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endmodule

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