URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_sprs.v] - Blame information for rev 710

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's interface to SPRs                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Decoding of SPR addresses and access to SPRs                ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_sprs.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_sprs(
                   // Clk & Rst
                   clk, rst,
 
                   // Internal CPU interface
                   flagforw, flag_we, flag, cyforw, cy_we, carry,
                   ovforw, ov_we,
                   addrbase, addrofs, dat_i, branch_op, ex_spr_read,
                   ex_spr_write,
                   epcr, eear, esr, except_started,
                   to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
                   spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,
                   spr_dat_mac,
 
                   boot_adr_sel_i,
 
                   // Floating point SPR input
                   fpcsr, fpcsr_we, spr_dat_fpu,
 
                   // From/to other RISC units
                   spr_dat_pic, spr_dat_tt, spr_dat_pm,
                   spr_dat_dmmu, spr_dat_immu, spr_dat_du,
                   spr_addr, spr_dat_o, spr_cs, spr_we,
 
                   du_addr, du_dat_du, du_read,
                   du_write, du_dat_cpu
 
                   );
 
   parameter width = `OR1200_OPERAND_WIDTH;
 
   //
   // I/O Ports
   //
 
   //
   // Internal CPU interface
   //
   input                                clk;            // Clock
   input                                rst;            // Reset
   input                                flagforw;       // From ALU
   input                                flag_we;        // From ALU
   output                               flag;           // SR[F]
   input                                cyforw;         // From ALU
   input                                cy_we;          // From ALU
   output                               carry;          // SR[CY]
   input                                ovforw;         // From ALU
   input                                ov_we;          // From ALU
   input [width-1:0]                     addrbase;       // SPR base address
   input [15:0]                  addrofs;        // SPR offset
   input [width-1:0]                     dat_i;          // SPR write data
   input                                ex_spr_read;    // l.mfspr in EX
   input                                ex_spr_write;   // l.mtspr in EX
   input [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;      // Branch operation
   input [width-1:0]                     epcr /* verilator public */;// EPCR0
   input [width-1:0]                     eear /* verilator public */;// EEAR0
   input [`OR1200_SR_WIDTH-1:0]  esr /* verilator public */; // ESR0
   input                                except_started; // Exception was started
   output [width-1:0]                    to_wbmux;       // For l.mfspr
   output                               epcr_we;        // EPCR0 write enable
   output                               eear_we;        // EEAR0 write enable
   output                               esr_we;         // ESR0 write enable
   output                               pc_we;          // PC write enable
   output                               sr_we;          // Write enable SR
   output [`OR1200_SR_WIDTH-1:0]         to_sr;          // Data to SR
   output [`OR1200_SR_WIDTH-1:0]         sr /* verilator public */;// SR
   input [31:0]                  spr_dat_cfgr;   // Data from CFGR
   input [31:0]                  spr_dat_rf;     // Data from RF
   input [31:0]                  spr_dat_npc;    // Data from NPC
   input [31:0]                  spr_dat_ppc;    // Data from PPC   
   input [31:0]                  spr_dat_mac;    // Data from MAC
   input                                boot_adr_sel_i;
 
   input [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;  // FPCSR
   output                               fpcsr_we;       // Write enable FPCSR   
   input [31:0]                  spr_dat_fpu;    // Data from FPU
 
   //
   // To/from other RISC units
   //
   input [31:0]                  spr_dat_pic;    // Data from PIC
   input [31:0]                  spr_dat_tt;     // Data from TT
   input [31:0]                  spr_dat_pm;     // Data from PM
   input [31:0]                  spr_dat_dmmu;   // Data from DMMU
   input [31:0]                  spr_dat_immu;   // Data from IMMU
   input [31:0]                  spr_dat_du;     // Data from DU
   output [31:0]                         spr_addr;       // SPR Address
   output [31:0]                         spr_dat_o;      // Data to unit
   output [31:0]                         spr_cs;         // Unit select
   output                               spr_we;         // SPR write enable
 
   //
   // To/from Debug Unit
   //
   input [width-1:0]                     du_addr;        // Address
   input [width-1:0]                     du_dat_du;      // Data from DU to SPRS
   input                                du_read;        // Read qualifier
   input                                du_write;       // Write qualifier
   output [width-1:0]                    du_dat_cpu;     // Data from SPRS to DU
 
   //
   // Internal regs & wires
   //
   reg [`OR1200_SR_WIDTH-1:0]            sr_reg;         // SR
   reg                                  sr_reg_bit_eph; // SR_EPH bit
   reg                                  sr_reg_bit_eph_select;// SR_EPH select
   wire                                 sr_reg_bit_eph_muxed;// SR_EPH muxed bit
   reg [`OR1200_SR_WIDTH-1:0]            sr;                     // SR
   reg [width-1:0]                       to_wbmux;       // For l.mfspr
   wire                                 cfgr_sel;       // Select for cfg regs
   wire                                 rf_sel;         // Select for RF
   wire                                 npc_sel;        // Select for NPC
   wire                                 ppc_sel;        // Select for PPC
   wire                                 sr_sel;         // Select for SR        
   wire                                 epcr_sel;       // Select for EPCR0
   wire                                 eear_sel;       // Select for EEAR0
   wire                                 esr_sel;        // Select for ESR0
   wire                                 fpcsr_sel;      // Select for FPCSR   
   wire [31:0]                           sys_data;// Read data from system SPRs
   wire                                 du_access;// Debug unit access
   reg [31:0]                            unqualified_cs; // Unqualified selects
   wire                                 ex_spr_write; // jb
 
   //
   // Decide if it is debug unit access
   //
   assign du_access = du_read | du_write;
 
   //
   // Generate SPR address from base address and offset
   // OR from debug unit address
   //
   assign spr_addr = du_access ? du_addr : (addrbase | {16'h0000, addrofs});
 
   //
   // SPR is written by debug unit or by l.mtspr
   //
   assign spr_dat_o = du_write ? du_dat_du : dat_i;
 
   //
   // debug unit data input:
   //  - read of SPRS by debug unit
   //  - write into debug unit SPRs by debug unit itself
   //  - write into debug unit SPRs by l.mtspr
   //
   assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;
 
   //
   // Write into SPRs when DU or l.mtspr
   //
   assign spr_we = du_write | ( ex_spr_write & !du_access );
 
 
   //
   // Qualify chip selects
   //
   assign spr_cs = unqualified_cs & {32{du_read | du_write | ex_spr_read |
                                        (ex_spr_write & sr[`OR1200_SR_SM])}};
 
   //
   // Decoding of groups
   //
   always @(spr_addr)
     case (spr_addr[`OR1200_SPR_GROUP_BITS])    // synopsys parallel_case
       `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs
         = 32'b00000000_00000000_00000000_00000001;
       `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs
         = 32'b00000000_00000000_00000000_00000010;
       `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs
         = 32'b00000000_00000000_00000000_00000100;
       `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs
         = 32'b00000000_00000000_00000000_00001000;
       `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs
         = 32'b00000000_00000000_00000000_00010000;
       `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs
         = 32'b00000000_00000000_00000000_00100000;
       `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs
         = 32'b00000000_00000000_00000000_01000000;
       `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs
         = 32'b00000000_00000000_00000000_10000000;
       `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs
         = 32'b00000000_00000000_00000001_00000000;
       `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs
         = 32'b00000000_00000000_00000010_00000000;
       `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs
         = 32'b00000000_00000000_00000100_00000000;
       `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs
         = 32'b00000000_00000000_00001000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs
         = 32'b00000000_00000000_00010000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs
         = 32'b00000000_00000000_00100000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs
         = 32'b00000000_00000000_01000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs
         = 32'b00000000_00000000_10000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs
         = 32'b00000000_00000001_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs
         = 32'b00000000_00000010_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs
         = 32'b00000000_00000100_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs
         = 32'b00000000_00001000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs
         = 32'b00000000_00010000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs
         = 32'b00000000_00100000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs
         = 32'b00000000_01000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs
         = 32'b00000000_10000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs
         = 32'b00000001_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs
         = 32'b00000010_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs
         = 32'b00000100_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs
         = 32'b00001000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs
         = 32'b00010000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs
         = 32'b00100000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs
         = 32'b01000000_00000000_00000000_00000000;
       `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs
         = 32'b10000000_00000000_00000000_00000000;
     endcase
 
   //
   // SPRs System Group
   //
 
   //
   // What to write into SR
   //
   assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
            = (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_DSX],1'b0} :
              (branch_op == `OR1200_BRANCHOP_RFE) ?
              esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
              {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
              sr[`OR1200_SR_FO:`OR1200_SR_OVE];
   assign to_sr[`OR1200_SR_TED]
            = (except_started) ? 1'b1 :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
              sr[`OR1200_SR_TED];
   assign to_sr[`OR1200_SR_OV]
            = (except_started) ? sr[`OR1200_SR_OV] :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_OV] :
              ov_we ? ovforw :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
              sr[`OR1200_SR_OV];
   assign to_sr[`OR1200_SR_CY]
            = (except_started) ? sr[`OR1200_SR_CY] :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
              cy_we ? cyforw :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
              sr[`OR1200_SR_CY];
   assign to_sr[`OR1200_SR_F]
            = (except_started) ? sr[`OR1200_SR_F] :
              (branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
              flag_we ? flagforw :
              (spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
              sr[`OR1200_SR_F];
 
   assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM]
            = (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00,
                                  sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
              (branch_op == `OR1200_BRANCHOP_RFE) ?
              esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ?
              spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
              sr[`OR1200_SR_CE:`OR1200_SR_SM];
 
   //
   // Selects for system SPRs
   //
   assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                      (spr_addr[10:4] == `OR1200_SPR_CFGR));
   assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                    (spr_addr[10:5] == `OR1200_SPR_RF));
   assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                     (spr_addr[10:0] == `OR1200_SPR_NPC));
   assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                     (spr_addr[10:0] == `OR1200_SPR_PPC));
   assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                    (spr_addr[10:0] == `OR1200_SPR_SR));
   assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                      (spr_addr[10:0] == `OR1200_SPR_EPCR));
   assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                      (spr_addr[10:0] == `OR1200_SPR_EEAR));
   assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                     (spr_addr[10:0] == `OR1200_SPR_ESR));
   assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
                       (spr_addr[10:0] == `OR1200_SPR_FPCSR));
 
 
   //
   // Write enables for system SPRs
   //
   assign sr_we = (spr_we && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) |
                  flag_we | cy_we | ov_we;
   assign pc_we = (du_write && (npc_sel | ppc_sel));
   assign epcr_we = (spr_we && epcr_sel);
   assign eear_we = (spr_we && eear_sel);
   assign esr_we = (spr_we && esr_sel);
   assign fpcsr_we = (spr_we && fpcsr_sel);
 
   //
   // Output from system SPRs
   //
   assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) |
                     (spr_dat_rf & {32{rf_sel}}) |
                     (spr_dat_npc & {32{npc_sel}}) |
                     (spr_dat_ppc & {32{ppc_sel}}) |
                     ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) |
                     (epcr & {32{epcr_sel}}) |
                     (eear & {32{eear_sel}}) |
                     ({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
                      {32{fpcsr_sel}}) |
                     ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
 
   //
   // Flag alias
   //
   assign flag = sr[`OR1200_SR_F];
 
   //
   // Carry alias
   //
   assign carry = sr[`OR1200_SR_CY];
 
   //
   // Supervision register
   //
   always @(posedge clk or `OR1200_RST_EVENT rst)
     if (rst == `OR1200_RST_VALUE)
       sr_reg <=  {2'b01, // Fixed one.
                   `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
     else if (except_started)
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
     else if (sr_we)
       sr_reg <=  to_sr[`OR1200_SR_WIDTH-1:0];
 
   // EPH part of Supervision register
   always @(posedge clk or `OR1200_RST_EVENT rst)
     // default value 
     if (rst == `OR1200_RST_VALUE) begin
        sr_reg_bit_eph <=  `OR1200_SR_EPH_DEF;
        // select async. value due to reset state
        sr_reg_bit_eph_select <=  1'b1;
     end
   // selected value (different from default) is written into FF after reset 
   // state
     else if (sr_reg_bit_eph_select) begin
        // dynamic value can only be assigned to FF out of reset!
        sr_reg_bit_eph <=  boot_adr_sel_i;
        sr_reg_bit_eph_select <=  1'b0; // select FF value
     end
     else if (sr_we) begin
        sr_reg_bit_eph <=  to_sr[`OR1200_SR_EPH];
     end
 
   // select async. value of EPH bit after reset 
   assign       sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ?
                                       boot_adr_sel_i : sr_reg_bit_eph;
 
   // EPH part joined together with rest of Supervision register
   always @(sr_reg or sr_reg_bit_eph_muxed)
     sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
           sr_reg[`OR1200_SR_WIDTH-4:0]};
 
`ifdef verilator
   // Function to access various sprs (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
 
   function [31:0] get_sr;
      // verilator public
      get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
   endfunction // get_sr
 
   function [31:0] get_epcr;
      // verilator public
      get_epcr = epcr;
   endfunction // get_epcr
 
   function [31:0] get_eear;
      // verilator public
      get_eear = eear;
   endfunction // get_eear
 
   function [31:0] get_esr;
      // verilator public
      get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
   endfunction // get_esr
 
`endif
 
   //
   // MTSPR/MFSPR interface
   //
   always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
            spr_dat_fpu or
            spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
      casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
        `OR1200_SPR_GROUP_SYS:
          to_wbmux = sys_data;
        `OR1200_SPR_GROUP_TT:
          to_wbmux = spr_dat_tt;
        `OR1200_SPR_GROUP_PIC:
          to_wbmux = spr_dat_pic;
        `OR1200_SPR_GROUP_PM:
          to_wbmux = spr_dat_pm;
        `OR1200_SPR_GROUP_DMMU:
          to_wbmux = spr_dat_dmmu;
        `OR1200_SPR_GROUP_IMMU:
          to_wbmux = spr_dat_immu;
        `OR1200_SPR_GROUP_MAC:
          to_wbmux = spr_dat_mac;
        `OR1200_SPR_GROUP_FPU:
          to_wbmux = spr_dat_fpu;
        default: //`OR1200_SPR_GROUP_DU:
          to_wbmux = spr_dat_du;
      endcase
   end
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's interface to SPRs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Decoding of SPR addresses and access to SPRs ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_sprs.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Major update:`
47			`// Structure reordered and bugs fixed.`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_sprs(`
55	456	julius	`// Clk & Rst`
56			`clk, rst,`
57	350	julius
58	456	julius	`// Internal CPU interface`
59			`flagforw, flag_we, flag, cyforw, cy_we, carry,`
60	502	julius	`ovforw, ov_we,`
61	456	julius	`addrbase, addrofs, dat_i, branch_op, ex_spr_read,`
62			`ex_spr_write,`
63			`epcr, eear, esr, except_started,`
64			`to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,`
65			`spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc,`
66			`spr_dat_mac,`
67
68			`boot_adr_sel_i,`
69	350	julius
70	456	julius	`// Floating point SPR input`
71			`fpcsr, fpcsr_we, spr_dat_fpu,`
72	350	julius
73	456	julius	`// From/to other RISC units`
74			`spr_dat_pic, spr_dat_tt, spr_dat_pm,`
75			`spr_dat_dmmu, spr_dat_immu, spr_dat_du,`
76			`spr_addr, spr_dat_o, spr_cs, spr_we,`
77	350	julius
78	456	julius	`du_addr, du_dat_du, du_read,`
79			`du_write, du_dat_cpu`
80	350	julius
81	456	julius	`);`
82	350	julius
83	456	julius	parameter width = `OR1200_OPERAND_WIDTH;
84	350	julius
85	456	julius	`//`
86			`// I/O Ports`
87			`//`
88	350	julius
89	456	julius	`//`
90			`// Internal CPU interface`
91			`//`
92			`input clk; // Clock`
93			`input rst; // Reset`
94			`input flagforw; // From ALU`
95			`input flag_we; // From ALU`
96			`output flag; // SR[F]`
97			`input cyforw; // From ALU`
98			`input cy_we; // From ALU`
99			`output carry; // SR[CY]`
100	502	julius	`input ovforw; // From ALU`
101			`input ov_we; // From ALU`
102	456	julius	`input [width-1:0] addrbase; // SPR base address`
103			`input [15:0] addrofs; // SPR offset`
104			`input [width-1:0] dat_i; // SPR write data`
105			`input ex_spr_read; // l.mfspr in EX`
106			`input ex_spr_write; // l.mtspr in EX`
107			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
108			`input [width-1:0] epcr /* verilator public */;// EPCR0`
109			`input [width-1:0] eear /* verilator public */;// EEAR0`
110			input [`OR1200_SR_WIDTH-1:0] esr /* verilator public */; // ESR0
111			`input except_started; // Exception was started`
112			`output [width-1:0] to_wbmux; // For l.mfspr`
113			`output epcr_we; // EPCR0 write enable`
114			`output eear_we; // EEAR0 write enable`
115			`output esr_we; // ESR0 write enable`
116			`output pc_we; // PC write enable`
117			`output sr_we; // Write enable SR`
118			output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
119			output [`OR1200_SR_WIDTH-1:0] sr /* verilator public */;// SR
120			`input [31:0] spr_dat_cfgr; // Data from CFGR`
121			`input [31:0] spr_dat_rf; // Data from RF`
122			`input [31:0] spr_dat_npc; // Data from NPC`
123			`input [31:0] spr_dat_ppc; // Data from PPC`
124			`input [31:0] spr_dat_mac; // Data from MAC`
125			`input boot_adr_sel_i;`
126
127			input [`OR1200_FPCSR_WIDTH-1:0] fpcsr; // FPCSR
128			`output fpcsr_we; // Write enable FPCSR`
129			`input [31:0] spr_dat_fpu; // Data from FPU`
130	350	julius
131	456	julius	`//`
132			`// To/from other RISC units`
133			`//`
134			`input [31:0] spr_dat_pic; // Data from PIC`
135			`input [31:0] spr_dat_tt; // Data from TT`
136			`input [31:0] spr_dat_pm; // Data from PM`
137			`input [31:0] spr_dat_dmmu; // Data from DMMU`
138			`input [31:0] spr_dat_immu; // Data from IMMU`
139			`input [31:0] spr_dat_du; // Data from DU`
140			`output [31:0] spr_addr; // SPR Address`
141			`output [31:0] spr_dat_o; // Data to unit`
142			`output [31:0] spr_cs; // Unit select`
143			`output spr_we; // SPR write enable`
144	350	julius
145	456	julius	`//`
146			`// To/from Debug Unit`
147			`//`
148			`input [width-1:0] du_addr; // Address`
149			`input [width-1:0] du_dat_du; // Data from DU to SPRS`
150			`input du_read; // Read qualifier`
151			`input du_write; // Write qualifier`
152			`output [width-1:0] du_dat_cpu; // Data from SPRS to DU`
153	350	julius
154	456	julius	`//`
155			`// Internal regs & wires`
156			`//`
157			reg [`OR1200_SR_WIDTH-1:0] sr_reg; // SR
158			`reg sr_reg_bit_eph; // SR_EPH bit`
159			`reg sr_reg_bit_eph_select;// SR_EPH select`
160			`wire sr_reg_bit_eph_muxed;// SR_EPH muxed bit`
161			reg [`OR1200_SR_WIDTH-1:0] sr; // SR
162			`reg [width-1:0] to_wbmux; // For l.mfspr`
163			`wire cfgr_sel; // Select for cfg regs`
164			`wire rf_sel; // Select for RF`
165			`wire npc_sel; // Select for NPC`
166			`wire ppc_sel; // Select for PPC`
167			`wire sr_sel; // Select for SR`
168			`wire epcr_sel; // Select for EPCR0`
169			`wire eear_sel; // Select for EEAR0`
170			`wire esr_sel; // Select for ESR0`
171			`wire fpcsr_sel; // Select for FPCSR`
172			`wire [31:0] sys_data;// Read data from system SPRs`
173			`wire du_access;// Debug unit access`
174			`reg [31:0] unqualified_cs; // Unqualified selects`
175			`wire ex_spr_write; // jb`
176	350	julius
177	456	julius	`//`
178			`// Decide if it is debug unit access`
179			`//`
180			`assign du_access = du_read \| du_write;`
181	350	julius
182	456	julius	`//`
183			`// Generate SPR address from base address and offset`
184			`// OR from debug unit address`
185			`//`
186			`assign spr_addr = du_access ? du_addr : (addrbase \| {16'h0000, addrofs});`
187	350	julius
188	456	julius	`//`
189			`// SPR is written by debug unit or by l.mtspr`
190			`//`
191			`assign spr_dat_o = du_write ? du_dat_du : dat_i;`
192	350	julius
193	456	julius	`//`
194			`// debug unit data input:`
195			`// - read of SPRS by debug unit`
196			`// - write into debug unit SPRs by debug unit itself`
197			`// - write into debug unit SPRs by l.mtspr`
198			`//`
199			`assign du_dat_cpu = du_read ? to_wbmux : du_write ? du_dat_du : dat_i;`
200	350	julius
201	456	julius	`//`
202			`// Write into SPRs when DU or l.mtspr`
203			`//`
204			`assign spr_we = du_write \| ( ex_spr_write & !du_access );`
205	350	julius
206
207	456	julius	`//`
208			`// Qualify chip selects`
209			`//`
210			`assign spr_cs = unqualified_cs & {32{du_read \| du_write \| ex_spr_read \|`
211			(ex_spr_write & sr[`OR1200_SR_SM])}};
212	350	julius
213	456	julius	`//`
214			`// Decoding of groups`
215			`//`
216			`always @(spr_addr)`
217			case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
218			`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs
219			`= 32'b00000000_00000000_00000000_00000001;`
220			`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs
221			`= 32'b00000000_00000000_00000000_00000010;`
222			`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs
223			`= 32'b00000000_00000000_00000000_00000100;`
224			`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs
225			`= 32'b00000000_00000000_00000000_00001000;`
226			`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs
227			`= 32'b00000000_00000000_00000000_00010000;`
228			`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs
229			`= 32'b00000000_00000000_00000000_00100000;`
230			`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs
231			`= 32'b00000000_00000000_00000000_01000000;`
232			`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs
233			`= 32'b00000000_00000000_00000000_10000000;`
234			`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs
235			`= 32'b00000000_00000000_00000001_00000000;`
236			`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs
237			`= 32'b00000000_00000000_00000010_00000000;`
238			`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs
239			`= 32'b00000000_00000000_00000100_00000000;`
240			`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs
241			`= 32'b00000000_00000000_00001000_00000000;`
242			`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs
243			`= 32'b00000000_00000000_00010000_00000000;`
244			`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs
245			`= 32'b00000000_00000000_00100000_00000000;`
246			`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs
247			`= 32'b00000000_00000000_01000000_00000000;`
248			`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs
249			`= 32'b00000000_00000000_10000000_00000000;`
250			`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs
251			`= 32'b00000000_00000001_00000000_00000000;`
252			`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs
253			`= 32'b00000000_00000010_00000000_00000000;`
254			`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs
255			`= 32'b00000000_00000100_00000000_00000000;`
256			`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs
257			`= 32'b00000000_00001000_00000000_00000000;`
258			`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs
259			`= 32'b00000000_00010000_00000000_00000000;`
260			`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs
261			`= 32'b00000000_00100000_00000000_00000000;`
262			`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs
263			`= 32'b00000000_01000000_00000000_00000000;`
264			`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs
265			`= 32'b00000000_10000000_00000000_00000000;`
266			`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs
267			`= 32'b00000001_00000000_00000000_00000000;`
268			`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs
269			`= 32'b00000010_00000000_00000000_00000000;`
270			`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs
271			`= 32'b00000100_00000000_00000000_00000000;`
272			`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs
273			`= 32'b00001000_00000000_00000000_00000000;`
274			`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs
275			`= 32'b00010000_00000000_00000000_00000000;`
276			`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs
277			`= 32'b00100000_00000000_00000000_00000000;`
278			`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs
279			`= 32'b01000000_00000000_00000000_00000000;`
280			`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs
281			`= 32'b10000000_00000000_00000000_00000000;`
282			`endcase`
283	350	julius
284	456	julius	`//`
285			`// SPRs System Group`
286			`//`
287	350	julius
288	456	julius	`//`
289			`// What to write into SR`
290			`//`
291	502	julius	assign to_sr[`OR1200_SR_FO:`OR1200_SR_OVE]
292			= (except_started) ? {sr[`OR1200_SR_FO:`OR1200_SR_DSX],1'b0} :
293	456	julius	(branch_op == `OR1200_BRANCHOP_RFE) ?
294	502	julius	esr[`OR1200_SR_FO:`OR1200_SR_OVE] : (spr_we && sr_sel) ?
295			{1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OVE]} :
296			sr[`OR1200_SR_FO:`OR1200_SR_OVE];
297	456	julius	assign to_sr[`OR1200_SR_TED]
298			`= (except_started) ? 1'b1 :`
299			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_TED] :
300			(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_TED] :
301			sr[`OR1200_SR_TED];
302	502	julius	assign to_sr[`OR1200_SR_OV]
303			= (except_started) ? sr[`OR1200_SR_OV] :
304			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_OV] :
305			`ov_we ? ovforw :`
306			(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_OV] :
307			sr[`OR1200_SR_OV];
308	456	julius	assign to_sr[`OR1200_SR_CY]
309			= (except_started) ? sr[`OR1200_SR_CY] :
310			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
311			`cy_we ? cyforw :`
312			(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
313			sr[`OR1200_SR_CY];
314			assign to_sr[`OR1200_SR_F]
315			= (except_started) ? sr[`OR1200_SR_F] :
316			(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
317			`flag_we ? flagforw :`
318			(spr_we && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
319			sr[`OR1200_SR_F];
320
321			assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM]
322			= (except_started) ? {sr[`OR1200_SR_CE:`OR1200_SR_LEE], 2'b00,
323			sr[`OR1200_SR_ICE:`OR1200_SR_DCE], 3'b001} :
324			(branch_op == `OR1200_BRANCHOP_RFE) ?
325			esr[`OR1200_SR_CE:`OR1200_SR_SM] : (spr_we && sr_sel) ?
326			spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM] :
327			sr[`OR1200_SR_CE:`OR1200_SR_SM];
328	350	julius
329	456	julius	`//`
330			`// Selects for system SPRs`
331			`//`
332			assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
333			(spr_addr[10:4] == `OR1200_SPR_CFGR));
334			assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
335			(spr_addr[10:5] == `OR1200_SPR_RF));
336			assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
337			(spr_addr[10:0] == `OR1200_SPR_NPC));
338			assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
339			(spr_addr[10:0] == `OR1200_SPR_PPC));
340			assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
341			(spr_addr[10:0] == `OR1200_SPR_SR));
342			assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
343			(spr_addr[10:0] == `OR1200_SPR_EPCR));
344			assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
345			(spr_addr[10:0] == `OR1200_SPR_EEAR));
346			assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
347			(spr_addr[10:0] == `OR1200_SPR_ESR));
348			assign fpcsr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] &&
349			(spr_addr[10:0] == `OR1200_SPR_FPCSR));
350	350	julius
351
352	456	julius	`//`
353			`// Write enables for system SPRs`
354			`//`
355			assign sr_we = (spr_we && sr_sel) \| (branch_op == `OR1200_BRANCHOP_RFE) \|
356	502	julius	`flag_we \| cy_we \| ov_we;`
357	456	julius	`assign pc_we = (du_write && (npc_sel \| ppc_sel));`
358			`assign epcr_we = (spr_we && epcr_sel);`
359			`assign eear_we = (spr_we && eear_sel);`
360			`assign esr_we = (spr_we && esr_sel);`
361			`assign fpcsr_we = (spr_we && fpcsr_sel);`
362	350	julius
363	456	julius	`//`
364			`// Output from system SPRs`
365			`//`
366			`assign sys_data = (spr_dat_cfgr & {32{cfgr_sel}}) \|`
367			`(spr_dat_rf & {32{rf_sel}}) \|`
368			`(spr_dat_npc & {32{npc_sel}}) \|`
369			`(spr_dat_ppc & {32{ppc_sel}}) \|`
370			({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{sr_sel}}) \|
371			`(epcr & {32{epcr_sel}}) \|`
372			`(eear & {32{eear_sel}}) \|`
373			({{32-`OR1200_FPCSR_WIDTH{1'b0}},fpcsr} &
374			`{32{fpcsr_sel}}) \|`
375			({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{esr_sel}});
376	350	julius
377	456	julius	`//`
378			`// Flag alias`
379			`//`
380			assign flag = sr[`OR1200_SR_F];
381	350	julius
382	456	julius	`//`
383			`// Carry alias`
384			`//`
385			assign carry = sr[`OR1200_SR_CY];
386	502	julius
387	456	julius	`//`
388			`// Supervision register`
389			`//`
390			always @(posedge clk or `OR1200_RST_EVENT rst)
391			if (rst == `OR1200_RST_VALUE)
392			`sr_reg <= {2'b01, // Fixed one.`
393			`OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-4{1'b0}}, 1'b1};
394			`else if (except_started)`
395			sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
396			`else if (sr_we)`
397			sr_reg <= to_sr[`OR1200_SR_WIDTH-1:0];
398	350	julius
399	456	julius	`// EPH part of Supervision register`
400			always @(posedge clk or `OR1200_RST_EVENT rst)
401			`// default value`
402			if (rst == `OR1200_RST_VALUE) begin
403			sr_reg_bit_eph <= `OR1200_SR_EPH_DEF;
404			`// select async. value due to reset state`
405			`sr_reg_bit_eph_select <= 1'b1;`
406			`end`
407			`// selected value (different from default) is written into FF after reset`
408			`// state`
409			`else if (sr_reg_bit_eph_select) begin`
410			`// dynamic value can only be assigned to FF out of reset!`
411			`sr_reg_bit_eph <= boot_adr_sel_i;`
412			`sr_reg_bit_eph_select <= 1'b0; // select FF value`
413			`end`
414			`else if (sr_we) begin`
415			sr_reg_bit_eph <= to_sr[`OR1200_SR_EPH];
416			`end`
417	350	julius
418	456	julius	`// select async. value of EPH bit after reset`
419			`assign sr_reg_bit_eph_muxed = (sr_reg_bit_eph_select) ?`
420			`boot_adr_sel_i : sr_reg_bit_eph;`
421	350	julius
422	456	julius	`// EPH part joined together with rest of Supervision register`
423			`always @(sr_reg or sr_reg_bit_eph_muxed)`
424			sr = {sr_reg[`OR1200_SR_WIDTH-1:`OR1200_SR_WIDTH-2], sr_reg_bit_eph_muxed,
425			sr_reg[`OR1200_SR_WIDTH-4:0]};
426	350	julius
427	353	julius	`ifdef verilator
428			`// Function to access various sprs (for Verilator). Have to hide this from`
429			`// simulator, since functions with no inputs are not allowed in IEEE`
430			`// 1364-2001.`
431
432			`function [31:0] get_sr;`
433			`// verilator public`
434	363	julius	get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
435	353	julius	`endfunction // get_sr`
436
437			`function [31:0] get_epcr;`
438			`// verilator public`
439			`get_epcr = epcr;`
440			`endfunction // get_epcr`
441
442			`function [31:0] get_eear;`
443			`// verilator public`
444			`get_eear = eear;`
445			`endfunction // get_eear`
446
447			`function [31:0] get_esr;`
448			`// verilator public`
449	363	julius	get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
450	353	julius	`endfunction // get_esr`
451
452			`endif
453
454	456	julius	`//`
455			`// MTSPR/MFSPR interface`
456			`//`
457			`always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or`
458			`spr_dat_fpu or`
459			`spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin`
460			casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
461			`OR1200_SPR_GROUP_SYS:
462			`to_wbmux = sys_data;`
463			`OR1200_SPR_GROUP_TT:
464			`to_wbmux = spr_dat_tt;`
465			`OR1200_SPR_GROUP_PIC:
466			`to_wbmux = spr_dat_pic;`
467			`OR1200_SPR_GROUP_PM:
468			`to_wbmux = spr_dat_pm;`
469			`OR1200_SPR_GROUP_DMMU:
470			`to_wbmux = spr_dat_dmmu;`
471			`OR1200_SPR_GROUP_IMMU:
472			`to_wbmux = spr_dat_immu;`
473			`OR1200_SPR_GROUP_MAC:
474			`to_wbmux = spr_dat_mac;`
475			`OR1200_SPR_GROUP_FPU:
476			`to_wbmux = spr_dat_fpu;`
477			default: //`OR1200_SPR_GROUP_DU:
478			`to_wbmux = spr_dat_du;`
479			`endcase`
480			`end`
481	350	julius
482			`endmodule`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_sprs.v] - Blame information for rev 710