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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_top.v] - Blame information for rev 433

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200 Top Level                                            ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
6
////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
9
////  OR1200 Top Level                                            ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
18
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: or1200_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Major update: 
49
// Structure reordered. 
50
//
51
 
52
// synopsys translate_off
53
`include "timescale.v"
54
// synopsys translate_on
55
`include "or1200_defines.v"
56
 
57
module or1200_top(
58
        // System
59
        clk_i, rst_i, pic_ints_i, clmode_i,
60
 
61
        // Instruction WISHBONE INTERFACE
62
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
63
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
64
`ifdef OR1200_WB_CAB
65
        iwb_cab_o,
66
`endif
67
`ifdef OR1200_WB_B3
68
        iwb_cti_o, iwb_bte_o,
69
`endif
70
        // Data WISHBONE INTERFACE
71
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
72
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
73
`ifdef OR1200_WB_CAB
74
        dwb_cab_o,
75
`endif
76
`ifdef OR1200_WB_B3
77
        dwb_cti_o, dwb_bte_o,
78
`endif
79
 
80
        // External Debug Interface
81
        dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
82
        dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
83
 
84
`ifdef OR1200_BIST
85
        // RAM BIST
86
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
87
`endif
88
        // Power Management
89
        pm_cpustall_i,
90
        pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
91
        pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
92
 
93
,sig_tick
94
 
95
);
96
 
97
parameter dw = `OR1200_OPERAND_WIDTH;
98
parameter aw = `OR1200_OPERAND_WIDTH;
99
parameter ppic_ints = `OR1200_PIC_INTS;
100
 
101
//
102
// I/O
103
//
104
 
105
//
106
// System
107
//
108
input                   clk_i;
109
input                   rst_i;
110
input   [1:0]            clmode_i;       // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
111
input   [ppic_ints-1:0]  pic_ints_i;
112
 
113
//
114
// Instruction WISHBONE interface
115
//
116
input                   iwb_clk_i;      // clock input
117
input                   iwb_rst_i;      // reset input
118
input                   iwb_ack_i;      // normal termination
119
input                   iwb_err_i;      // termination w/ error
120
input                   iwb_rty_i;      // termination w/ retry
121
input   [dw-1:0] iwb_dat_i;      // input data bus
122
output                  iwb_cyc_o;      // cycle valid output
123
output  [aw-1:0] iwb_adr_o;      // address bus outputs
124
output                  iwb_stb_o;      // strobe output
125
output                  iwb_we_o;       // indicates write transfer
126
output  [3:0]            iwb_sel_o;      // byte select outputs
127
output  [dw-1:0] iwb_dat_o;      // output data bus
128
`ifdef OR1200_WB_CAB
129
output                  iwb_cab_o;      // indicates consecutive address burst
130
`endif
131
`ifdef OR1200_WB_B3
132
output  [2:0]            iwb_cti_o;      // cycle type identifier
133
output  [1:0]            iwb_bte_o;      // burst type extension
134
`endif
135
 
136
//
137
// Data WISHBONE interface
138
//
139
input                   dwb_clk_i;      // clock input
140
input                   dwb_rst_i;      // reset input
141
input                   dwb_ack_i;      // normal termination
142
input                   dwb_err_i;      // termination w/ error
143
input                   dwb_rty_i;      // termination w/ retry
144
input   [dw-1:0] dwb_dat_i;      // input data bus
145
output                  dwb_cyc_o;      // cycle valid output
146
output  [aw-1:0] dwb_adr_o;      // address bus outputs
147
output                  dwb_stb_o;      // strobe output
148
output                  dwb_we_o;       // indicates write transfer
149
output  [3:0]            dwb_sel_o;      // byte select outputs
150
output  [dw-1:0] dwb_dat_o;      // output data bus
151
`ifdef OR1200_WB_CAB
152
output                  dwb_cab_o;      // indicates consecutive address burst
153
`endif
154
`ifdef OR1200_WB_B3
155
output  [2:0]            dwb_cti_o;      // cycle type identifier
156
output  [1:0]            dwb_bte_o;      // burst type extension
157
`endif
158
 
159
//
160
// External Debug Interface
161
//
162
input                   dbg_stall_i;    // External Stall Input
163
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
164
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
165
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
166
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
167
output                  dbg_bp_o;       // Breakpoint Output
168
input                   dbg_stb_i;      // External Address/Data Strobe
169
input                   dbg_we_i;       // External Write Enable
170
input   [aw-1:0] dbg_adr_i;      // External Address Input
171
input   [dw-1:0] dbg_dat_i;      // External Data Input
172
output  [dw-1:0] dbg_dat_o;      // External Data Output
173
output                  dbg_ack_o;      // External Data Acknowledge (not WB compatible)
174
 
175
`ifdef OR1200_BIST
176
//
177
// RAM BIST
178
//
179
input mbist_si_i;
180
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
181
output mbist_so_o;
182
`endif
183
 
184
//
185
// Power Management
186
//
187
input                   pm_cpustall_i;
188
output  [3:0]            pm_clksd_o;
189
output                  pm_dc_gate_o;
190
output                  pm_ic_gate_o;
191
output                  pm_dmmu_gate_o;
192
output                  pm_immu_gate_o;
193
output                  pm_tt_gate_o;
194
output                  pm_cpu_gate_o;
195
output                  pm_wakeup_o;
196
output                  pm_lvolt_o;
197
 
198
 
199
//
200
// Internal wires and regs
201
//
202
 
203
//
204
// DC to SB
205
//
206
wire    [dw-1:0] dcsb_dat_dc;
207
wire    [aw-1:0] dcsb_adr_dc;
208
wire                    dcsb_cyc_dc;
209
wire                    dcsb_stb_dc;
210
wire                    dcsb_we_dc;
211
wire    [3:0]            dcsb_sel_dc;
212
wire                    dcsb_cab_dc;
213
wire    [dw-1:0] dcsb_dat_sb;
214
wire                    dcsb_ack_sb;
215
wire                    dcsb_err_sb;
216
 
217
//
218
// SB to BIU
219
//
220
wire    [dw-1:0] sbbiu_dat_sb;
221
wire    [aw-1:0] sbbiu_adr_sb;
222
wire                    sbbiu_cyc_sb;
223
wire                    sbbiu_stb_sb;
224
wire                    sbbiu_we_sb;
225
wire    [3:0]            sbbiu_sel_sb;
226
wire                    sbbiu_cab_sb;
227
wire    [dw-1:0] sbbiu_dat_biu;
228
wire                    sbbiu_ack_biu;
229
wire                    sbbiu_err_biu;
230
 
231
//
232
// IC to BIU
233
//
234
wire    [dw-1:0] icbiu_dat_ic;
235
wire    [aw-1:0] icbiu_adr_ic;
236
wire    [aw-1:0] icbiu_adr_ic_word;
237
wire                    icbiu_cyc_ic;
238
wire                    icbiu_stb_ic;
239
wire                    icbiu_we_ic;
240
wire    [3:0]            icbiu_sel_ic;
241
wire    [3:0]            icbiu_tag_ic;
242
wire                    icbiu_cab_ic;
243
wire    [dw-1:0] icbiu_dat_biu;
244
wire                    icbiu_ack_biu;
245
wire                    icbiu_err_biu;
246
wire    [3:0]            icbiu_tag_biu;
247
 
248
//
249
// SR Interface (this signal can be connected to the input pin)
250
//
251
wire                    boot_adr_sel = `OR1200_SR_EPH_DEF;
252
 
253
//
254
// CPU's SPR access to various RISC units (shared wires)
255
//
256
wire                    supv;
257
wire    [aw-1:0] spr_addr;
258
wire    [dw-1:0] spr_dat_cpu;
259
wire    [31:0]           spr_cs;
260
wire                    spr_we;
261 363 julius
wire                    mtspr_dc_done;
262
 
263 350 julius
//
264
// SB
265
//
266
wire                    sb_en;
267
 
268
//
269
// DMMU and CPU
270
//
271
wire                    dmmu_en;
272
wire    [31:0]           spr_dat_dmmu;
273
 
274
//
275
// DMMU and QMEM
276
//
277
wire                    qmemdmmu_err_qmem;
278
wire    [3:0]            qmemdmmu_tag_qmem;
279
wire    [aw-1:0] qmemdmmu_adr_dmmu;
280
wire                    qmemdmmu_cycstb_dmmu;
281
wire                    qmemdmmu_ci_dmmu;
282
 
283
//
284
// CPU and data memory subsystem
285
//
286
wire                    dc_en;
287
wire    [31:0]           dcpu_adr_cpu;
288
wire                    dcpu_cycstb_cpu;
289
wire                    dcpu_we_cpu;
290
wire    [3:0]            dcpu_sel_cpu;
291
wire    [3:0]            dcpu_tag_cpu;
292
wire    [31:0]           dcpu_dat_cpu;
293
wire    [31:0]           dcpu_dat_qmem;
294
wire                    dcpu_ack_qmem;
295
wire                    dcpu_rty_qmem;
296
wire                    dcpu_err_dmmu;
297
wire    [3:0]            dcpu_tag_dmmu;
298
wire                    dc_no_writethrough;
299
 
300
//
301
// IMMU and CPU
302
//
303
wire                    immu_en;
304
wire    [31:0]           spr_dat_immu;
305
 
306
//
307
// CPU and insn memory subsystem
308
//
309
wire                    ic_en;
310
wire    [31:0]           icpu_adr_cpu;
311
wire                    icpu_cycstb_cpu;
312
wire    [3:0]            icpu_sel_cpu;
313
wire    [3:0]            icpu_tag_cpu;
314
wire    [31:0]           icpu_dat_qmem;
315
wire                    icpu_ack_qmem;
316
wire    [31:0]           icpu_adr_immu;
317
wire                    icpu_err_immu;
318
wire    [3:0]            icpu_tag_immu;
319
wire                    icpu_rty_immu;
320
 
321
//
322
// IMMU and QMEM
323
//
324
wire    [aw-1:0] qmemimmu_adr_immu;
325
wire                    qmemimmu_rty_qmem;
326
wire                    qmemimmu_err_qmem;
327
wire    [3:0]            qmemimmu_tag_qmem;
328
wire                    qmemimmu_cycstb_immu;
329
wire                    qmemimmu_ci_immu;
330
 
331
//
332
// QMEM and IC
333
//
334
wire    [aw-1:0] icqmem_adr_qmem;
335
wire                    icqmem_rty_ic;
336
wire                    icqmem_err_ic;
337
wire    [3:0]            icqmem_tag_ic;
338
wire                    icqmem_cycstb_qmem;
339
wire                    icqmem_ci_qmem;
340
wire    [31:0]           icqmem_dat_ic;
341
wire                    icqmem_ack_ic;
342
 
343
//
344
// QMEM and DC
345
//
346
wire    [aw-1:0] dcqmem_adr_qmem;
347
wire                    dcqmem_rty_dc;
348
wire                    dcqmem_err_dc;
349
wire    [3:0]            dcqmem_tag_dc;
350
wire                    dcqmem_cycstb_qmem;
351
wire                    dcqmem_ci_qmem;
352
wire    [31:0]           dcqmem_dat_dc;
353
wire    [31:0]           dcqmem_dat_qmem;
354
wire                    dcqmem_we_qmem;
355
wire    [3:0]            dcqmem_sel_qmem;
356
wire                    dcqmem_ack_dc;
357
 
358
//
359
// Connection between CPU and PIC
360
//
361
wire    [dw-1:0] spr_dat_pic;
362
wire                    pic_wakeup;
363
wire                    sig_int;
364
 
365
//
366
// Connection between CPU and PM
367
//
368
wire    [dw-1:0] spr_dat_pm;
369
 
370
//
371
// CPU and TT
372
//
373
wire    [dw-1:0] spr_dat_tt;
374
output wire                     sig_tick; // jb
375
 
376
//
377
// Debug port and caches/MMUs
378
//
379
wire    [dw-1:0] spr_dat_du;
380
wire                    du_stall;
381
wire    [dw-1:0] du_addr;
382
wire    [dw-1:0] du_dat_du;
383
wire                    du_read;
384
wire                    du_write;
385
wire    [13:0]           du_except_trig;
386
wire    [13:0]           du_except_stop;
387
wire    [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
388
wire    [24:0]           du_dmr1;
389
wire    [dw-1:0] du_dat_cpu;
390
wire    [dw-1:0] du_lsu_store_dat;
391
wire    [dw-1:0] du_lsu_load_dat;
392
wire                    du_hwbkpt;
393
wire                    du_hwbkpt_ls_r = 1'b0;
394
wire                    flushpipe;
395
wire                    ex_freeze;
396
wire                    wb_freeze;
397
wire                    id_void;
398
wire                    ex_void;
399
wire    [31:0]           id_insn;
400
wire    [31:0]           ex_insn;
401
wire    [31:0]           wb_insn;
402
wire    [31:0]           id_pc;
403
wire    [31:0]           ex_pc;
404
wire    [31:0]           wb_pc;
405
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
406
wire    [31:0]           spr_dat_npc;
407
wire    [31:0]           rf_dataw;
408
wire                    abort_ex;
409
wire                    abort_mvspr;
410
 
411
`ifdef OR1200_BIST
412
//
413
// RAM BIST
414
//
415
wire                    mbist_immu_so;
416
wire                    mbist_ic_so;
417
wire                    mbist_dmmu_so;
418
wire                    mbist_dc_so;
419
wire                    mbist_qmem_so;
420
wire                    mbist_immu_si = mbist_si_i;
421
wire                    mbist_ic_si = mbist_immu_so;
422
wire                    mbist_qmem_si = mbist_ic_so;
423
wire                    mbist_dmmu_si = mbist_qmem_so;
424
wire                    mbist_dc_si = mbist_dmmu_so;
425
assign                  mbist_so_o = mbist_dc_so;
426
`endif
427
 
428
wire  [3:0] icqmem_sel_qmem;
429
wire  [3:0] icqmem_tag_qmem;
430
wire  [3:0] dcqmem_tag_qmem;
431
 
432
//
433
// Instantiation of Instruction WISHBONE BIU
434
//
435
or1200_wb_biu iwb_biu(
436
        // RISC clk, rst and clock control
437
        .clk(clk_i),
438
        .rst(rst_i),
439
        .clmode(clmode_i),
440
 
441
        // WISHBONE interface
442
        .wb_clk_i(iwb_clk_i),
443
        .wb_rst_i(iwb_rst_i),
444
        .wb_ack_i(iwb_ack_i),
445
        .wb_err_i(iwb_err_i),
446
        .wb_rty_i(iwb_rty_i),
447
        .wb_dat_i(iwb_dat_i),
448
        .wb_cyc_o(iwb_cyc_o),
449
        .wb_adr_o(iwb_adr_o),
450
        .wb_stb_o(iwb_stb_o),
451
        .wb_we_o(iwb_we_o),
452
        .wb_sel_o(iwb_sel_o),
453
        .wb_dat_o(iwb_dat_o),
454
`ifdef OR1200_WB_CAB
455
        .wb_cab_o(iwb_cab_o),
456
`endif
457
`ifdef OR1200_WB_B3
458
        .wb_cti_o(iwb_cti_o),
459
        .wb_bte_o(iwb_bte_o),
460
`endif
461
 
462
        // Internal RISC bus
463
        .biu_dat_i(icbiu_dat_ic),
464
        .biu_adr_i(icbiu_adr_ic_word),
465
        .biu_cyc_i(icbiu_cyc_ic),
466
        .biu_stb_i(icbiu_stb_ic),
467
        .biu_we_i(icbiu_we_ic),
468
        .biu_sel_i(icbiu_sel_ic),
469
        .biu_cab_i(icbiu_cab_ic),
470
        .biu_dat_o(icbiu_dat_biu),
471
        .biu_ack_o(icbiu_ack_biu),
472
        .biu_err_o(icbiu_err_biu)
473
);
474
assign icbiu_adr_ic_word = {icbiu_adr_ic[31:2], 2'h0};
475
 
476
//
477
// Instantiation of Data WISHBONE BIU
478
//
479
or1200_wb_biu dwb_biu(
480
        // RISC clk, rst and clock control
481
        .clk(clk_i),
482
        .rst(rst_i),
483
        .clmode(clmode_i),
484
 
485
        // WISHBONE interface
486
        .wb_clk_i(dwb_clk_i),
487
        .wb_rst_i(dwb_rst_i),
488
        .wb_ack_i(dwb_ack_i),
489
        .wb_err_i(dwb_err_i),
490
        .wb_rty_i(dwb_rty_i),
491
        .wb_dat_i(dwb_dat_i),
492
        .wb_cyc_o(dwb_cyc_o),
493
        .wb_adr_o(dwb_adr_o),
494
        .wb_stb_o(dwb_stb_o),
495
        .wb_we_o(dwb_we_o),
496
        .wb_sel_o(dwb_sel_o),
497
        .wb_dat_o(dwb_dat_o),
498
`ifdef OR1200_WB_CAB
499
        .wb_cab_o(dwb_cab_o),
500
`endif
501
`ifdef OR1200_WB_B3
502
        .wb_cti_o(dwb_cti_o),
503
        .wb_bte_o(dwb_bte_o),
504
`endif
505
 
506
        // Internal RISC bus
507
        .biu_dat_i(sbbiu_dat_sb),
508
        .biu_adr_i(sbbiu_adr_sb),
509
        .biu_cyc_i(sbbiu_cyc_sb),
510
        .biu_stb_i(sbbiu_stb_sb),
511
        .biu_we_i(sbbiu_we_sb),
512
        .biu_sel_i(sbbiu_sel_sb),
513
        .biu_cab_i(sbbiu_cab_sb),
514
        .biu_dat_o(sbbiu_dat_biu),
515
        .biu_ack_o(sbbiu_ack_biu),
516
        .biu_err_o(sbbiu_err_biu)
517
);
518
 
519
//
520
// Instantiation of IMMU
521
//
522
or1200_immu_top or1200_immu_top(
523
        // Rst and clk
524
        .clk(clk_i),
525
        .rst(rst_i),
526
 
527
`ifdef OR1200_BIST
528
        // RAM BIST
529
        .mbist_si_i(mbist_immu_si),
530
        .mbist_so_o(mbist_immu_so),
531
        .mbist_ctrl_i(mbist_ctrl_i),
532
`endif
533
 
534
        // CPU and IMMU
535
        .ic_en(ic_en),
536
        .immu_en(immu_en),
537
        .supv(supv),
538
        .icpu_adr_i(icpu_adr_cpu),
539
        .icpu_cycstb_i(icpu_cycstb_cpu),
540
        .icpu_adr_o(icpu_adr_immu),
541
        .icpu_tag_o(icpu_tag_immu),
542
        .icpu_rty_o(icpu_rty_immu),
543
        .icpu_err_o(icpu_err_immu),
544
 
545
        // SR Interface
546
        .boot_adr_sel_i(boot_adr_sel),
547
 
548
        // SPR access
549
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
550
        .spr_write(spr_we),
551
        .spr_addr(spr_addr),
552
        .spr_dat_i(spr_dat_cpu),
553
        .spr_dat_o(spr_dat_immu),
554
 
555
        // QMEM and IMMU
556
        .qmemimmu_rty_i(qmemimmu_rty_qmem),
557
        .qmemimmu_err_i(qmemimmu_err_qmem),
558
        .qmemimmu_tag_i(qmemimmu_tag_qmem),
559
        .qmemimmu_adr_o(qmemimmu_adr_immu),
560
        .qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
561
        .qmemimmu_ci_o(qmemimmu_ci_immu)
562
);
563
 
564
//
565
// Instantiation of Instruction Cache
566
//
567
or1200_ic_top or1200_ic_top(
568
        .clk(clk_i),
569
        .rst(rst_i),
570
 
571
`ifdef OR1200_BIST
572
        // RAM BIST
573
        .mbist_si_i(mbist_ic_si),
574
        .mbist_so_o(mbist_ic_so),
575
        .mbist_ctrl_i(mbist_ctrl_i),
576
`endif
577
 
578
        // IC and QMEM
579
        .ic_en(ic_en),
580
        .icqmem_adr_i(icqmem_adr_qmem),
581
        .icqmem_cycstb_i(icqmem_cycstb_qmem),
582
        .icqmem_ci_i(icqmem_ci_qmem),
583
        .icqmem_sel_i(icqmem_sel_qmem),
584
        .icqmem_tag_i(icqmem_tag_qmem),
585
        .icqmem_dat_o(icqmem_dat_ic),
586
        .icqmem_ack_o(icqmem_ack_ic),
587
        .icqmem_rty_o(icqmem_rty_ic),
588
        .icqmem_err_o(icqmem_err_ic),
589
        .icqmem_tag_o(icqmem_tag_ic),
590
 
591
        // SPR access
592
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
593
        .spr_write(spr_we),
594
        .spr_dat_i(spr_dat_cpu),
595
 
596
        // IC and BIU
597
        .icbiu_dat_o(icbiu_dat_ic),
598
        .icbiu_adr_o(icbiu_adr_ic),
599
        .icbiu_cyc_o(icbiu_cyc_ic),
600
        .icbiu_stb_o(icbiu_stb_ic),
601
        .icbiu_we_o(icbiu_we_ic),
602
        .icbiu_sel_o(icbiu_sel_ic),
603
        .icbiu_cab_o(icbiu_cab_ic),
604
        .icbiu_dat_i(icbiu_dat_biu),
605
        .icbiu_ack_i(icbiu_ack_biu),
606
        .icbiu_err_i(icbiu_err_biu)
607
);
608
 
609
//
610
// Instantiation of Instruction Cache
611
//
612
or1200_cpu or1200_cpu(
613
        .clk(clk_i),
614
        .rst(rst_i),
615
 
616
        // Connection QMEM and IFETCHER inside CPU
617
        .ic_en(ic_en),
618
        .icpu_adr_o(icpu_adr_cpu),
619
        .icpu_cycstb_o(icpu_cycstb_cpu),
620
        .icpu_sel_o(icpu_sel_cpu),
621
        .icpu_tag_o(icpu_tag_cpu),
622
        .icpu_dat_i(icpu_dat_qmem),
623
        .icpu_ack_i(icpu_ack_qmem),
624
        .icpu_rty_i(icpu_rty_immu),
625
        .icpu_adr_i(icpu_adr_immu),
626
        .icpu_err_i(icpu_err_immu),
627
        .icpu_tag_i(icpu_tag_immu),
628
 
629
        // Connection CPU to external Debug port
630
        .id_void(id_void),
631
        .id_insn(id_insn),
632
        .ex_void(ex_void),
633
        .ex_insn(ex_insn),
634
        .ex_freeze(ex_freeze),
635
        .wb_insn(wb_insn),
636
        .wb_freeze(wb_freeze),
637
        .id_pc(id_pc),
638
        .ex_pc(ex_pc),
639
        .wb_pc(wb_pc),
640
        .branch_op(branch_op),
641
        .rf_dataw(rf_dataw),
642
        .ex_flushpipe(flushpipe),
643
        .du_stall(du_stall),
644
        .du_addr(du_addr),
645
        .du_dat_du(du_dat_du),
646
        .du_read(du_read),
647
        .du_write(du_write),
648
        .du_except_trig(du_except_trig),
649
        .du_except_stop(du_except_stop),
650
        .du_dsr(du_dsr),
651
        .du_dmr1(du_dmr1),
652
        .du_hwbkpt(du_hwbkpt),
653
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
654
        .du_dat_cpu(du_dat_cpu),
655
        .du_lsu_store_dat(du_lsu_store_dat),
656
        .du_lsu_load_dat(du_lsu_load_dat),
657
        .abort_mvspr(abort_mvspr),
658
        .abort_ex(abort_ex),
659
 
660
        // Connection IMMU and CPU internally
661
        .immu_en(immu_en),
662
 
663
        // Connection QMEM and CPU
664
        .dc_en(dc_en),
665
        .dcpu_adr_o(dcpu_adr_cpu),
666
        .dcpu_cycstb_o(dcpu_cycstb_cpu),
667
        .dcpu_we_o(dcpu_we_cpu),
668
        .dcpu_sel_o(dcpu_sel_cpu),
669
        .dcpu_tag_o(dcpu_tag_cpu),
670
        .dcpu_dat_o(dcpu_dat_cpu),
671
        .dcpu_dat_i(dcpu_dat_qmem),
672
        .dcpu_ack_i(dcpu_ack_qmem),
673
        .dcpu_rty_i(dcpu_rty_qmem),
674
        .dcpu_err_i(dcpu_err_dmmu),
675
        .dcpu_tag_i(dcpu_tag_dmmu),
676
        .dc_no_writethrough(dc_no_writethrough),
677
 
678
        // Connection DMMU and CPU internally
679
        .dmmu_en(dmmu_en),
680
 
681
        // SR Interface
682
        .boot_adr_sel_i(boot_adr_sel),
683
 
684
        // SB Enable
685
        .sb_en(sb_en),
686
 
687
        // Connection PIC and CPU's EXCEPT
688
        .sig_int(sig_int),
689
        .sig_tick(sig_tick),
690
 
691
        // SPRs
692
        .supv(supv),
693
        .spr_addr(spr_addr),
694
        .spr_dat_cpu(spr_dat_cpu),
695
        .spr_dat_pic(spr_dat_pic),
696
        .spr_dat_tt(spr_dat_tt),
697
        .spr_dat_pm(spr_dat_pm),
698
        .spr_dat_dmmu(spr_dat_dmmu),
699
        .spr_dat_immu(spr_dat_immu),
700
        .spr_dat_du(spr_dat_du),
701
        .spr_dat_npc(spr_dat_npc),
702
        .spr_cs(spr_cs),
703
        .spr_we(spr_we),
704
        .mtspr_dc_done(mtspr_dc_done)
705
);
706
 
707
//
708
// Instantiation of DMMU
709
//
710
or1200_dmmu_top or1200_dmmu_top(
711
        // Rst and clk
712
        .clk(clk_i),
713
        .rst(rst_i),
714
 
715
`ifdef OR1200_BIST
716
        // RAM BIST
717
        .mbist_si_i(mbist_dmmu_si),
718
        .mbist_so_o(mbist_dmmu_so),
719
        .mbist_ctrl_i(mbist_ctrl_i),
720
`endif
721
 
722
        // CPU i/f
723
        .dc_en(dc_en),
724
        .dmmu_en(dmmu_en),
725
        .supv(supv),
726
        .dcpu_adr_i(dcpu_adr_cpu),
727
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
728
        .dcpu_we_i(dcpu_we_cpu),
729
        .dcpu_tag_o(dcpu_tag_dmmu),
730
        .dcpu_err_o(dcpu_err_dmmu),
731
 
732
        // SPR access
733
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
734
        .spr_write(spr_we),
735
        .spr_addr(spr_addr),
736
        .spr_dat_i(spr_dat_cpu),
737
        .spr_dat_o(spr_dat_dmmu),
738
 
739
        // QMEM and DMMU
740
        .qmemdmmu_err_i(qmemdmmu_err_qmem),
741
        .qmemdmmu_tag_i(qmemdmmu_tag_qmem),
742
        .qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
743
        .qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
744
        .qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
745
);
746
 
747
//
748
// Instantiation of Data Cache
749
//
750
or1200_dc_top or1200_dc_top(
751
        .clk(clk_i),
752
        .rst(rst_i),
753
 
754
`ifdef OR1200_BIST
755
        // RAM BIST
756
        .mbist_si_i(mbist_dc_si),
757
        .mbist_so_o(mbist_dc_so),
758
        .mbist_ctrl_i(mbist_ctrl_i),
759
`endif
760
 
761
        // DC and QMEM
762
        .dc_en(dc_en),
763
        .dcqmem_adr_i(dcqmem_adr_qmem),
764
        .dcqmem_cycstb_i(dcqmem_cycstb_qmem),
765
        .dcqmem_ci_i(dcqmem_ci_qmem),
766
        .dcqmem_we_i(dcqmem_we_qmem),
767
        .dcqmem_sel_i(dcqmem_sel_qmem),
768
        .dcqmem_tag_i(dcqmem_tag_qmem),
769
        .dcqmem_dat_i(dcqmem_dat_qmem),
770
        .dcqmem_dat_o(dcqmem_dat_dc),
771
        .dcqmem_ack_o(dcqmem_ack_dc),
772
        .dcqmem_rty_o(dcqmem_rty_dc),
773
        .dcqmem_err_o(dcqmem_err_dc),
774
        .dcqmem_tag_o(dcqmem_tag_dc),
775
 
776
        .dc_no_writethrough(dc_no_writethrough),
777
 
778
        // SPR access
779
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
780
        .spr_addr(spr_addr),
781
        .spr_write(spr_we),
782
        .spr_dat_i(spr_dat_cpu),
783
        .mtspr_dc_done(mtspr_dc_done),
784
 
785
        // DC and BIU
786
        .dcsb_dat_o(dcsb_dat_dc),
787
        .dcsb_adr_o(dcsb_adr_dc),
788
        .dcsb_cyc_o(dcsb_cyc_dc),
789
        .dcsb_stb_o(dcsb_stb_dc),
790
        .dcsb_we_o(dcsb_we_dc),
791
        .dcsb_sel_o(dcsb_sel_dc),
792
        .dcsb_cab_o(dcsb_cab_dc),
793
        .dcsb_dat_i(dcsb_dat_sb),
794
        .dcsb_ack_i(dcsb_ack_sb),
795
        .dcsb_err_i(dcsb_err_sb)
796
);
797
 
798
//
799
// Instantiation of embedded memory - qmem
800
//
801
or1200_qmem_top or1200_qmem_top(
802
        .clk(clk_i),
803
        .rst(rst_i),
804
 
805
`ifdef OR1200_BIST
806
        // RAM BIST
807
        .mbist_si_i(mbist_qmem_si),
808
        .mbist_so_o(mbist_qmem_so),
809
        .mbist_ctrl_i(mbist_ctrl_i),
810
`endif
811
 
812
        // QMEM and CPU/IMMU
813
        .qmemimmu_adr_i(qmemimmu_adr_immu),
814
        .qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
815
        .qmemimmu_ci_i(qmemimmu_ci_immu),
816
        .qmemicpu_sel_i(icpu_sel_cpu),
817
        .qmemicpu_tag_i(icpu_tag_cpu),
818
        .qmemicpu_dat_o(icpu_dat_qmem),
819
        .qmemicpu_ack_o(icpu_ack_qmem),
820
        .qmemimmu_rty_o(qmemimmu_rty_qmem),
821
        .qmemimmu_err_o(qmemimmu_err_qmem),
822
        .qmemimmu_tag_o(qmemimmu_tag_qmem),
823
 
824
        // QMEM and IC
825
        .icqmem_adr_o(icqmem_adr_qmem),
826
        .icqmem_cycstb_o(icqmem_cycstb_qmem),
827
        .icqmem_ci_o(icqmem_ci_qmem),
828
        .icqmem_sel_o(icqmem_sel_qmem),
829
        .icqmem_tag_o(icqmem_tag_qmem),
830
        .icqmem_dat_i(icqmem_dat_ic),
831
        .icqmem_ack_i(icqmem_ack_ic),
832
        .icqmem_rty_i(icqmem_rty_ic),
833
        .icqmem_err_i(icqmem_err_ic),
834
        .icqmem_tag_i(icqmem_tag_ic),
835
 
836
        // QMEM and CPU/DMMU
837
        .qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
838
        .qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
839
        .qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
840
        .qmemdcpu_we_i(dcpu_we_cpu),
841
        .qmemdcpu_sel_i(dcpu_sel_cpu),
842
        .qmemdcpu_tag_i(dcpu_tag_cpu),
843
        .qmemdcpu_dat_i(dcpu_dat_cpu),
844
        .qmemdcpu_dat_o(dcpu_dat_qmem),
845
        .qmemdcpu_ack_o(dcpu_ack_qmem),
846
        .qmemdcpu_rty_o(dcpu_rty_qmem),
847
        .qmemdmmu_err_o(qmemdmmu_err_qmem),
848
        .qmemdmmu_tag_o(qmemdmmu_tag_qmem),
849
 
850
        // QMEM and DC
851
        .dcqmem_adr_o(dcqmem_adr_qmem),
852
        .dcqmem_cycstb_o(dcqmem_cycstb_qmem),
853
        .dcqmem_ci_o(dcqmem_ci_qmem),
854
        .dcqmem_we_o(dcqmem_we_qmem),
855
        .dcqmem_sel_o(dcqmem_sel_qmem),
856
        .dcqmem_tag_o(dcqmem_tag_qmem),
857
        .dcqmem_dat_o(dcqmem_dat_qmem),
858
        .dcqmem_dat_i(dcqmem_dat_dc),
859
        .dcqmem_ack_i(dcqmem_ack_dc),
860
        .dcqmem_rty_i(dcqmem_rty_dc),
861
        .dcqmem_err_i(dcqmem_err_dc),
862
        .dcqmem_tag_i(dcqmem_tag_dc)
863
);
864
 
865
//
866
// Instantiation of Store Buffer
867
//
868
or1200_sb or1200_sb(
869
        // RISC clock, reset
870
        .clk(clk_i),
871
        .rst(rst_i),
872
 
873
        // Internal RISC bus (SB)
874
        .sb_en(sb_en),
875
 
876
        // Internal RISC bus (DC<->SB)
877
        .dcsb_dat_i(dcsb_dat_dc),
878
        .dcsb_adr_i(dcsb_adr_dc),
879
        .dcsb_cyc_i(dcsb_cyc_dc),
880
        .dcsb_stb_i(dcsb_stb_dc),
881
        .dcsb_we_i(dcsb_we_dc),
882
        .dcsb_sel_i(dcsb_sel_dc),
883
        .dcsb_cab_i(dcsb_cab_dc),
884
        .dcsb_dat_o(dcsb_dat_sb),
885
        .dcsb_ack_o(dcsb_ack_sb),
886
        .dcsb_err_o(dcsb_err_sb),
887
 
888
        // SB and BIU
889
        .sbbiu_dat_o(sbbiu_dat_sb),
890
        .sbbiu_adr_o(sbbiu_adr_sb),
891
        .sbbiu_cyc_o(sbbiu_cyc_sb),
892
        .sbbiu_stb_o(sbbiu_stb_sb),
893
        .sbbiu_we_o(sbbiu_we_sb),
894
        .sbbiu_sel_o(sbbiu_sel_sb),
895
        .sbbiu_cab_o(sbbiu_cab_sb),
896
        .sbbiu_dat_i(sbbiu_dat_biu),
897
        .sbbiu_ack_i(sbbiu_ack_biu),
898
        .sbbiu_err_i(sbbiu_err_biu)
899
);
900
 
901
//
902
// Instantiation of Debug Unit
903
//
904
or1200_du or1200_du(
905
        // RISC Internal Interface
906
        .clk(clk_i),
907
        .rst(rst_i),
908
        .dcpu_cycstb_i(dcpu_cycstb_cpu),
909
        .dcpu_we_i(dcpu_we_cpu),
910
        .dcpu_adr_i(dcpu_adr_cpu),
911
        .dcpu_dat_lsu(dcpu_dat_cpu),
912
        .dcpu_dat_dc(dcpu_dat_qmem),
913
        .icpu_cycstb_i(icpu_cycstb_cpu),
914
        .ex_freeze(ex_freeze),
915
        .branch_op(branch_op),
916
        .ex_insn(ex_insn),
917
        .id_pc(id_pc),
918
        .du_dsr(du_dsr),
919
        .du_dmr1(du_dmr1),
920
 
921
        // For Trace buffer
922
        .spr_dat_npc(spr_dat_npc),
923
        .rf_dataw(rf_dataw),
924
 
925
        // DU's access to SPR unit
926
        .du_stall(du_stall),
927
        .du_addr(du_addr),
928
        .du_dat_i(du_dat_cpu),
929
        .du_dat_o(du_dat_du),
930
        .du_read(du_read),
931
        .du_write(du_write),
932
        .du_except_stop(du_except_stop),
933
        .du_hwbkpt(du_hwbkpt),
934
 
935
        // Access to DU's SPRs
936
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
937
        .spr_write(spr_we),
938
        .spr_addr(spr_addr),
939
        .spr_dat_i(spr_dat_cpu),
940
        .spr_dat_o(spr_dat_du),
941
 
942
        // External Debug Interface
943
        .dbg_stall_i(dbg_stall_i),
944
        .dbg_ewt_i(dbg_ewt_i),
945
        .dbg_lss_o(dbg_lss_o),
946
        .dbg_is_o(dbg_is_o),
947
        .dbg_wp_o(dbg_wp_o),
948
        .dbg_bp_o(dbg_bp_o),
949
        .dbg_stb_i(dbg_stb_i),
950
        .dbg_we_i(dbg_we_i),
951
        .dbg_adr_i(dbg_adr_i),
952
        .dbg_dat_i(dbg_dat_i),
953
        .dbg_dat_o(dbg_dat_o),
954
        .dbg_ack_o(dbg_ack_o)
955
);
956
 
957
//
958
// Programmable interrupt controller
959
//
960
or1200_pic or1200_pic(
961
        // RISC Internal Interface
962
        .clk(clk_i),
963
        .rst(rst_i),
964
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
965
        .spr_write(spr_we),
966
        .spr_addr(spr_addr),
967
        .spr_dat_i(spr_dat_cpu),
968
        .spr_dat_o(spr_dat_pic),
969
        .pic_wakeup(pic_wakeup),
970
        .intr(sig_int),
971
 
972
        // PIC Interface
973
        .pic_int(pic_ints_i)
974
);
975
 
976
//
977
// Instantiation of Tick timer
978
//
979
or1200_tt or1200_tt(
980
        // RISC Internal Interface
981
        .clk(clk_i),
982
        .rst(rst_i),
983
        .du_stall(du_stall),
984
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
985
        .spr_write(spr_we),
986
        .spr_addr(spr_addr),
987
        .spr_dat_i(spr_dat_cpu),
988
        .spr_dat_o(spr_dat_tt),
989
        .intr(sig_tick)
990
);
991
 
992
//
993
// Instantiation of Power Management
994
//
995
or1200_pm or1200_pm(
996
        // RISC Internal Interface
997
        .clk(clk_i),
998
        .rst(rst_i),
999
        .pic_wakeup(pic_wakeup),
1000
        .spr_write(spr_we),
1001
        .spr_addr(spr_addr),
1002
        .spr_dat_i(spr_dat_cpu),
1003
        .spr_dat_o(spr_dat_pm),
1004
 
1005
        // Power Management Interface
1006
        .pm_cpustall(pm_cpustall_i),
1007
        .pm_clksd(pm_clksd_o),
1008
        .pm_dc_gate(pm_dc_gate_o),
1009
        .pm_ic_gate(pm_ic_gate_o),
1010
        .pm_dmmu_gate(pm_dmmu_gate_o),
1011
        .pm_immu_gate(pm_immu_gate_o),
1012
        .pm_tt_gate(pm_tt_gate_o),
1013
        .pm_cpu_gate(pm_cpu_gate_o),
1014
        .pm_wakeup(pm_wakeup_o),
1015
        .pm_lvolt(pm_lvolt_o)
1016
);
1017
 
1018
 
1019
endmodule

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