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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_wb_biu.v] - Blame information for rev 477

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's WISHBONE BIU                                       ////
4
////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
8
////  Description                                                 ////
9
////  Implements WISHBONE interface                               ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - if biu_cyc/stb are deasserted and wb_ack_i is asserted   ////
13
////   and this happens even before aborted_r is asssrted,        ////
14
////   wb_ack_i will be delivered even though transfer is         ////
15
////   internally considered already aborted. However most        ////
16
////   wb_ack_i are externally registered and delayed. Normally   ////
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////   this shouldn't cause any problems.                         ////
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////                                                              ////
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////  Author(s):                                                  ////
20
////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
23
////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
28
//// removed from the file and that any derivative work contains  ////
29
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
31
//// This source file is free software; you can redistribute it   ////
32
//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
34
//// either version 2.1 of the License, or (at your option) any   ////
35
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
38
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
39
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
40
//// PURPOSE.  See the GNU Lesser General Public License for more ////
41
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
44
//// Public License along with this source; if not, download it   ////
45
//// from http://www.opencores.org/lgpl.shtml                     ////
46
////                                                              ////
47
//////////////////////////////////////////////////////////////////////
48
//
49
//
50
// $Log: or1200_wb_biu.v,v $
51
// Revision 2.0  2010/06/30 11:00:00  ORSoC
52
// Major update: 
53
// Structure reordered and bugs fixed. 
54
//
55
 
56
// synopsys translate_off
57
`include "timescale.v"
58
// synopsys translate_on
59
`include "or1200_defines.v"
60
 
61
module or1200_wb_biu(
62
                     // RISC clock, reset and clock control
63
                     clk, rst, clmode,
64
 
65
                     // WISHBONE interface
66
                     wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
67
                     wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,
68
`ifdef OR1200_WB_CAB
69
                     wb_cab_o,
70
`endif
71
`ifdef OR1200_WB_B3
72
                     wb_cti_o, wb_bte_o,
73
`endif
74
 
75
                     // Internal RISC bus
76
                     biu_dat_i, biu_adr_i, biu_cyc_i, biu_stb_i, biu_we_i, biu_sel_i, biu_cab_i,
77
                     biu_dat_o, biu_ack_o, biu_err_o
78
                     );
79
 
80
   parameter dw = `OR1200_OPERAND_WIDTH;
81
   parameter aw = `OR1200_OPERAND_WIDTH;
82 477 julius
   parameter bl = 4; /* Can currently be either 4 or 8 - the two optional line
83
                      sizes for the OR1200. */
84
 
85
 
86 350 julius
   //
87
   // RISC clock, reset and clock control
88
   //
89
   input                                clk;            // RISC clock
90
   input                                rst;            // RISC reset
91
   input [1:0]                           clmode;         // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
92
 
93
   //
94
   // WISHBONE interface
95
   //
96
   input                                wb_clk_i;       // clock input
97
   input                                wb_rst_i;       // reset input
98
   input                                wb_ack_i;       // normal termination
99
   input                                wb_err_i;       // termination w/ error
100
   input                                wb_rty_i;       // termination w/ retry
101
   input [dw-1:0]                        wb_dat_i;       // input data bus
102
   output                               wb_cyc_o;       // cycle valid output
103
   output [aw-1:0]                       wb_adr_o;       // address bus outputs
104
   output                               wb_stb_o;       // strobe output
105
   output                               wb_we_o;        // indicates write transfer
106
   output [3:0]                  wb_sel_o;       // byte select outputs
107
   output [dw-1:0]                       wb_dat_o;       // output data bus
108
`ifdef OR1200_WB_CAB
109
   output                               wb_cab_o;       // consecutive address burst
110
`endif
111
`ifdef OR1200_WB_B3
112
   output [2:0]                  wb_cti_o;       // cycle type identifier
113
   output [1:0]                  wb_bte_o;       // burst type extension
114
`endif
115
 
116
   //
117
   // Internal RISC interface
118
   //
119
   input [dw-1:0]                        biu_dat_i;      // input data bus
120
   input [aw-1:0]                        biu_adr_i;      // address bus
121
   input                                biu_cyc_i;      // WB cycle
122
   input                                biu_stb_i;      // WB strobe
123
   input                                biu_we_i;       // WB write enable
124
   input                                biu_cab_i;      // CAB input
125
   input [3:0]                           biu_sel_i;      // byte selects
126
   output [31:0]                         biu_dat_o;      // output data bus
127
   output                               biu_ack_o;      // ack output
128
   output                               biu_err_o;      // err output
129
 
130
   //
131
   // Registers
132
   //
133
   wire                                 wb_ack;         // normal termination
134
   reg [aw-1:0]                  wb_adr_o;       // address bus outputs
135
   reg                                  wb_cyc_o;       // cycle output
136
   reg                                  wb_stb_o;       // strobe output
137
   reg                                  wb_we_o;        // indicates write transfer
138
   reg [3:0]                             wb_sel_o;       // byte select outputs
139
`ifdef OR1200_WB_CAB
140
   reg                                  wb_cab_o;       // CAB output
141
`endif
142
`ifdef OR1200_WB_B3
143
   reg [2:0]                             wb_cti_o;       // cycle type identifier
144
   reg [1:0]                             wb_bte_o;       // burst type extension
145
`endif
146
`ifdef OR1200_NO_DC
147
   reg [dw-1:0]                  wb_dat_o;       // output data bus
148
`else
149
   assign wb_dat_o = biu_dat_i;    // No register on this - straight from DCRAM
150
`endif
151
 
152
`ifdef OR1200_WB_RETRY
153
   reg [`OR1200_WB_RETRY-1:0]            retry_cnt;      // Retry counter
154
`else
155
   wire                                 retry_cnt;
156
   assign retry_cnt = 1'b0;
157
`endif
158
`ifdef OR1200_WB_B3
159 477 julius
   reg [3:0]                             burst_len;      // burst counter
160 350 julius
`endif
161
 
162
   reg                                  biu_stb_reg;    // WB strobe
163
   wire                                 biu_stb;        // WB strobe
164
   reg                                  wb_cyc_nxt;     // next WB cycle value
165
   reg                                  wb_stb_nxt;     // next WB strobe value
166
   reg [2:0]                             wb_cti_nxt;     // next cycle type identifier value
167
 
168
   reg                                  wb_ack_cnt;     // WB ack toggle counter
169
   reg                                  wb_err_cnt;     // WB err toggle counter
170
   reg                                  wb_rty_cnt;     // WB rty toggle counter
171
   reg                                  biu_ack_cnt;    // BIU ack toggle counter
172
   reg                                  biu_err_cnt;    // BIU err toggle counter
173
   reg                                  biu_rty_cnt;    // BIU rty toggle counter
174
   wire                                 biu_rty;        // BIU rty indicator
175
 
176
   reg [1:0]                             wb_fsm_state_cur;       // WB FSM - surrent state
177
   reg [1:0]                             wb_fsm_state_nxt;       // WB FSM - next state
178
   wire [1:0]                            wb_fsm_idle     = 2'h0; // WB FSM state - IDLE
179
   wire [1:0]                            wb_fsm_trans    = 2'h1; // WB FSM state - normal TRANSFER
180
   wire [1:0]                            wb_fsm_last     = 2'h2; // EB FSM state - LAST transfer
181
 
182
   //
183
   // WISHBONE I/F <-> Internal RISC I/F conversion
184
   //
185
   //assign wb_ack = wb_ack_i;
186
   assign wb_ack = wb_ack_i & !wb_err_i & !wb_rty_i;
187
 
188
   //
189
   // WB FSM - register part
190
   // 
191 358 julius
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
192
      if (wb_rst_i == `OR1200_RST_VALUE)
193 350 julius
        wb_fsm_state_cur <=  wb_fsm_idle;
194
      else
195
        wb_fsm_state_cur <=  wb_fsm_state_nxt;
196
   end
197
 
198
   //
199
   // WB burst tength counter
200
   // 
201 358 julius
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
202
      if (wb_rst_i == `OR1200_RST_VALUE) begin
203 477 julius
         burst_len <= 0;
204 350 julius
      end
205
      else begin
206
         // burst counter
207
         if (wb_fsm_state_cur == wb_fsm_idle)
208 477 julius
           burst_len <=  bl[3:0] - 2;
209 350 julius
         else if (wb_stb_o & wb_ack)
210 477 julius
           burst_len <=  burst_len - 1;
211 350 julius
      end
212
   end
213
 
214
   // 
215
   // WB FSM - combinatorial part
216
   // 
217
   always @(wb_fsm_state_cur or burst_len or wb_err_i or wb_rty_i or wb_ack or
218
            wb_cti_o or wb_sel_o or wb_stb_o or wb_we_o or biu_cyc_i or
219
            biu_stb or biu_cab_i or biu_sel_i or biu_we_i) begin
220
      // States of WISHBONE Finite State Machine
221
      case(wb_fsm_state_cur)
222
        // IDLE 
223
        wb_fsm_idle : begin
224
           wb_cyc_nxt = biu_cyc_i & biu_stb;
225
           wb_stb_nxt = biu_cyc_i & biu_stb;
226
           wb_cti_nxt = {!biu_cab_i, 1'b1, !biu_cab_i};
227
           if (biu_cyc_i & biu_stb)
228
             wb_fsm_state_nxt = wb_fsm_trans;
229
           else
230
             wb_fsm_state_nxt = wb_fsm_idle;
231
        end
232
        // normal TRANSFER
233
        wb_fsm_trans : begin
234
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
235
                        !(wb_ack & wb_cti_o == 3'b111);
236
 
237
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
238
                        !wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
239
           wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
240
           wb_cti_nxt[1] = 1'b1  ;
241
           wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
242 477 julius
 
243 350 julius
 
244
           //if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010  | 
245
           //     biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
246
 
247
           if ((!biu_cyc_i | !biu_stb | !biu_cab_i | biu_sel_i != wb_sel_o |
248
                biu_we_i != wb_we_o) & wb_cti_o == 3'b010)
249
             wb_fsm_state_nxt = wb_fsm_last;
250
           else if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o==3'b111) &
251
                    wb_stb_o)
252
             wb_fsm_state_nxt = wb_fsm_idle;
253
           else
254
             wb_fsm_state_nxt = wb_fsm_trans;
255
        end
256
        // LAST transfer
257
        wb_fsm_last : begin
258
           wb_cyc_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
259
                        !(wb_ack & wb_cti_o == 3'b111);
260
           wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i &
261
                        !(wb_ack & wb_cti_o == 3'b111);
262
           wb_cti_nxt[2] = wb_ack & wb_stb_o | wb_cti_o[2];
263
           wb_cti_nxt[1] = 1'b1                  ;
264
           wb_cti_nxt[0] = wb_ack & wb_stb_o | wb_cti_o[0];
265
           if ((wb_err_i | wb_rty_i | wb_ack & wb_cti_o == 3'b111) & wb_stb_o)
266
             wb_fsm_state_nxt = wb_fsm_idle;
267
           else
268
             wb_fsm_state_nxt = wb_fsm_last;
269
        end
270
        // default state
271
        default:begin
272
           wb_cyc_nxt = 1'bx;
273
           wb_stb_nxt = 1'bx;
274
           wb_cti_nxt = 3'bxxx;
275
           wb_fsm_state_nxt = 2'bxx;
276
        end
277
      endcase
278
   end
279
 
280
   //
281
   // WB FSM - output signals
282
   // 
283 358 julius
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
284
      if (wb_rst_i == `OR1200_RST_VALUE) begin
285 350 julius
         wb_cyc_o       <=  1'b0;
286
         wb_stb_o       <=  1'b0;
287
         wb_cti_o       <=  3'b111;
288 477 julius
         wb_bte_o       <=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
289 350 julius
`ifdef OR1200_WB_CAB
290
         wb_cab_o       <=  1'b0;
291
`endif
292
         wb_we_o                <=  1'b0;
293
         wb_sel_o       <=  4'hf;
294
         wb_adr_o       <=  {aw{1'b0}};
295
`ifdef OR1200_NO_DC
296
         wb_dat_o       <=  {dw{1'b0}};
297
`endif
298
      end
299
      else begin
300
         wb_cyc_o       <=  wb_cyc_nxt;
301
         //             wb_stb_o        <=  wb_stb_nxt;
302
         if (wb_ack & wb_cti_o == 3'b111)
303
           wb_stb_o        <=  1'b0;
304
         else
305
           wb_stb_o        <=  wb_stb_nxt;
306
         wb_cti_o       <=  wb_cti_nxt;
307 477 julius
         wb_bte_o       <=  (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
308 350 julius
`ifdef OR1200_WB_CAB
309
         wb_cab_o       <=  biu_cab_i;
310
`endif
311
         // we and sel - set at beginning of access 
312
         if (wb_fsm_state_cur == wb_fsm_idle) begin
313
            wb_we_o             <=  biu_we_i;
314
            wb_sel_o    <=  biu_sel_i;
315
         end
316
         // adr - set at beginning of access and changed at every termination 
317
         if (wb_fsm_state_cur == wb_fsm_idle) begin
318
            wb_adr_o    <=  biu_adr_i;
319
         end
320
         else if (wb_stb_o & wb_ack) begin
321 477 julius
            if (bl==4) begin
322
               wb_adr_o[3:2]    <=  wb_adr_o[3:2] + 1;
323
            end
324
            if (bl==8) begin
325
               wb_adr_o[4:2]    <=  wb_adr_o[4:2] + 1;
326
            end
327 350 julius
         end
328
`ifdef OR1200_NO_DC
329
         // dat - write data changed after avery subsequent write access
330
         if (!wb_stb_o) begin
331
            wb_dat_o    <=  biu_dat_i;
332
         end
333
`endif
334
      end
335
   end
336
 
337
   //
338
   // WB & BIU termination toggle counters
339
   // 
340 358 julius
   always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
341
      if (wb_rst_i == `OR1200_RST_VALUE) begin
342 350 julius
         wb_ack_cnt     <=  1'b0;
343
         wb_err_cnt     <=  1'b0;
344
         wb_rty_cnt     <=  1'b0;
345
      end
346
      else begin
347
         // WB ack toggle counter
348 363 julius
         if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
349 350 julius
           wb_ack_cnt   <=  1'b0;
350
         else if (wb_stb_o & wb_ack)
351
           wb_ack_cnt   <=  !wb_ack_cnt;
352
         // WB err toggle counter
353 363 julius
         if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
354 350 julius
           wb_err_cnt   <=  1'b0;
355
         else if (wb_stb_o & wb_err_i)
356
           wb_err_cnt   <=  !wb_err_cnt;
357
         // WB rty toggle counter
358 363 julius
         if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
359 350 julius
           wb_rty_cnt   <=  1'b0;
360
         else if (wb_stb_o & wb_rty_i)
361
           wb_rty_cnt   <=  !wb_rty_cnt;
362
      end
363
   end
364
 
365 358 julius
   always @(posedge clk or `OR1200_RST_EVENT rst) begin
366
      if (rst == `OR1200_RST_VALUE) begin
367 350 julius
         biu_stb_reg    <=  1'b0;
368
         biu_ack_cnt    <=  1'b0;
369
         biu_err_cnt    <=  1'b0;
370
         biu_rty_cnt    <=  1'b0;
371
`ifdef OR1200_WB_RETRY
372
         retry_cnt      <= {`OR1200_WB_RETRY{1'b0}};
373
`endif
374
      end
375
      else begin
376
         // BIU strobe
377
         if (biu_stb_i & !biu_cab_i & biu_ack_o)
378
           biu_stb_reg  <=  1'b0;
379
         else
380
           biu_stb_reg  <=  biu_stb_i;
381
         // BIU ack toggle counter
382 363 julius
         if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
383 350 julius
           biu_ack_cnt  <=  1'b0 ;
384
         else if (biu_ack_o)
385
           biu_ack_cnt  <=  !biu_ack_cnt ;
386
         // BIU err toggle counter
387 363 julius
         if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
388 350 julius
           biu_err_cnt  <=  1'b0 ;
389
         else if (wb_err_i & biu_err_o)
390
           biu_err_cnt  <=  !biu_err_cnt ;
391
         // BIU rty toggle counter
392 363 julius
         if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
393 350 julius
           biu_rty_cnt  <=  1'b0 ;
394
         else if (biu_rty)
395
           biu_rty_cnt  <=  !biu_rty_cnt ;
396
`ifdef OR1200_WB_RETRY
397
         if (biu_ack_o | biu_err_o)
398
           retry_cnt    <=  {`OR1200_WB_RETRY{1'b0}};
399
         else if (biu_rty)
400
           retry_cnt    <=  retry_cnt + 1'b1;
401
`endif
402
      end
403
   end
404
 
405
   assign biu_stb = biu_stb_i & biu_stb_reg;
406
 
407
   //
408
   // Input BIU data bus
409
   //
410
   assign       biu_dat_o       = wb_dat_i;
411
 
412
   //
413
   // Input BIU termination signals 
414
   //
415
   assign       biu_rty         = (wb_fsm_state_cur == wb_fsm_trans) & wb_rty_i & wb_stb_o & (wb_rty_cnt ~^ biu_rty_cnt);
416
   assign       biu_ack_o       = (wb_fsm_state_cur == wb_fsm_trans) & wb_ack & wb_stb_o & (wb_ack_cnt ~^ biu_ack_cnt);
417
   assign       biu_err_o       = (wb_fsm_state_cur == wb_fsm_trans) & wb_err_i & wb_stb_o & (wb_err_cnt ~^ biu_err_cnt)
418
`ifdef OR1200_WB_RETRY
419
     | biu_rty & retry_cnt[`OR1200_WB_RETRY-1];
420
`else
421
   ;
422
`endif
423
 
424
 
425
endmodule

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