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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [rom/] [rom.v] - Blame information for rev 361

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1 361 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  ROM                                                         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback (unneback@opencores.org)             ////
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////      - Julius Baxter    (julius@opencores.org)               ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//`define B3_BURST
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`define NONBLOCK_ASSIGN <= #1
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module rom
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  ( wb_adr_i, wb_stb_i, wb_cyc_i, wb_cti_i, wb_bte_i,
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    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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   parameter addr_width = 5;
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   input [(addr_width+2)-1:2]       wb_adr_i;
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   input                            wb_stb_i;
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   input                            wb_cyc_i;
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   input [2:0]                       wb_cti_i;
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   input [1:0]                       wb_bte_i;
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   output reg [31:0]                 wb_dat_o;
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   output reg                       wb_ack_o;
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   input                            wb_clk;
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   input                            wb_rst;
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`ifdef B3_BURST
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   reg [addr_width-1:0]      adr;
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   reg                              wb_stb_i_r;
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   wire                             new_access;
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   reg                              new_access_r;
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   wire                             burst;
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   reg                              burst_r;
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   wire                             new_burst;
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`endif
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_dat_o `NONBLOCK_ASSIGN 32'h15000000;
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     else
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`ifdef B3_BURST
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       case (adr)
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`else
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         case (wb_adr_i)
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`endif
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`include "bootrom.v"
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           /*
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            // Zero r0 and jump to 0x00000100
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            1 : wb_dat_o <= 32'hA8200000;
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            2 : wb_dat_o <= 32'hA8C00100;
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            3 : wb_dat_o <= 32'h44003000;
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            4 : wb_dat_o <= 32'h15000000;
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            */
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           default:
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             wb_dat_o `NONBLOCK_ASSIGN 32'h00000000;
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         endcase // case (wb_adr_i)
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`ifdef B3_BURST
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   always @(posedge wb_clk)
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     wb_stb_i_r `NONBLOCK_ASSIGN wb_stb_i;
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   assign new_access = (wb_stb_i & !wb_stb_i_r);
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   always @(posedge wb_clk)
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     new_access_r <= new_access;
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   always @(posedge wb_clk)
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     burst_r `NONBLOCK_ASSIGN burst;
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   assign new_burst = (burst & !burst_r);
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   always @(posedge wb_clk)
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     if (wb_rst)
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       adr `NONBLOCK_ASSIGN 0;
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     else if (new_access)
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       // New access, register address, ack a cycle later
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       adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
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     else if (burst)
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       begin
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          if (wb_cti_i == 3'b010)
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            case (wb_bte_i)
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              2'b00: adr `NONBLOCK_ASSIGN adr + 1;
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              2'b01: adr[1:0] `NONBLOCK_ASSIGN adr[1:0] + 1;
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              2'b10: adr[2:0] `NONBLOCK_ASSIGN adr[2:0] + 1;
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              2'b11: adr[3:0] `NONBLOCK_ASSIGN adr[3:0] + 1;
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            endcase // case (wb_bte_i)
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          else
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            adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
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       end // if (burst)
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   always @(posedge wb_clk)
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     if (wb_rst)
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       wb_ack_o `NONBLOCK_ASSIGN 0;
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     else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
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       wb_ack_o `NONBLOCK_ASSIGN 0;
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     else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
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       wb_ack_o `NONBLOCK_ASSIGN 1;
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     else
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       wb_ack_o `NONBLOCK_ASSIGN 0;
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   assign burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
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`else // !`ifdef B3_BURST
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   always @ (posedge wb_clk or posedge wb_rst)
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     if (wb_rst)
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       wb_ack_o `NONBLOCK_ASSIGN 1'b0;
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     else
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       wb_ack_o `NONBLOCK_ASSIGN wb_stb_i & wb_cyc_i & !wb_ack_o;
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`endif // !`ifdef B3_BURST
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endmodule

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