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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  ROM                                                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback (unneback@opencores.org)             ////
////      - Julius Baxter    (julius@opencores.org)               ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//`define B3_BURST
`define NONBLOCK_ASSIGN <= #1
module rom
  ( wb_adr_i, wb_stb_i, wb_cyc_i, wb_cti_i, wb_bte_i,
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
   parameter addr_width = 5;
 
   input [(addr_width+2)-1:2]       wb_adr_i;
   input                            wb_stb_i;
   input                            wb_cyc_i;
   input [2:0]                       wb_cti_i;
   input [1:0]                       wb_bte_i;
   output reg [31:0]                 wb_dat_o;
   output reg                       wb_ack_o;
   input                            wb_clk;
   input                            wb_rst;
 
`ifdef B3_BURST
   reg [addr_width-1:0]      adr;
   reg                              wb_stb_i_r;
   wire                             new_access;
   reg                              new_access_r;
   wire                             burst;
   reg                              burst_r;
   wire                             new_burst;
 
`endif
 
   always @ (posedge wb_clk or posedge wb_rst)
     if (wb_rst)
       wb_dat_o `NONBLOCK_ASSIGN 32'h15000000;
     else
`ifdef B3_BURST
       case (adr)
`else
         case (wb_adr_i)
`endif
`include "bootrom.v"
           /*
            // Zero r0 and jump to 0x00000100
 
            1 : wb_dat_o <= 32'hA8200000;
            2 : wb_dat_o <= 32'hA8C00100;
            3 : wb_dat_o <= 32'h44003000;
            4 : wb_dat_o <= 32'h15000000;
            */
           default:
             wb_dat_o `NONBLOCK_ASSIGN 32'h00000000;
 
         endcase // case (wb_adr_i)
 
`ifdef B3_BURST
 
   always @(posedge wb_clk)
     wb_stb_i_r `NONBLOCK_ASSIGN wb_stb_i;
 
   assign new_access = (wb_stb_i & !wb_stb_i_r);
 
   always @(posedge wb_clk)
     new_access_r <= new_access;
 
   always @(posedge wb_clk)
     burst_r `NONBLOCK_ASSIGN burst;
 
   assign new_burst = (burst & !burst_r);
 
   always @(posedge wb_clk)
     if (wb_rst)
       adr `NONBLOCK_ASSIGN 0;
     else if (new_access)
       // New access, register address, ack a cycle later
       adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
     else if (burst)
       begin
          if (wb_cti_i == 3'b010)
            case (wb_bte_i)
              2'b00: adr `NONBLOCK_ASSIGN adr + 1;
              2'b01: adr[1:0] `NONBLOCK_ASSIGN adr[1:0] + 1;
              2'b10: adr[2:0] `NONBLOCK_ASSIGN adr[2:0] + 1;
              2'b11: adr[3:0] `NONBLOCK_ASSIGN adr[3:0] + 1;
            endcase // case (wb_bte_i)
          else
            adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
       end // if (burst)
 
 
   always @(posedge wb_clk)
     if (wb_rst)
       wb_ack_o `NONBLOCK_ASSIGN 0;
     else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
       wb_ack_o `NONBLOCK_ASSIGN 0;
     else if (wb_stb_i & ((!burst & !new_access & new_access_r) | (burst & burst_r)))
       wb_ack_o `NONBLOCK_ASSIGN 1;
     else
       wb_ack_o `NONBLOCK_ASSIGN 0;
 
 
   assign burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
 
`else // !`ifdef B3_BURST
 
   always @ (posedge wb_clk or posedge wb_rst)
     if (wb_rst)
       wb_ack_o `NONBLOCK_ASSIGN 1'b0;
     else
       wb_ack_o `NONBLOCK_ASSIGN wb_stb_i & wb_cyc_i & !wb_ack_o;
 
`endif // !`ifdef B3_BURST
 
endmodule

Line No.	Rev	Author	Line
1	361	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// ROM ////`
4			`//// ////`
5			`//// Author(s): ////`
6			`//// - Michael Unneback (unneback@opencores.org) ////`
7			`//// - Julius Baxter (julius@opencores.org) ////`
8			`//// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009 Authors ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35			//`define B3_BURST
36			`define NONBLOCK_ASSIGN <= #1
37			`module rom`
38			`( wb_adr_i, wb_stb_i, wb_cyc_i, wb_cti_i, wb_bte_i,`
39			`wb_dat_o, wb_ack_o, wb_clk, wb_rst);`
40
41			`parameter addr_width = 5;`
42
43			`input [(addr_width+2)-1:2] wb_adr_i;`
44			`input wb_stb_i;`
45			`input wb_cyc_i;`
46			`input [2:0] wb_cti_i;`
47			`input [1:0] wb_bte_i;`
48			`output reg [31:0] wb_dat_o;`
49			`output reg wb_ack_o;`
50			`input wb_clk;`
51			`input wb_rst;`
52
53			`ifdef B3_BURST
54			`reg [addr_width-1:0] adr;`
55			`reg wb_stb_i_r;`
56			`wire new_access;`
57			`reg new_access_r;`
58			`wire burst;`
59			`reg burst_r;`
60			`wire new_burst;`
61
62			`endif
63
64			`always @ (posedge wb_clk or posedge wb_rst)`
65			`if (wb_rst)`
66			wb_dat_o `NONBLOCK_ASSIGN 32'h15000000;
67			`else`
68			`ifdef B3_BURST
69			`case (adr)`
70			`else
71			`case (wb_adr_i)`
72			`endif
73			`include "bootrom.v"
74			`/*`
75			`// Zero r0 and jump to 0x00000100`
76
77			`1 : wb_dat_o <= 32'hA8200000;`
78			`2 : wb_dat_o <= 32'hA8C00100;`
79			`3 : wb_dat_o <= 32'h44003000;`
80			`4 : wb_dat_o <= 32'h15000000;`
81			`*/`
82			`default:`
83			wb_dat_o `NONBLOCK_ASSIGN 32'h00000000;
84
85			`endcase // case (wb_adr_i)`
86
87			`ifdef B3_BURST
88
89			`always @(posedge wb_clk)`
90			wb_stb_i_r `NONBLOCK_ASSIGN wb_stb_i;
91
92			`assign new_access = (wb_stb_i & !wb_stb_i_r);`
93
94			`always @(posedge wb_clk)`
95			`new_access_r <= new_access;`
96
97			`always @(posedge wb_clk)`
98			burst_r `NONBLOCK_ASSIGN burst;
99
100			`assign new_burst = (burst & !burst_r);`
101
102			`always @(posedge wb_clk)`
103			`if (wb_rst)`
104			adr `NONBLOCK_ASSIGN 0;
105			`else if (new_access)`
106			`// New access, register address, ack a cycle later`
107			adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
108			`else if (burst)`
109			`begin`
110			`if (wb_cti_i == 3'b010)`
111			`case (wb_bte_i)`
112			2'b00: adr `NONBLOCK_ASSIGN adr + 1;
113			2'b01: adr[1:0] `NONBLOCK_ASSIGN adr[1:0] + 1;
114			2'b10: adr[2:0] `NONBLOCK_ASSIGN adr[2:0] + 1;
115			2'b11: adr[3:0] `NONBLOCK_ASSIGN adr[3:0] + 1;
116			`endcase // case (wb_bte_i)`
117			`else`
118			adr `NONBLOCK_ASSIGN wb_adr_i[(addr_width+2)-1:2];
119			`end // if (burst)`
120
121
122			`always @(posedge wb_clk)`
123			`if (wb_rst)`
124			wb_ack_o `NONBLOCK_ASSIGN 0;
125			`else if (wb_ack_o & (!burst \| (wb_cti_i == 3'b111)))`
126			wb_ack_o `NONBLOCK_ASSIGN 0;
127			`else if (wb_stb_i & ((!burst & !new_access & new_access_r) \| (burst & burst_r)))`
128			wb_ack_o `NONBLOCK_ASSIGN 1;
129			`else`
130			wb_ack_o `NONBLOCK_ASSIGN 0;
131
132
133			`assign burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));`
134
135			`else // !`ifdef B3_BURST
136
137			`always @ (posedge wb_clk or posedge wb_rst)`
138			`if (wb_rst)`
139			wb_ack_o `NONBLOCK_ASSIGN 1'b0;
140			`else`
141			wb_ack_o `NONBLOCK_ASSIGN wb_stb_i & wb_cyc_i & !wb_ack_o;
142
143			`endif // !`ifdef B3_BURST
144
145			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [rom/] [rom.v] - Blame information for rev 361