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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [simple_spi/] [README] - Blame information for rev 805

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"Simple SPI" SPI controller RTL
 
http://opencores.org/project,simple_spi
 
The core has had a variable-width slave-select register and corresponding I/O
lines added.
 
There is also optional boot-up logic, that sends a series of bus-commands upon
reset, initialising, say a SPI flash chip, to read-state. This could potentially
save space in any bootloader code or FSM wishing to read from an SPI-bus chip
at boot time. Defparam the 'startup_state_reset' to 4'h10 to enable it, and
see the RTL for more details.
 

Line No.	Rev	Author	Line
1	361	julius	`"Simple SPI" SPI controller RTL`
2
3			`http://opencores.org/project,simple_spi`
4
5			`The core has had a variable-width slave-select register and corresponding I/O`
6			`lines added.`
7
8			`There is also optional boot-up logic, that sends a series of bus-commands upon`
9			`reset, initialising, say a SPI flash chip, to read-state. This could potentially`
10			`save space in any bootloader code or FSM wishing to read from an SPI-bus chip`
11			`at boot time. Defparam the 'startup_state_reset' to 4'h10 to enable it, and`
12			`see the RTL for more details.`
13

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [simple_spi/] [README] - Blame information for rev 805