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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [smii/] [smii.v] - Blame information for rev 584

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1 408 julius
/*
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 * SMII <-> MII interface
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 *
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 * Julius Baxter, julius.baxter@orsoc.se
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 *
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 */
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module smii
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  (
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   eth_clk,
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   eth_rst,
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   eth_sync_pad_o,
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   eth_tx_pad_o,
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   eth_rx_pad_i,
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   mtxd,
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   mtxen,
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   mtxerr,
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   mtx_clk,
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   mrxd,
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   mrxdv,
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   mrxerr,
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   mrx_clk,
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   mcoll,
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   mcrs,
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   speed,
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   duplex,
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   link
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   );
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   input eth_clk;
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   input eth_rst; // active high reset synchronous to ethernet clock
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   // SMII
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   output reg eth_sync_pad_o /*synthesis syn_useioff=1 syn_allow_retiming=0 syn_noprune=1*/;
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   output reg eth_tx_pad_o /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
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   input      eth_rx_pad_i;
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   // MII
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   // TX
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   input [3:0] mtxd;
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   input       mtxen;
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   input       mtxerr;
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   output      mtx_clk;
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   // RX
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   output [3:0] mrxd;
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   output       mrxdv;
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   output       mrxerr;
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   output       mrx_clk;
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   output       mcoll;
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   output       mcrs;
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   output       speed;
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   output       duplex;
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   output       link;
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   // Wires from pads
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   wire         smii_tx;
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   reg          smii_rx /*synthesis syn_useioff=1 syn_allow_retiming=0 */;
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   // Sync generation
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   wire [10:1]  tx_smii_state;
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   wire [10:1]  next_tx_smii_state;
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   wire [10:1]  rx_smii_state;
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   wire         smii_sync;
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   smii_sync smii_sync0
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     (
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      .sync(smii_sync),
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      .tx_state(tx_smii_state),
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      .next_tx_state(next_tx_smii_state),
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      .rx_state(rx_smii_state),
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      .clk(eth_clk),
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      .rst(eth_rst)
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      );
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   // IOB regs for SMII
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   always @(posedge eth_clk) eth_sync_pad_o <= smii_sync;
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   always @(posedge eth_clk) eth_tx_pad_o <= smii_tx;
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   always @(posedge eth_clk) smii_rx <= eth_rx_pad_i;
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   smii_if smii_if0
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     (
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      // SMII signals
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      .tx                               (smii_tx),
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      .rx                               (smii_rx),
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      .tx_smii_state                    (tx_smii_state[10:1]),
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      .next_tx_smii_state               (next_tx_smii_state[10:1]),
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      .rx_smii_state                    (rx_smii_state[10:1]),
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      // MAC MII receive
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      .mrxd                             (mrxd[3:0]),
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      .mrxdv                            (mrxdv),
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      .mrxerr                           (mrxerr),
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      .mrx_clk                          (mrx_clk),
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      // MAC MII transmit
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      .mtx_clk                          (mtx_clk),
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      .mtxd                             (mtxd[3:0]),
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      .mtxen                            (mtxen),
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      .mtxerr                           (mtxerr),
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      // Collision
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      .mcoll                            (mcoll),
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      // Carrier sense
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      .mcrs                             (mcrs),
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      // Speedy ethernet
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      .speed                            (speed),
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      // Duplex indicator
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      .duplex                           (duplex),
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      // Linke indicator
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      .link                             (link),
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      // Clocks, resets
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      .eth_clk                          (eth_clk),
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      .eth_rst                          (eth_rst)
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      );
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endmodule // smii

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