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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [smii/] [smii_sync.v] - Blame information for rev 862

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1 408 julius
/*
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 * SMII sync generation module
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 *
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 * Generate sync to PHY, and for internal statemachines
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 *
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 * Julius Baxter, julius.baxter@orsoc.se
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 *
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 */
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module smii_sync
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  (
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   // SMII sync
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    output            sync,
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   // internal
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    output [10:1]     tx_state,
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    output [10:1]     next_tx_state,
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    output [10:1]     rx_state,
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   // clock amd reset
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    input             clk,
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    input             rst
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   );
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   reg [10:1] next_tx_state_r;
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   reg [10:1] tx_state_r;
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   reg [10:1]         rx_state_int;
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   reg [10:1]         rx_state_int2;
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   reg [10:1]         rx_state_int3;
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   // sync shall go high every 10:th cycle
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   always @ (posedge clk)
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     if (rst)
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       begin
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          next_tx_state_r <= 10'b0000000010;
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          tx_state_r <= 0;
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       end
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     else
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       begin
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          tx_state_r <= next_tx_state_r;
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          next_tx_state_r <= {next_tx_state_r[9:1],next_tx_state_r[10]};
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       end
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   assign tx_state = tx_state_r;
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   assign next_tx_state = next_tx_state_r;
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   assign sync = tx_state_r[1];
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   always @(posedge clk)
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     begin
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        rx_state_int <= {tx_state_r[9:1],tx_state_r[10]};
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        rx_state_int2 <= rx_state_int;
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        rx_state_int3 <= rx_state_int2;
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     end
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   // rx_state counter is 2 clocks behind tx state due to flops in and out of
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   // FPGA
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   assign rx_state = rx_state_int3;
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endmodule // smii_sync

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