URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [README] - Blame information for rev 361


UART 16550 compatible (mostly) core RTL
 
http://opencores.org/project,uart16550
 
The core is configured to be in 8-bit mode in this project.

Line No.	Rev	Author	Line
1	361	julius	`UART 16550 compatible (mostly) core RTL`
2
3			`http://opencores.org/project,uart16550`
4
5			`The core is configured to be in 8-bit mode in this project.`