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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart16550.v] - Blame information for rev 584

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1 6 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  uart_top.v                                                  ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the "UART 16550 compatible" project    ////
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////  http://www.opencores.org/cores/uart16550/                   ////
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////                                                              ////
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////  Documentation related to this project:                      ////
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////  - http://www.opencores.org/cores/uart16550/                 ////
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////                                                              ////
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////  Projects compatibility:                                     ////
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////  - WISHBONE                                                  ////
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////  RS232 Protocol                                              ////
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////  16550D uart (mostly supported)                              ////
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////                                                              ////
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////  Overview (main Features):                                   ////
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////  UART core top level.                                        ////
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////                                                              ////
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////  Known problems (limits):                                    ////
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////  Note that transmitter and receiver instances are inside     ////
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////  the uart_regs.v file.                                       ////
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////                                                              ////
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////  To Do:                                                      ////
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////  Nothing so far.                                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - gorban@opencores.org                                  ////
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////      - Jacob Gorban                                          ////
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////      - Igor Mohor (igorm@opencores.org)                      ////
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////                                                              ////
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////  Created:        2001/05/12                                  ////
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////  Last Updated:   2001/05/17                                  ////
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////                  (See log for the revision history)          ////
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////                                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2001 Authors                             ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
66 360 julius
// $Log: not supported by cvs2svn $
67 6 julius
// Revision 1.18  2002/07/22 23:02:23  gorban
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// Bug Fixes:
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//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
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//   Problem reported by Kenny.Tung.
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//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
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//
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// Improvements:
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//  * Made FIFO's as general inferrable memory where possible.
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//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
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//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
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//
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//  * Added optional baudrate output (baud_o).
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//  This is identical to BAUDOUT* signal on 16550 chip.
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//  It outputs 16xbit_clock_rate - the divided clock.
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//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
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//
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// Revision 1.17  2001/12/19 08:40:03  mohor
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// Warnings fixed (unused signals removed).
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//
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// Revision 1.16  2001/12/06 14:51:04  gorban
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// Bug in LSR[0] is fixed.
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// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
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//
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// Revision 1.15  2001/12/03 21:44:29  gorban
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// Updated specification documentation.
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// Added full 32-bit data bus interface, now as default.
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// Address is 5-bit wide in 32-bit data bus mode.
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// Added wb_sel_i input to the core. It's used in the 32-bit mode.
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// Added debug interface with two 32-bit read-only registers in 32-bit mode.
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// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
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// My small test bench is modified to work with 32-bit mode.
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//
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// Revision 1.14  2001/11/07 17:51:52  gorban
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// Heavily rewritten interrupt and LSR subsystems.
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// Many bugs hopefully squashed.
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//
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// Revision 1.13  2001/10/20 09:58:40  gorban
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// Small synopsis fixes
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//
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// Revision 1.12  2001/08/25 15:46:19  gorban
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// Modified port names again
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//
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// Revision 1.11  2001/08/24 21:01:12  mohor
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// Things connected to parity changed.
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// Clock devider changed.
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//
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// Revision 1.10  2001/08/23 16:05:05  mohor
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// Stop bit bug fixed.
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// Parity bug fixed.
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// WISHBONE read cycle bug fixed,
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// OE indicator (Overrun Error) bug fixed.
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// PE indicator (Parity Error) bug fixed.
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// Register read bug fixed.
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//
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// Revision 1.4  2001/05/31 20:08:01  gorban
122
// FIFO changes and other corrections.
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//
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// Revision 1.3  2001/05/21 19:12:02  gorban
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// Corrected some Linter messages.
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//
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// Revision 1.2  2001/05/17 18:34:18  gorban
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// First 'stable' release. Should be sythesizable now. Also added new header.
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//
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// Revision 1.0  2001-05-17 21:27:12+02  jacob
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// Initial revision
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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138
`include "uart_defines.v"
139
 
140 360 julius
//module uart_top       (
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module uart16550( // renamed by Julius
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                  wb_clk_i,
143 44 julius
 
144 360 julius
                  // Wishbone signals
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                  wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_dat_o,
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`ifndef DATA_BUS_WIDTH_8
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                  wb_sel_i,
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`endif
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                  wb_stb_i, wb_cyc_i, wb_ack_o,
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                  int_o, // interrupt request
151 6 julius
 
152 360 julius
                  // UART       signals
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                  // serial input/output
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                  stx_pad_o, srx_pad_i,
155 6 julius
 
156 360 julius
                  // modem signals
157
                  rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i,
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                  dcd_pad_i
159 6 julius
`ifdef UART_HAS_BAUDRATE_OUTPUT
160 360 julius
                  , baud_o
161 6 julius
`endif
162 360 julius
                  );
163 6 julius
 
164 360 julius
   parameter uart_data_width = `UART_DATA_WIDTH;
165
   parameter uart_addr_width = `UART_ADDR_WIDTH;
166 6 julius
 
167 360 julius
   input  wb_clk_i;
168 6 julius
 
169 44 julius
   // WISHBONE interface
170 360 julius
   input  wb_rst_i;
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   input [uart_addr_width-1:0] wb_adr_i;
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   input [uart_data_width-1:0] wb_dat_i;
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   output [uart_data_width-1:0] wb_dat_o;
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   input                        wb_we_i;
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   input                        wb_stb_i;
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   input                        wb_cyc_i;
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`ifndef DATA_BUS_WIDTH_8
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   input [3:0]                   wb_sel_i;
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`endif
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   output                       wb_ack_o;
181
   output                       int_o;
182 6 julius
 
183 44 julius
   // UART      signals
184 360 julius
   input                        srx_pad_i;
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   output                       stx_pad_o;
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   output                       rts_pad_o;
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   input                        cts_pad_i;
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   output                       dtr_pad_o;
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   input                        dsr_pad_i;
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   input                        ri_pad_i;
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   input                        dcd_pad_i;
192 6 julius
 
193 44 julius
   // optional baudrate output
194 6 julius
`ifdef UART_HAS_BAUDRATE_OUTPUT
195 360 julius
   output                       baud_o;
196 6 julius
`endif
197
 
198
 
199 360 julius
   wire                         stx_pad_o;
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   wire                         rts_pad_o;
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   wire                         dtr_pad_o;
202 6 julius
 
203 360 julius
   wire [uart_addr_width-1:0]    wb_adr_i;
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   wire [uart_data_width-1:0]    wb_dat_i;
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   wire [uart_data_width-1:0]    wb_dat_o;
206 6 julius
 
207 360 julius
   wire [7:0]                    wb_dat8_i; // 8-bit internal data input
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   wire [7:0]                    wb_dat8_o; // 8-bit internal data output
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   wire [31:0]                   wb_dat32_o; // debug interface 32-bit output
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   wire [3:0]                    wb_sel_i;  // WISHBONE select signal
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   wire [uart_addr_width-1:0]    wb_adr_int;
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   wire                         we_o;   // Write enable for registers
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   wire                         re_o;   // Read enable for registers
214 44 julius
   //
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   // MODULE INSTANCES
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   //
217 6 julius
 
218
`ifdef DATA_BUS_WIDTH_8
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`else
220 44 julius
   // debug interface wires
221 360 julius
   wire [3:0]                    ier;
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   wire [3:0]                    iir;
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   wire [1:0]                    fcr;
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   wire [4:0]                    mcr;
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   wire [7:0]                    lcr;
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   wire [7:0]                    msr;
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   wire [7:0]                    lsr;
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   wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
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   wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
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   wire [2:0]                       tstate;
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   wire [3:0]                       rstate;
232 6 julius
`endif
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234
`ifdef DATA_BUS_WIDTH_8
235 44 julius
   ////  WISHBONE interface module
236 360 julius
   uart_wb wb_interface
237
     (
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      .clk(             wb_clk_i                ),
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      .wb_rst_i(        wb_rst_i        ),
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      .wb_dat_i(wb_dat_i),
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      .wb_dat_o(wb_dat_o),
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      .wb_dat8_i(wb_dat8_i),
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      .wb_dat8_o(wb_dat8_o),
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      .wb_dat32_o(32'b0),
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      .wb_sel_i(4'b0),
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      .wb_we_i( wb_we_i         ),
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      .wb_stb_i(        wb_stb_i        ),
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      .wb_cyc_i(        wb_cyc_i        ),
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      .wb_ack_o(        wb_ack_o        ),
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      .wb_adr_i(wb_adr_i),
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      .wb_adr_int(wb_adr_int),
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      .we_o(            we_o            ),
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      .re_o(re_o)
254
      );
255 6 julius
`else
256 360 julius
   uart_wb wb_interface
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     (
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      .clk(             wb_clk_i                ),
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      .wb_rst_i(        wb_rst_i        ),
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      .wb_dat_i(wb_dat_i),
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      .wb_dat_o(wb_dat_o),
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      .wb_dat8_i(wb_dat8_i),
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      .wb_dat8_o(wb_dat8_o),
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      .wb_sel_i(wb_sel_i),
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      .wb_dat32_o(wb_dat32_o),
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      .wb_we_i( wb_we_i         ),
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      .wb_stb_i(        wb_stb_i        ),
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      .wb_cyc_i(        wb_cyc_i        ),
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      .wb_ack_o(        wb_ack_o        ),
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      .wb_adr_i(wb_adr_i),
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      .wb_adr_int(wb_adr_int),
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      .we_o(            we_o            ),
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      .re_o(re_o)
274
      );
275 6 julius
`endif
276
 
277 44 julius
   // Registers
278 360 julius
   uart_regs regs
279
     (
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      .clk(             wb_clk_i                ),
281
      .wb_rst_i(        wb_rst_i        ),
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      .wb_addr_i(       wb_adr_int      ),
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      .wb_dat_i(        wb_dat8_i       ),
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      .wb_dat_o(        wb_dat8_o       ),
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      .wb_we_i( we_o            ),
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      .wb_re_i(re_o),
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      .modem_inputs(    {cts_pad_i, dsr_pad_i,
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                         ri_pad_i,  dcd_pad_i}  ),
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      .stx_pad_o(               stx_pad_o               ),
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      .srx_pad_i(               srx_pad_i               ),
291 6 julius
`ifdef DATA_BUS_WIDTH_8
292
`else
293 360 julius
      // debug interface signals        enabled
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      .ier(ier),
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      .iir(iir),
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      .fcr(fcr),
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      .mcr(mcr),
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      .lcr(lcr),
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      .msr(msr),
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      .lsr(lsr),
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      .rf_count(rf_count),
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      .tf_count(tf_count),
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      .tstate(tstate),
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      .rstate(rstate),
305 6 julius
`endif
306 360 julius
      .rts_pad_o(               rts_pad_o               ),
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      .dtr_pad_o(               dtr_pad_o               ),
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      .int_o(           int_o           )
309 6 julius
`ifdef UART_HAS_BAUDRATE_OUTPUT
310 360 julius
      , .baud_o(baud_o)
311 6 julius
`endif
312
 
313 360 julius
      );
314 6 julius
 
315
`ifdef DATA_BUS_WIDTH_8
316
`else
317 360 julius
   uart_debug_if dbg
318
     (
319
      // Outputs
320
      .wb_dat32_o                                (wb_dat32_o[31:0]),
321
      // Inputs
322
      .wb_adr_i                          (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
323
      .ier                                               (ier[3:0]),
324
      .iir                                               (iir[3:0]),
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      .fcr                                               (fcr[1:0]),
326
      .mcr                                               (mcr[4:0]),
327
      .lcr                                               (lcr[7:0]),
328
      .msr                                               (msr[7:0]),
329
      .lsr                                               (lsr[7:0]),
330
      .rf_count                          (rf_count[`UART_FIFO_COUNTER_W-1:0]),
331
      .tf_count                          (tf_count[`UART_FIFO_COUNTER_W-1:0]),
332
      .tstate                                    (tstate[2:0]),
333
      .rstate                                    (rstate[3:0]));
334 6 julius
`endif
335
 
336 360 julius
/*
337 44 julius
   initial
338
     begin
339 360 julius
`ifdef DATA_BUS_WIDTH_8
340 44 julius
        $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
341 360 julius
`else
342 44 julius
        $display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");
343 360 julius
`endif
344
`ifdef UART_HAS_BAUDRATE_OUTPUT
345 44 julius
        $display("(%m) UART INFO: Has baudrate output\n");
346 360 julius
`else
347 44 julius
        $display("(%m) UART INFO: Doesn't have baudrate output\n");
348 6 julius
`endif
349 44 julius
     end
350 360 julius
*/
351
endmodule
352 6 julius
 
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