URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart_transmitter.v] - Blame information for rev 363

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.18  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16  2002/01/08 11:29:40  mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "uart_defines.v"
 
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
 
input                                                                           clk;
input                                                                           wb_rst_i;
input [7:0]                                                              lcr;
input                                                                           tf_push;
input [7:0]                                                              wb_dat_i;
input                                                                           enable;
input                                                                           tx_reset;
input                                                                           lsr_mask; //reset of fifo
output                                                                          stx_pad_o;
output [2:0]                                                             tstate;
output [`UART_FIFO_COUNTER_W-1:0]        tf_count;
 
reg [2:0]                                                                        tstate;
reg [4:0]                                                                        counter;
reg [2:0]                                                                        bit_counter;   // counts the bits to be sent
reg [6:0]                                                                        shift_out;      // output shift register
reg                                                                                     stx_o_tmp;
reg                                                                                     parity_xor;  // parity of the word
reg                                                                                     tf_pop;
reg                                                                                     bit_out;
 
// TX FIFO instance
//
// Transmitter FIFO signals
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_in;
wire [`UART_FIFO_WIDTH-1:0]                      tf_data_out;
wire                                                                                    tf_push;
wire                                                                                    tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0]          tf_count;
 
assign                                                                          tf_data_in = wb_dat_i;
 
uart_tfifo fifo_tx(     // error bit signal is not used in transmitter FIFO
        .clk(           clk             ),
        .wb_rst_i(      wb_rst_i        ),
        .data_in(       tf_data_in      ),
        .data_out(      tf_data_out     ),
        .push(          tf_push         ),
        .pop(           tf_pop          ),
        .overrun(       tf_overrun      ),
        .count(         tf_count        ),
        .fifo_reset(    tx_reset        ),
        .reset_status(lsr_mask)
);
 
// TRANSMITTER FINAL STATE MACHINE
 
parameter s_idle        = 3'd0;
parameter s_send_start  = 3'd1;
parameter s_send_byte   = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop   = 3'd4;
parameter s_pop_byte    = 3'd5;
 
always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
        tstate       <=  s_idle;
        stx_o_tmp       <=  1'b1;
        counter   <=  5'b0;
        shift_out   <=  7'b0;
        bit_out     <=  1'b0;
        parity_xor  <=  1'b0;
        tf_pop      <=  1'b0;
        bit_counter <=  3'b0;
  end
  else
  if (enable)
  begin
        case (tstate)
        s_idle   :      if (~|tf_count) // if tf_count==0
                        begin
                                tstate <=  s_idle;
                                stx_o_tmp <=  1'b1;
                        end
                        else
                        begin
                                tf_pop <=  1'b0;
                                stx_o_tmp  <=  1'b1;
                                tstate  <=  s_pop_byte;
                        end
        s_pop_byte :    begin
                                tf_pop <=  1'b1;
                                case (lcr[/*`UART_LC_BITS*/1:0])  // number of bits in a word
                                2'b00 : begin
                                        bit_counter <=  3'b100;
                                        parity_xor  <=  ^tf_data_out[4:0];
                                     end
                                2'b01 : begin
                                        bit_counter <=  3'b101;
                                        parity_xor  <=  ^tf_data_out[5:0];
                                     end
                                2'b10 : begin
                                        bit_counter <=  3'b110;
                                        parity_xor  <=  ^tf_data_out[6:0];
                                     end
                                2'b11 : begin
                                        bit_counter <=  3'b111;
                                        parity_xor  <=  ^tf_data_out[7:0];
                                     end
                                endcase
                                {shift_out[6:0], bit_out} <=  tf_data_out;
                                tstate <=  s_send_start;
                        end
        s_send_start :  begin
                                tf_pop <=  1'b0;
                                if (~|counter)
                                        counter <=  5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <=  0;
                                        tstate <=  s_send_byte;
                                end
                                else
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  1'b0;
                        end
        s_send_byte :   begin
                                if (~|counter)
                                        counter <=  5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        if (bit_counter > 3'b0)
                                        begin
                                                bit_counter <=  bit_counter - 3'd1;
                                                {shift_out[5:0],bit_out  } <=  {shift_out[6:1], shift_out[0]};
                                                tstate <=  s_send_byte;
                                        end
                                        else   // end of byte
                                        if (~lcr[`UART_LC_PE])
                                        begin
                                                tstate <=  s_send_stop;
                                        end
                                        else
                                        begin
                                                case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
                                                2'b00:  bit_out <=  ~parity_xor;
                                                2'b01:  bit_out <=  1'b1;
                                                2'b10:  bit_out <=  parity_xor;
                                                2'b11:  bit_out <=  1'b0;
                                                endcase
                                                tstate <=  s_send_parity;
                                        end
                                        counter <=  0;
                                end
                                else
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  bit_out; // set output pin
                        end
        s_send_parity : begin
                                if (~|counter)
                                        counter <=  5'b01111;
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <=  5'd0;
                                        tstate <=  s_send_stop;
                                end
                                else
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  bit_out;
                        end
        s_send_stop :  begin
                                if (~|counter)
                                  begin
                                                casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
                                                3'b0??:   counter <=  5'b01101;     // 1 stop bit ok igor
                                                3'b100:   counter <=  5'b10101;     // 1.5 stop bit
                                                default:          counter <=  5'b11101;     // 2 stop bits
                                                endcase
                                        end
                                else
                                if (counter == 5'b00001)
                                begin
                                        counter <=  0;
                                        tstate <=  s_idle;
                                end
                                else
                                        counter <=  counter - 5'd1;
                                stx_o_tmp <=  1'b1;
                        end
 
                default : // should never get here
                        tstate <=  s_idle;
        endcase
  end // end if enable
  else
    tf_pop <=  1'b0;  // tf_pop must be 1 cycle width
end // transmitter logic
 
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;    // Break condition
 
endmodule

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_transmitter.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// UART core transmitter logic ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None known ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Thourough testing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29			`//// - Igor Mohor (igorm@opencores.org) ////`
30			`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000, 2001 Authors ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65	360	julius	`// $Log: not supported by cvs2svn $`
66	6	julius	`// Revision 1.18 2002/07/22 23:02:23 gorban`
67			`// Bug Fixes:`
68			`// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.`
69			`// Problem reported by Kenny.Tung.`
70			`// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.`
71			`//`
72			`// Improvements:`
73			`// * Made FIFO's as general inferrable memory where possible.`
74			`// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).`
75			`// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.`
76			`//`
77			`// * Added optional baudrate output (baud_o).`
78			`// This is identical to BAUDOUT* signal on 16550 chip.`
79			`// It outputs 16xbit_clock_rate - the divided clock.`
80			`// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.`
81			`//`
82			`// Revision 1.16 2002/01/08 11:29:40 mohor`
83			`// tf_pop was too wide. Now it is only 1 clk cycle width.`
84			`//`
85			`// Revision 1.15 2001/12/17 14:46:48 mohor`
86			`// overrun signal was moved to separate block because many sequential lsr`
87			`// reads were preventing data from being written to rx fifo.`
88			`// underrun signal was not used and was removed from the project.`
89			`//`
90			`// Revision 1.14 2001/12/03 21:44:29 gorban`
91			`// Updated specification documentation.`
92			`// Added full 32-bit data bus interface, now as default.`
93			`// Address is 5-bit wide in 32-bit data bus mode.`
94			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
95			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
96			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
97			`// My small test bench is modified to work with 32-bit mode.`
98			`//`
99			`// Revision 1.13 2001/11/08 14:54:23 mohor`
100			`// Comments in Slovene language deleted, few small fixes for better work of`
101			`// old tools. IRQs need to be fix.`
102			`//`
103			`// Revision 1.12 2001/11/07 17:51:52 gorban`
104			`// Heavily rewritten interrupt and LSR subsystems.`
105			`// Many bugs hopefully squashed.`
106			`//`
107			`// Revision 1.11 2001/10/29 17:00:46 gorban`
108			`// fixed parity sending and tx_fifo resets over- and underrun`
109			`//`
110			`// Revision 1.10 2001/10/20 09:58:40 gorban`
111			`// Small synopsis fixes`
112			`//`
113			`// Revision 1.9 2001/08/24 21:01:12 mohor`
114			`// Things connected to parity changed.`
115			`// Clock devider changed.`
116			`//`
117			`// Revision 1.8 2001/08/23 16:05:05 mohor`
118			`// Stop bit bug fixed.`
119			`// Parity bug fixed.`
120			`// WISHBONE read cycle bug fixed,`
121			`// OE indicator (Overrun Error) bug fixed.`
122			`// PE indicator (Parity Error) bug fixed.`
123			`// Register read bug fixed.`
124			`//`
125			`// Revision 1.6 2001/06/23 11:21:48 gorban`
126			`// DL made 16-bit long. Fixed transmission/reception bugs.`
127			`//`
128			`// Revision 1.5 2001/06/02 14:28:14 gorban`
129			`// Fixed receiver and transmitter. Major bug fixed.`
130			`//`
131			`// Revision 1.4 2001/05/31 20:08:01 gorban`
132			`// FIFO changes and other corrections.`
133			`//`
134			`// Revision 1.3 2001/05/27 17:37:49 gorban`
135			`// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.`
136			`//`
137			`// Revision 1.2 2001/05/21 19:12:02 gorban`
138			`// Corrected some Linter messages.`
139			`//`
140			`// Revision 1.1 2001/05/17 18:34:18 gorban`
141			`// First 'stable' release. Should be sythesizable now. Also added new header.`
142			`//`
143			`// Revision 1.0 2001-05-17 21:27:12+02 jacob`
144			`// Initial revision`
145			`//`
146			`//`
147
148			`// synopsys translate_off`
149			`include "timescale.v"
150			`// synopsys translate_on`
151
152			`include "uart_defines.v"
153
154			`module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);`
155
156			`input clk;`
157			`input wb_rst_i;`
158			`input [7:0] lcr;`
159			`input tf_push;`
160			`input [7:0] wb_dat_i;`
161			`input enable;`
162			`input tx_reset;`
163			`input lsr_mask; //reset of fifo`
164			`output stx_pad_o;`
165			`output [2:0] tstate;`
166			output [`UART_FIFO_COUNTER_W-1:0] tf_count;
167
168			`reg [2:0] tstate;`
169			`reg [4:0] counter;`
170			`reg [2:0] bit_counter; // counts the bits to be sent`
171			`reg [6:0] shift_out; // output shift register`
172			`reg stx_o_tmp;`
173			`reg parity_xor; // parity of the word`
174			`reg tf_pop;`
175			`reg bit_out;`
176
177			`// TX FIFO instance`
178			`//`
179			`// Transmitter FIFO signals`
180			wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
181			wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
182			`wire tf_push;`
183			`wire tf_overrun;`
184			wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
185
186			`assign tf_data_in = wb_dat_i;`
187
188			`uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO`
189			`.clk( clk ),`
190			`.wb_rst_i( wb_rst_i ),`
191			`.data_in( tf_data_in ),`
192			`.data_out( tf_data_out ),`
193			`.push( tf_push ),`
194			`.pop( tf_pop ),`
195			`.overrun( tf_overrun ),`
196			`.count( tf_count ),`
197			`.fifo_reset( tx_reset ),`
198			`.reset_status(lsr_mask)`
199			`);`
200
201	360	julius	`// TRANSMITTER FINAL STATE MACHINE`
202	6	julius
203			`parameter s_idle = 3'd0;`
204			`parameter s_send_start = 3'd1;`
205			`parameter s_send_byte = 3'd2;`
206			`parameter s_send_parity = 3'd3;`
207			`parameter s_send_stop = 3'd4;`
208			`parameter s_pop_byte = 3'd5;`
209
210			`always @(posedge clk or posedge wb_rst_i)`
211			`begin`
212			`if (wb_rst_i)`
213			`begin`
214	360	julius	`tstate <= s_idle;`
215			`stx_o_tmp <= 1'b1;`
216			`counter <= 5'b0;`
217			`shift_out <= 7'b0;`
218			`bit_out <= 1'b0;`
219			`parity_xor <= 1'b0;`
220			`tf_pop <= 1'b0;`
221			`bit_counter <= 3'b0;`
222	6	julius	`end`
223			`else`
224			`if (enable)`
225			`begin`
226			`case (tstate)`
227			`s_idle : if (~\|tf_count) // if tf_count==0`
228			`begin`
229	360	julius	`tstate <= s_idle;`
230			`stx_o_tmp <= 1'b1;`
231	6	julius	`end`
232			`else`
233			`begin`
234	360	julius	`tf_pop <= 1'b0;`
235			`stx_o_tmp <= 1'b1;`
236			`tstate <= s_pop_byte;`
237	6	julius	`end`
238			`s_pop_byte : begin`
239	360	julius	`tf_pop <= 1'b1;`
240	6	julius	case (lcr[/`UART_LC_BITS/1:0]) // number of bits in a word
241			`2'b00 : begin`
242	360	julius	`bit_counter <= 3'b100;`
243			`parity_xor <= ^tf_data_out[4:0];`
244	6	julius	`end`
245			`2'b01 : begin`
246	360	julius	`bit_counter <= 3'b101;`
247			`parity_xor <= ^tf_data_out[5:0];`
248	6	julius	`end`
249			`2'b10 : begin`
250	360	julius	`bit_counter <= 3'b110;`
251			`parity_xor <= ^tf_data_out[6:0];`
252	6	julius	`end`
253			`2'b11 : begin`
254	360	julius	`bit_counter <= 3'b111;`
255			`parity_xor <= ^tf_data_out[7:0];`
256	6	julius	`end`
257			`endcase`
258	360	julius	`{shift_out[6:0], bit_out} <= tf_data_out;`
259			`tstate <= s_send_start;`
260	6	julius	`end`
261			`s_send_start : begin`
262	360	julius	`tf_pop <= 1'b0;`
263	6	julius	`if (~\|counter)`
264	360	julius	`counter <= 5'b01111;`
265	6	julius	`else`
266			`if (counter == 5'b00001)`
267			`begin`
268	360	julius	`counter <= 0;`
269			`tstate <= s_send_byte;`
270	6	julius	`end`
271			`else`
272	363	julius	`counter <= counter - 5'd1;`
273	360	julius	`stx_o_tmp <= 1'b0;`
274	6	julius	`end`
275			`s_send_byte : begin`
276			`if (~\|counter)`
277	360	julius	`counter <= 5'b01111;`
278	6	julius	`else`
279			`if (counter == 5'b00001)`
280			`begin`
281			`if (bit_counter > 3'b0)`
282			`begin`
283	363	julius	`bit_counter <= bit_counter - 3'd1;`
284	360	julius	`{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};`
285			`tstate <= s_send_byte;`
286	6	julius	`end`
287			`else // end of byte`
288			if (~lcr[`UART_LC_PE])
289			`begin`
290	360	julius	`tstate <= s_send_stop;`
291	6	julius	`end`
292			`else`
293			`begin`
294			case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
295	360	julius	`2'b00: bit_out <= ~parity_xor;`
296			`2'b01: bit_out <= 1'b1;`
297			`2'b10: bit_out <= parity_xor;`
298			`2'b11: bit_out <= 1'b0;`
299	6	julius	`endcase`
300	360	julius	`tstate <= s_send_parity;`
301	6	julius	`end`
302	360	julius	`counter <= 0;`
303	6	julius	`end`
304			`else`
305	363	julius	`counter <= counter - 5'd1;`
306	360	julius	`stx_o_tmp <= bit_out; // set output pin`
307	6	julius	`end`
308			`s_send_parity : begin`
309			`if (~\|counter)`
310	360	julius	`counter <= 5'b01111;`
311	6	julius	`else`
312			`if (counter == 5'b00001)`
313			`begin`
314	363	julius	`counter <= 5'd0;`
315	360	julius	`tstate <= s_send_stop;`
316	6	julius	`end`
317			`else`
318	363	julius	`counter <= counter - 5'd1;`
319	360	julius	`stx_o_tmp <= bit_out;`
320	6	julius	`end`
321			`s_send_stop : begin`
322			`if (~\|counter)`
323			`begin`
324	363	julius	casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
325			`3'b0??: counter <= 5'b01101; // 1 stop bit ok igor`
326	360	julius	`3'b100: counter <= 5'b10101; // 1.5 stop bit`
327			`default: counter <= 5'b11101; // 2 stop bits`
328	6	julius	`endcase`
329			`end`
330			`else`
331			`if (counter == 5'b00001)`
332			`begin`
333	360	julius	`counter <= 0;`
334			`tstate <= s_idle;`
335	6	julius	`end`
336			`else`
337	363	julius	`counter <= counter - 5'd1;`
338	360	julius	`stx_o_tmp <= 1'b1;`
339	6	julius	`end`
340
341			`default : // should never get here`
342	360	julius	`tstate <= s_idle;`
343	6	julius	`endcase`
344			`end // end if enable`
345			`else`
346	360	julius	`tf_pop <= 1'b0; // tf_pop must be 1 cycle width`
347	6	julius	`end // transmitter logic`
348
349			assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
350
351			`endmodule`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart_transmitter.v] - Blame information for rev 363