OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [uart16550/] [uart_wb.v] - Blame information for rev 403

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  uart_wb.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the "UART 16550 compatible" project    ////
7
////  http://www.opencores.org/cores/uart16550/                   ////
8
////                                                              ////
9
////  Documentation related to this project:                      ////
10
////  - http://www.opencores.org/cores/uart16550/                 ////
11
////                                                              ////
12
////  Projects compatibility:                                     ////
13
////  - WISHBONE                                                  ////
14
////  RS232 Protocol                                              ////
15
////  16550D uart (mostly supported)                              ////
16
////                                                              ////
17
////  Overview (main Features):                                   ////
18
////  UART core WISHBONE interface.                               ////
19
////                                                              ////
20
////  Known problems (limits):                                    ////
21
////  Inserts one wait state on all transfers.                    ////
22
////  Note affected signals and the way they are affected.        ////
23
////                                                              ////
24
////  To Do:                                                      ////
25
////  Nothing.                                                    ////
26
////                                                              ////
27
////  Author(s):                                                  ////
28
////      - gorban@opencores.org                                  ////
29
////      - Jacob Gorban                                          ////
30
////      - Igor Mohor (igorm@opencores.org)                      ////
31
////                                                              ////
32
////  Created:        2001/05/12                                  ////
33
////  Last Updated:   2001/05/17                                  ////
34
////                  (See log for the revision history)          ////
35
////                                                              ////
36
////                                                              ////
37
//////////////////////////////////////////////////////////////////////
38
////                                                              ////
39
//// Copyright (C) 2000, 2001 Authors                             ////
40
////                                                              ////
41
//// This source file may be used and distributed without         ////
42
//// restriction provided that this copyright statement is not    ////
43
//// removed from the file and that any derivative work contains  ////
44
//// the original copyright notice and the associated disclaimer. ////
45
////                                                              ////
46
//// This source file is free software; you can redistribute it   ////
47
//// and/or modify it under the terms of the GNU Lesser General   ////
48
//// Public License as published by the Free Software Foundation; ////
49
//// either version 2.1 of the License, or (at your option) any   ////
50
//// later version.                                               ////
51
////                                                              ////
52
//// This source is distributed in the hope that it will be       ////
53
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
54
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
55
//// PURPOSE.  See the GNU Lesser General Public License for more ////
56
//// details.                                                     ////
57
////                                                              ////
58
//// You should have received a copy of the GNU Lesser General    ////
59
//// Public License along with this source; if not, download it   ////
60
//// from http://www.opencores.org/lgpl.shtml                     ////
61
////                                                              ////
62
//////////////////////////////////////////////////////////////////////
63
//
64
// CVS Revision History
65
//
66 360 julius
// $Log: not supported by cvs2svn $
67 6 julius
// Revision 1.16  2002/07/29 21:16:18  gorban
68
// The uart_defines.v file is included again in sources.
69
//
70
// Revision 1.15  2002/07/22 23:02:23  gorban
71
// Bug Fixes:
72
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
73
//   Problem reported by Kenny.Tung.
74
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
75
//
76
// Improvements:
77
//  * Made FIFO's as general inferrable memory where possible.
78
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
79
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
80
//
81
//  * Added optional baudrate output (baud_o).
82
//  This is identical to BAUDOUT* signal on 16550 chip.
83
//  It outputs 16xbit_clock_rate - the divided clock.
84
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
85
//
86
// Revision 1.12  2001/12/19 08:03:34  mohor
87
// Warnings cleared.
88
//
89
// Revision 1.11  2001/12/06 14:51:04  gorban
90
// Bug in LSR[0] is fixed.
91
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
92
//
93
// Revision 1.10  2001/12/03 21:44:29  gorban
94
// Updated specification documentation.
95
// Added full 32-bit data bus interface, now as default.
96
// Address is 5-bit wide in 32-bit data bus mode.
97
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
98
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
99
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
100
// My small test bench is modified to work with 32-bit mode.
101
//
102
// Revision 1.9  2001/10/20 09:58:40  gorban
103
// Small synopsis fixes
104
//
105
// Revision 1.8  2001/08/24 21:01:12  mohor
106
// Things connected to parity changed.
107
// Clock devider changed.
108
//
109
// Revision 1.7  2001/08/23 16:05:05  mohor
110
// Stop bit bug fixed.
111
// Parity bug fixed.
112
// WISHBONE read cycle bug fixed,
113
// OE indicator (Overrun Error) bug fixed.
114
// PE indicator (Parity Error) bug fixed.
115
// Register read bug fixed.
116
//
117
// Revision 1.4  2001/05/31 20:08:01  gorban
118
// FIFO changes and other corrections.
119
//
120
// Revision 1.3  2001/05/21 19:12:01  gorban
121
// Corrected some Linter messages.
122
//
123
// Revision 1.2  2001/05/17 18:34:18  gorban
124
// First 'stable' release. Should be sythesizable now. Also added new header.
125
//
126
// Revision 1.0  2001-05-17 21:27:13+02  jacob
127
// Initial revision
128
//
129
//
130
 
131
// UART core WISHBONE interface 
132
//
133
// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
134
// Company: Flextronics Semiconductor
135
//
136
 
137
// synopsys translate_off
138
`include "timescale.v"
139
// synopsys translate_on
140
`include "uart_defines.v"
141
 
142
module uart_wb (clk, wb_rst_i,
143
        wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
144
        wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
145
        we_o, re_o // Write and read enable output for the core
146
);
147
 
148
input             clk;
149
 
150
// WISHBONE interface   
151
input             wb_rst_i;
152
input             wb_we_i;
153
input             wb_stb_i;
154
input             wb_cyc_i;
155
input [3:0]   wb_sel_i;
156
input [`UART_ADDR_WIDTH-1:0]     wb_adr_i; //WISHBONE address line
157
 
158
`ifdef DATA_BUS_WIDTH_8
159
input [7:0]  wb_dat_i; //input WISHBONE bus 
160
output [7:0] wb_dat_o;
161
reg [7:0]         wb_dat_o;
162
wire [7:0]        wb_dat_i;
163
reg [7:0]         wb_dat_is;
164
`else // for 32 data bus mode
165
input [31:0]  wb_dat_i; //input WISHBONE bus 
166
output [31:0] wb_dat_o;
167
reg [31:0]         wb_dat_o;
168
wire [31:0]   wb_dat_i;
169
reg [31:0]         wb_dat_is;
170
`endif // !`ifdef DATA_BUS_WIDTH_8
171
 
172
output [`UART_ADDR_WIDTH-1:0]    wb_adr_int; // internal signal for address bus
173
input [7:0]   wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
174
output [7:0]  wb_dat8_i;
175
input [31:0]  wb_dat32_o; // 32 bit data output (for debug interface)
176
output            wb_ack_o;
177
output            we_o;
178
output            re_o;
179
 
180
wire                      we_o;
181
reg                       wb_ack_o;
182
reg [7:0]          wb_dat8_i;
183
wire [7:0]         wb_dat8_o;
184
wire [`UART_ADDR_WIDTH-1:0]      wb_adr_int; // internal signal for address bus
185
reg [`UART_ADDR_WIDTH-1:0]       wb_adr_is;
186
reg                                                             wb_we_is;
187
reg                                                             wb_cyc_is;
188
reg                                                             wb_stb_is;
189
reg [3:0]                                                wb_sel_is;
190
wire [3:0]   wb_sel_i;
191
reg                      wre ;// timing control signal for write or read enable
192
 
193
// wb_ack_o FSM
194
reg [1:0]         wbstate;
195
always  @(posedge clk or posedge wb_rst_i)
196
        if (wb_rst_i) begin
197 360 julius
                wb_ack_o <=  1'b0;
198
                wbstate <=  0;
199
                wre <=  1'b1;
200 6 julius
        end else
201
                case (wbstate)
202
                        0: begin
203
                                if (wb_stb_is & wb_cyc_is) begin
204 360 julius
                                        wre <=  0;
205
                                        wbstate <=  1;
206
                                        wb_ack_o <=  1;
207 6 julius
                                end else begin
208 360 julius
                                        wre <=  1;
209
                                        wb_ack_o <=  0;
210 6 julius
                                end
211
                        end
212
                        1: begin
213 360 julius
                           wb_ack_o <=  0;
214
                                wbstate <=  2;
215
                                wre <=  0;
216 6 julius
                        end
217
                        2,3: begin
218 360 julius
                                wb_ack_o <=  0;
219
                                wbstate <=  0;
220
                                wre <=  0;
221 6 julius
                        end
222
                endcase
223
 
224
assign we_o =  wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers      
225
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers      
226
 
227
// Sample input signals
228
always  @(posedge clk or posedge wb_rst_i)
229
        if (wb_rst_i) begin
230 360 julius
                wb_adr_is <=  0;
231
                wb_we_is <=  0;
232
                wb_cyc_is <=  0;
233
                wb_stb_is <=  0;
234
                wb_dat_is <=  0;
235
                wb_sel_is <=  0;
236 6 julius
        end else begin
237 360 julius
                wb_adr_is <=  wb_adr_i;
238
                wb_we_is <=  wb_we_i;
239
                wb_cyc_is <=  wb_cyc_i;
240
                wb_stb_is <=  wb_stb_i;
241
                wb_dat_is <=  wb_dat_i;
242
                wb_sel_is <=  wb_sel_i;
243 6 julius
        end
244
 
245
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
246
always @(posedge clk or posedge wb_rst_i)
247
        if (wb_rst_i)
248 360 julius
                wb_dat_o <=  0;
249 6 julius
        else
250 360 julius
                wb_dat_o <=  wb_dat8_o;
251 6 julius
 
252
always @(wb_dat_is)
253
        wb_dat8_i = wb_dat_is;
254
 
255
assign wb_adr_int = wb_adr_is;
256
 
257
`else // 32-bit bus
258
// put output to the correct byte in 32 bits using select line
259
always @(posedge clk or posedge wb_rst_i)
260
        if (wb_rst_i)
261 360 julius
                wb_dat_o <=  0;
262 6 julius
        else if (re_o)
263
                case (wb_sel_is)
264 360 julius
                        4'b0001: wb_dat_o <=  {24'b0, wb_dat8_o};
265
                        4'b0010: wb_dat_o <=  {16'b0, wb_dat8_o, 8'b0};
266
                        4'b0100: wb_dat_o <=  {8'b0, wb_dat8_o, 16'b0};
267
                        4'b1000: wb_dat_o <=  {wb_dat8_o, 24'b0};
268
                        4'b1111: wb_dat_o <=  wb_dat32_o; // debug interface output
269
                        default: wb_dat_o <=  0;
270 6 julius
                endcase // case(wb_sel_i)
271
 
272
reg [1:0] wb_adr_int_lsb;
273
 
274
always @(wb_sel_is or wb_dat_is)
275
begin
276
        case (wb_sel_is)
277
                4'b0001 : wb_dat8_i = wb_dat_is[7:0];
278
                4'b0010 : wb_dat8_i = wb_dat_is[15:8];
279
                4'b0100 : wb_dat8_i = wb_dat_is[23:16];
280
                4'b1000 : wb_dat8_i = wb_dat_is[31:24];
281
                default : wb_dat8_i = wb_dat_is[7:0];
282
        endcase // case(wb_sel_i)
283
 
284
  `ifdef LITLE_ENDIAN
285
        case (wb_sel_is)
286
                4'b0001 : wb_adr_int_lsb = 2'h0;
287
                4'b0010 : wb_adr_int_lsb = 2'h1;
288
                4'b0100 : wb_adr_int_lsb = 2'h2;
289
                4'b1000 : wb_adr_int_lsb = 2'h3;
290
                default : wb_adr_int_lsb = 2'h0;
291
        endcase // case(wb_sel_i)
292
  `else
293
        case (wb_sel_is)
294
                4'b0001 : wb_adr_int_lsb = 2'h3;
295
                4'b0010 : wb_adr_int_lsb = 2'h2;
296
                4'b0100 : wb_adr_int_lsb = 2'h1;
297
                4'b1000 : wb_adr_int_lsb = 2'h0;
298
                default : wb_adr_int_lsb = 2'h0;
299
        endcase // case(wb_sel_i)
300
  `endif
301
end
302
 
303
assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
304
 
305
`endif // !`ifdef DATA_BUS_WIDTH_8
306
 
307
endmodule
308
 
309
 
310
 
311
 
312
 
313
 
314
 
315
 
316
 
317
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.