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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [SOFTransmit.v] - Blame information for rev 435

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// File        : ../RTL/hostController/softransmit.v
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// Generated   : 11/10/06 05:37:21
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// From        : ../RTL/hostController/softransmit.asf
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// By          : FSM2VHDL ver. 5.0.0.9
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// softransmit
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// http://www.opencores.org/cores/usbhostslave/                 ////
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////                                                              ////
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//// Module Description:                                          ////
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbhostslave_hostcontrol_h.v"
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module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
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input   SOFEnable;              // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
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input   SOFSyncEn;
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input   [15:0] SOFTimer;
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input   clk;
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input   rst;
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input   sendPacketArbiterGnt;
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input   sendPacketRdy;
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output  SOFSent;                // single cycle pulse
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output  SOFTimerClr;            // Single cycle pulse
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output  sendPacketArbiterReq;
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output  sendPacketWEn;
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wire    SOFEnable;
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reg     SOFSent, next_SOFSent;
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wire    SOFSyncEn;
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reg     SOFTimerClr, next_SOFTimerClr;
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wire    [15:0] SOFTimer;
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wire    clk;
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wire    rst;
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wire    sendPacketArbiterGnt;
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reg     sendPacketArbiterReq, next_sendPacketArbiterReq;
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wire    sendPacketRdy;
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reg     sendPacketWEn, next_sendPacketWEn;
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// diagram signals declarations
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reg  [7:0]i, next_i;
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// BINARY ENCODED state machine: SOFTx
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// State codes definitions:
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`define START_STX 3'b000
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`define WAIT_SOF_NEAR 3'b001
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`define WAIT_SP_GNT 3'b010
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`define WAIT_SOF_NOW 3'b011
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`define SOF_FIN 3'b100
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`define DLY_SOF_CHK1 3'b101
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`define DLY_SOF_CHK2 3'b110
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reg [2:0] CurrState_SOFTx;
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reg [2:0] NextState_SOFTx;
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//--------------------------------------------------------------------
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// Machine: SOFTx
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//--------------------------------------------------------------------
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//----------------------------------
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// Next State Logic (combinatorial)
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//----------------------------------
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always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
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begin : SOFTx_NextState
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  NextState_SOFTx <= CurrState_SOFTx;
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  // Set default values for outputs and signals
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  next_sendPacketArbiterReq <= sendPacketArbiterReq;
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  next_sendPacketWEn <= sendPacketWEn;
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  next_SOFTimerClr <= SOFTimerClr;
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  next_SOFSent <= SOFSent;
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  next_i <= i;
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  case (CurrState_SOFTx)
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    `START_STX:
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      NextState_SOFTx <= `WAIT_SOF_NEAR;
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    `WAIT_SOF_NEAR:
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      if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
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        (SOFSyncEn == 1'b1 &&
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        SOFEnable == 1'b1))
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      begin
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        NextState_SOFTx <= `WAIT_SP_GNT;
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        next_sendPacketArbiterReq <= 1'b1;
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      end
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    `WAIT_SP_GNT:
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      if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
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        NextState_SOFTx <= `WAIT_SOF_NOW;
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    `WAIT_SOF_NOW:
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      if (SOFTimer >= `SOF_TX_TIME)
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      begin
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        NextState_SOFTx <= `SOF_FIN;
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        next_sendPacketWEn <= 1'b1;
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        next_SOFTimerClr <= 1'b1;
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        next_SOFSent <= 1'b1;
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      end
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      else if (SOFEnable == 1'b0)
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      begin
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        NextState_SOFTx <= `SOF_FIN;
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        next_SOFTimerClr <= 1'b1;
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      end
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    `SOF_FIN:
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    begin
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      next_sendPacketWEn <= 1'b0;
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      next_SOFTimerClr <= 1'b0;
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      next_SOFSent <= 1'b0;
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      if (sendPacketRdy == 1'b1)
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      begin
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        NextState_SOFTx <= `DLY_SOF_CHK1;
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        next_i <= 8'h00;
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      end
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    end
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    `DLY_SOF_CHK1:
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    begin
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      next_i <= i + 1'b1;
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      if (i==8'hff)
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      begin
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        NextState_SOFTx <= `DLY_SOF_CHK2;
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        next_sendPacketArbiterReq <= 1'b0;
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        next_i <= 8'h00;
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      end
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    end
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    `DLY_SOF_CHK2:
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    begin
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      next_i <= i + 1'b1;
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      if (i==8'hff)
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        NextState_SOFTx <= `WAIT_SOF_NEAR;
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    end
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  endcase
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end
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//----------------------------------
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// Current State Logic (sequential)
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//----------------------------------
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always @ (posedge clk)
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begin : SOFTx_CurrentState
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  if (rst)
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    CurrState_SOFTx <= `START_STX;
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  else
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    CurrState_SOFTx <= NextState_SOFTx;
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end
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//----------------------------------
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// Registered outputs logic
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//----------------------------------
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always @ (posedge clk)
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begin : SOFTx_RegOutput
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  if (rst)
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  begin
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    i <= 8'h00;
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    SOFSent <= 1'b0;
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    SOFTimerClr <= 1'b0;
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    sendPacketArbiterReq <= 1'b0;
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    sendPacketWEn <= 1'b0;
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  end
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  else
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  begin
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    i <= next_i;
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    SOFSent <= next_SOFSent;
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    SOFTimerClr <= next_SOFTimerClr;
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    sendPacketArbiterReq <= next_sendPacketArbiterReq;
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    sendPacketWEn <= next_sendPacketWEn;
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  end
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end
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endmodule

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