URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [processTxByte.v] - Blame information for rev 408

Details | Compare with Previous | View Log


 
// File        : ../RTL/serialInterfaceEngine/processTxByte.v
// Generated   : 11/10/06 05:37:23
// From        : ../RTL/serialInterfaceEngine/processTxByte.asf
// By          : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// processTxByte
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/                 ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbhostslave_serialinterfaceengine_h.v"
`include "usbhostslave_constants_h.v"
 
module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);
input   [1:0] JBit;
input   [1:0] KBit;
input   [7:0] TxByteCtrlIn;
input   TxByteFullSpeedRateIn;
input   [7:0] TxByteIn;
input   USBWireGnt;
input   USBWireRdy;
input   clk;
input   processTxByteWEn;
input   rst;
output  USBWireCtrl;
output  [1:0] USBWireData;
output  USBWireFullSpeedRate;
output  USBWireReq;
output  USBWireWEn;
output  processTxByteRdy;
 
wire    [1:0] JBit;
wire    [1:0] KBit;
wire    [7:0] TxByteCtrlIn;
wire    TxByteFullSpeedRateIn;
wire    [7:0] TxByteIn;
reg     USBWireCtrl, next_USBWireCtrl;
reg     [1:0] USBWireData, next_USBWireData;
reg     USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire    USBWireGnt;
wire    USBWireRdy;
reg     USBWireReq, next_USBWireReq;
reg     USBWireWEn, next_USBWireWEn;
wire    clk;
reg     processTxByteRdy, next_processTxByteRdy;
wire    processTxByteWEn;
wire    rst;
 
// diagram signals declarations
reg  [1:0]TXLineState, next_TXLineState;
reg  [3:0]TXOneCount, next_TXOneCount;
reg  [7:0]TxByteCtrl, next_TxByteCtrl;
reg  TxByteFullSpeedRate, next_TxByteFullSpeedRate;
reg  [7:0]TxByte, next_TxByte;
reg  [3:0]i, next_i;
 
// BINARY ENCODED state machine: prcTxB
// State codes definitions:
`define START_PTBY 5'b00000
`define PTBY_WAIT_EN 5'b00001
`define SEND_BYTE_UPDATE_BYTE 5'b00010
`define SEND_BYTE_WAIT_RDY 5'b00011
`define SEND_BYTE_CHK 5'b00100
`define SEND_BYTE_BIT_STUFF 5'b00101
`define SEND_BYTE_WAIT_RDY2 5'b00110
`define SEND_BYTE_CHK_FIN 5'b00111
`define PTBY_WAIT_GNT 5'b01000
`define STOP_SND_SE0_2 5'b01001
`define STOP_SND_SE0_1 5'b01010
`define STOP_CHK 5'b01011
`define STOP_SND_J 5'b01100
`define STOP_SND_IDLE 5'b01101
`define STOP_FIN 5'b01110
`define WAIT_RDY_WIRE 5'b01111
`define WAIT_RDY_PKT 5'b10000
`define LS_START_SND_IDLE3 5'b10001
`define LS_START_SND_J1 5'b10010
`define LS_START_SND_IDLE1 5'b10011
`define LS_START_SND_IDLE2 5'b10100
`define LS_START_FIN 5'b10101
`define LS_START_W_RDY1 5'b10110
`define LS_START_W_RDY2 5'b10111
`define LS_START_W_RDY3 5'b11000
`define STOP_W_RDY1 5'b11001
`define STOP_W_RDY2 5'b11010
`define STOP_W_RDY3 5'b11011
`define STOP_W_RDY4 5'b11100
 
reg [4:0] CurrState_prcTxB;
reg [4:0] NextState_prcTxB;
 
 
//--------------------------------------------------------------------
// Machine: prcTxB
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)
begin : prcTxB_NextState
  NextState_prcTxB <= CurrState_prcTxB;
  // Set default values for outputs and signals
  next_processTxByteRdy <= processTxByteRdy;
  next_USBWireData <= USBWireData;
  next_USBWireCtrl <= USBWireCtrl;
  next_USBWireReq <= USBWireReq;
  next_USBWireWEn <= USBWireWEn;
  next_i <= i;
  next_TxByte <= TxByte;
  next_TxByteCtrl <= TxByteCtrl;
  next_TXLineState <= TXLineState;
  next_TXOneCount <= TXOneCount;
  next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
  next_TxByteFullSpeedRate <= TxByteFullSpeedRate;
  case (CurrState_prcTxB)
    `START_PTBY:
    begin
      next_processTxByteRdy <= 1'b0;
      next_USBWireData <= 2'b00;
      next_USBWireCtrl <= `TRI_STATE;
      next_USBWireReq <= 1'b0;
      next_USBWireWEn <= 1'b0;
      next_i <= 4'h0;
      next_TxByte <= 8'h00;
      next_TxByteCtrl <= 8'h00;
      next_TXLineState <= 2'b0;
      next_TXOneCount <= 4'h0;
      next_USBWireFullSpeedRate <= 1'b0;
      next_TxByteFullSpeedRate <= 1'b0;
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `PTBY_WAIT_EN:
    begin
      next_processTxByteRdy <= 1'b1;
      if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
      begin
        NextState_prcTxB <= `PTBY_WAIT_GNT;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
        next_TXOneCount <= 4'h0;
        next_TXLineState <= JBit;
        next_USBWireReq <= 1'b1;
      end
      else if (processTxByteWEn == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
        next_processTxByteRdy <= 1'b0;
        next_TxByte <= TxByteIn;
        next_TxByteCtrl <= TxByteCtrlIn;
        next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;
        next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;
        next_i <= 4'h0;
      end
    end
    `PTBY_WAIT_GNT:
      if (USBWireGnt == 1'b1)
        NextState_prcTxB <= `WAIT_RDY_WIRE;
    `WAIT_RDY_WIRE:
      if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate  == 1'b0))
        NextState_prcTxB <= `LS_START_SND_IDLE1;
      else if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `WAIT_RDY_PKT;
        //actively drive the first J bit
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
        next_USBWireWEn <= 1'b1;
      end
    `WAIT_RDY_PKT:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      next_i <= 4'h0;
    end
    `SEND_BYTE_UPDATE_BYTE:
    begin
      next_i <= i + 1'b1;
      next_TxByte <= {1'b0, TxByte[7:1] };
      if (TxByte[0] == 1'b1)                      //If this bit is 1, then
        next_TXOneCount <= TXOneCount + 1'b1;
          //increment 'TXOneCount'
      else                                        //else this is a zero bit
      begin
        next_TXOneCount <= 4'h0;
          //reset 'TXOneCount'
          if (TXLineState == JBit)
          next_TXLineState <= KBit;
              //toggle the line state
          else
          next_TXLineState <= JBit;
      end
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
    end
    `SEND_BYTE_WAIT_RDY:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    `SEND_BYTE_CHK:
    begin
      next_USBWireWEn <= 1'b0;
      if (TXOneCount == `MAX_CONSEC_SAME_BITS)
        NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
      else if (i != 4'h8)
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      else
        NextState_prcTxB <= `STOP_CHK;
    end
    `SEND_BYTE_BIT_STUFF:
    begin
      next_TXOneCount <= 4'h0;
      //reset 'TXOneCount'
      if (TXLineState == JBit)
        next_TXLineState <= KBit;
          //toggle the line state
      else
        next_TXLineState <= JBit;
      NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
    end
    `SEND_BYTE_WAIT_RDY2:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= TXLineState;
        next_USBWireCtrl <= `DRIVE;
      end
    `SEND_BYTE_CHK_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      if (i == 4'h8)
        NextState_prcTxB <= `STOP_CHK;
      else
        NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
    end
    `STOP_SND_SE0_2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `STOP_W_RDY2;
    end
    `STOP_SND_SE0_1:
      NextState_prcTxB <= `STOP_W_RDY1;
    `STOP_CHK:
      if (TxByteCtrl == `DATA_STOP)
        NextState_prcTxB <= `STOP_SND_SE0_1;
      else
        NextState_prcTxB <= `PTBY_WAIT_EN;
    `STOP_SND_J:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `STOP_W_RDY3;
    end
    `STOP_SND_IDLE:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `STOP_W_RDY4;
    end
    `STOP_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      next_USBWireReq <= 1'b0;
      //release the wire
      NextState_prcTxB <= `PTBY_WAIT_EN;
    end
    `STOP_W_RDY1:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_SE0_2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    `STOP_W_RDY2:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_J;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= `SE0;
        next_USBWireCtrl <= `DRIVE;
      end
    `STOP_W_RDY3:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_SND_IDLE;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
    `STOP_W_RDY4:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `STOP_FIN;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    `LS_START_SND_IDLE3:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `LS_START_W_RDY2;
    end
    `LS_START_SND_J1:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `LS_START_W_RDY3;
    end
    `LS_START_SND_IDLE1:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE2;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    `LS_START_SND_IDLE2:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `LS_START_W_RDY1;
    end
    `LS_START_FIN:
    begin
      next_USBWireWEn <= 1'b0;
      NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
      next_i <= 4'h0;
    end
    `LS_START_W_RDY1:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_IDLE3;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    `LS_START_W_RDY2:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_SND_J1;
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `TRI_STATE;
      end
    `LS_START_W_RDY3:
      if (USBWireRdy == 1'b1)
      begin
        NextState_prcTxB <= `LS_START_FIN;
        //Drive the first JBit
        next_USBWireWEn <= 1'b1;
        next_USBWireData <= JBit;
        next_USBWireCtrl <= `DRIVE;
      end
  endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prcTxB_CurrentState
  if (rst)
    CurrState_prcTxB <= `START_PTBY;
  else
    CurrState_prcTxB <= NextState_prcTxB;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prcTxB_RegOutput
  if (rst)
  begin
    i <= 4'h0;
    TxByte <= 8'h00;
    TxByteCtrl <= 8'h00;
    TXLineState <= 2'b0;
    TXOneCount <= 4'h0;
    TxByteFullSpeedRate <= 1'b0;
    processTxByteRdy <= 1'b0;
    USBWireData <= 2'b00;
    USBWireCtrl <= `TRI_STATE;
    USBWireReq <= 1'b0;
    USBWireWEn <= 1'b0;
    USBWireFullSpeedRate <= 1'b0;
  end
  else
  begin
    i <= next_i;
    TxByte <= next_TxByte;
    TxByteCtrl <= next_TxByteCtrl;
    TXLineState <= next_TXLineState;
    TXOneCount <= next_TXOneCount;
    TxByteFullSpeedRate <= next_TxByteFullSpeedRate;
    processTxByteRdy <= next_processTxByteRdy;
    USBWireData <= next_USBWireData;
    USBWireCtrl <= next_USBWireCtrl;
    USBWireReq <= next_USBWireReq;
    USBWireWEn <= next_USBWireWEn;
    USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
  end
end
 
endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [processTxByte.v] - Blame information for rev 408

Line No.	Rev	Author	Line
1	408	julius
2			`// File : ../RTL/serialInterfaceEngine/processTxByte.v`
3			`// Generated : 11/10/06 05:37:23`
4			`// From : ../RTL/serialInterfaceEngine/processTxByte.asf`
5			`// By : FSM2VHDL ver. 5.0.0.9`
6
7			`//////////////////////////////////////////////////////////////////////`
8			`//// ////`
9			`//// processTxByte`
10			`//// ////`
11			`//// This file is part of the usbhostslave opencores effort.`
12			`//// http://www.opencores.org/cores/usbhostslave/ ////`
13			`//// ////`
14			`//// Module Description: ////`
15			`////`
16			`//// ////`
17			`//// To Do: ////`
18			`////`
19			`//// ////`
20			`//// Author(s): ////`
21			`//// - Steve Fielding, sfielding@base2designs.com ////`
22			`//// ////`
23			`//////////////////////////////////////////////////////////////////////`
24			`//// ////`
25			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
26			`//// ////`
27			`//// This source file may be used and distributed without ////`
28			`//// restriction provided that this copyright statement is not ////`
29			`//// removed from the file and that any derivative work contains ////`
30			`//// the original copyright notice and the associated disclaimer. ////`
31			`//// ////`
32			`//// This source file is free software; you can redistribute it ////`
33			`//// and/or modify it under the terms of the GNU Lesser General ////`
34			`//// Public License as published by the Free Software Foundation; ////`
35			`//// either version 2.1 of the License, or (at your option) any ////`
36			`//// later version. ////`
37			`//// ////`
38			`//// This source is distributed in the hope that it will be ////`
39			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
40			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
41			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
42			`//// details. ////`
43			`//// ////`
44			`//// You should have received a copy of the GNU Lesser General ////`
45			`//// Public License along with this source; if not, download it ////`
46			`//// from http://www.opencores.org/lgpl.shtml ////`
47			`//// ////`
48			`//////////////////////////////////////////////////////////////////////`
49			`//`
50			`include "timescale.v"
51			`include "usbhostslave_serialinterfaceengine_h.v"
52			`include "usbhostslave_constants_h.v"
53
54			`module processTxByte (JBit, KBit, TxByteCtrlIn, TxByteFullSpeedRateIn, TxByteIn, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, processTxByteRdy, processTxByteWEn, rst);`
55			`input [1:0] JBit;`
56			`input [1:0] KBit;`
57			`input [7:0] TxByteCtrlIn;`
58			`input TxByteFullSpeedRateIn;`
59			`input [7:0] TxByteIn;`
60			`input USBWireGnt;`
61			`input USBWireRdy;`
62			`input clk;`
63			`input processTxByteWEn;`
64			`input rst;`
65			`output USBWireCtrl;`
66			`output [1:0] USBWireData;`
67			`output USBWireFullSpeedRate;`
68			`output USBWireReq;`
69			`output USBWireWEn;`
70			`output processTxByteRdy;`
71
72			`wire [1:0] JBit;`
73			`wire [1:0] KBit;`
74			`wire [7:0] TxByteCtrlIn;`
75			`wire TxByteFullSpeedRateIn;`
76			`wire [7:0] TxByteIn;`
77			`reg USBWireCtrl, next_USBWireCtrl;`
78			`reg [1:0] USBWireData, next_USBWireData;`
79			`reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;`
80			`wire USBWireGnt;`
81			`wire USBWireRdy;`
82			`reg USBWireReq, next_USBWireReq;`
83			`reg USBWireWEn, next_USBWireWEn;`
84			`wire clk;`
85			`reg processTxByteRdy, next_processTxByteRdy;`
86			`wire processTxByteWEn;`
87			`wire rst;`
88
89			`// diagram signals declarations`
90			`reg [1:0]TXLineState, next_TXLineState;`
91			`reg [3:0]TXOneCount, next_TXOneCount;`
92			`reg [7:0]TxByteCtrl, next_TxByteCtrl;`
93			`reg TxByteFullSpeedRate, next_TxByteFullSpeedRate;`
94			`reg [7:0]TxByte, next_TxByte;`
95			`reg [3:0]i, next_i;`
96
97			`// BINARY ENCODED state machine: prcTxB`
98			`// State codes definitions:`
99			`define START_PTBY 5'b00000
100			`define PTBY_WAIT_EN 5'b00001
101			`define SEND_BYTE_UPDATE_BYTE 5'b00010
102			`define SEND_BYTE_WAIT_RDY 5'b00011
103			`define SEND_BYTE_CHK 5'b00100
104			`define SEND_BYTE_BIT_STUFF 5'b00101
105			`define SEND_BYTE_WAIT_RDY2 5'b00110
106			`define SEND_BYTE_CHK_FIN 5'b00111
107			`define PTBY_WAIT_GNT 5'b01000
108			`define STOP_SND_SE0_2 5'b01001
109			`define STOP_SND_SE0_1 5'b01010
110			`define STOP_CHK 5'b01011
111			`define STOP_SND_J 5'b01100
112			`define STOP_SND_IDLE 5'b01101
113			`define STOP_FIN 5'b01110
114			`define WAIT_RDY_WIRE 5'b01111
115			`define WAIT_RDY_PKT 5'b10000
116			`define LS_START_SND_IDLE3 5'b10001
117			`define LS_START_SND_J1 5'b10010
118			`define LS_START_SND_IDLE1 5'b10011
119			`define LS_START_SND_IDLE2 5'b10100
120			`define LS_START_FIN 5'b10101
121			`define LS_START_W_RDY1 5'b10110
122			`define LS_START_W_RDY2 5'b10111
123			`define LS_START_W_RDY3 5'b11000
124			`define STOP_W_RDY1 5'b11001
125			`define STOP_W_RDY2 5'b11010
126			`define STOP_W_RDY3 5'b11011
127			`define STOP_W_RDY4 5'b11100
128
129			`reg [4:0] CurrState_prcTxB;`
130			`reg [4:0] NextState_prcTxB;`
131
132
133			`//--------------------------------------------------------------------`
134			`// Machine: prcTxB`
135			`//--------------------------------------------------------------------`
136			`//----------------------------------`
137			`// Next State Logic (combinatorial)`
138			`//----------------------------------`
139			`always @ (TxByteIn or TxByteCtrlIn or TxByteFullSpeedRateIn or JBit or i or TxByte or TXOneCount or TXLineState or KBit or processTxByteWEn or USBWireGnt or USBWireRdy or TxByteFullSpeedRate or TxByteCtrl or processTxByteRdy or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or USBWireFullSpeedRate or CurrState_prcTxB)`
140			`begin : prcTxB_NextState`
141			`NextState_prcTxB <= CurrState_prcTxB;`
142			`// Set default values for outputs and signals`
143			`next_processTxByteRdy <= processTxByteRdy;`
144			`next_USBWireData <= USBWireData;`
145			`next_USBWireCtrl <= USBWireCtrl;`
146			`next_USBWireReq <= USBWireReq;`
147			`next_USBWireWEn <= USBWireWEn;`
148			`next_i <= i;`
149			`next_TxByte <= TxByte;`
150			`next_TxByteCtrl <= TxByteCtrl;`
151			`next_TXLineState <= TXLineState;`
152			`next_TXOneCount <= TXOneCount;`
153			`next_USBWireFullSpeedRate <= USBWireFullSpeedRate;`
154			`next_TxByteFullSpeedRate <= TxByteFullSpeedRate;`
155			`case (CurrState_prcTxB)`
156			`START_PTBY:
157			`begin`
158			`next_processTxByteRdy <= 1'b0;`
159			`next_USBWireData <= 2'b00;`
160			next_USBWireCtrl <= `TRI_STATE;
161			`next_USBWireReq <= 1'b0;`
162			`next_USBWireWEn <= 1'b0;`
163			`next_i <= 4'h0;`
164			`next_TxByte <= 8'h00;`
165			`next_TxByteCtrl <= 8'h00;`
166			`next_TXLineState <= 2'b0;`
167			`next_TXOneCount <= 4'h0;`
168			`next_USBWireFullSpeedRate <= 1'b0;`
169			`next_TxByteFullSpeedRate <= 1'b0;`
170			NextState_prcTxB <= `PTBY_WAIT_EN;
171			`end`
172			`PTBY_WAIT_EN:
173			`begin`
174			`next_processTxByteRdy <= 1'b1;`
175			if ((processTxByteWEn == 1'b1) && (TxByteCtrlIn == `DATA_START))
176			`begin`
177			NextState_prcTxB <= `PTBY_WAIT_GNT;
178			`next_processTxByteRdy <= 1'b0;`
179			`next_TxByte <= TxByteIn;`
180			`next_TxByteCtrl <= TxByteCtrlIn;`
181			`next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;`
182			`next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;`
183			`next_TXOneCount <= 4'h0;`
184			`next_TXLineState <= JBit;`
185			`next_USBWireReq <= 1'b1;`
186			`end`
187			`else if (processTxByteWEn == 1'b1)`
188			`begin`
189			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
190			`next_processTxByteRdy <= 1'b0;`
191			`next_TxByte <= TxByteIn;`
192			`next_TxByteCtrl <= TxByteCtrlIn;`
193			`next_TxByteFullSpeedRate <= TxByteFullSpeedRateIn;`
194			`next_USBWireFullSpeedRate <= TxByteFullSpeedRateIn;`
195			`next_i <= 4'h0;`
196			`end`
197			`end`
198			`PTBY_WAIT_GNT:
199			`if (USBWireGnt == 1'b1)`
200			NextState_prcTxB <= `WAIT_RDY_WIRE;
201			`WAIT_RDY_WIRE:
202			`if ((USBWireRdy == 1'b1) && (TxByteFullSpeedRate == 1'b0))`
203			NextState_prcTxB <= `LS_START_SND_IDLE1;
204			`else if (USBWireRdy == 1'b1)`
205			`begin`
206			NextState_prcTxB <= `WAIT_RDY_PKT;
207			`//actively drive the first J bit`
208			`next_USBWireData <= JBit;`
209			next_USBWireCtrl <= `DRIVE;
210			`next_USBWireWEn <= 1'b1;`
211			`end`
212			`WAIT_RDY_PKT:
213			`begin`
214			`next_USBWireWEn <= 1'b0;`
215			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
216			`next_i <= 4'h0;`
217			`end`
218			`SEND_BYTE_UPDATE_BYTE:
219			`begin`
220			`next_i <= i + 1'b1;`
221			`next_TxByte <= {1'b0, TxByte[7:1] };`
222			`if (TxByte[0] == 1'b1) //If this bit is 1, then`
223			`next_TXOneCount <= TXOneCount + 1'b1;`
224			`//increment 'TXOneCount'`
225			`else //else this is a zero bit`
226			`begin`
227			`next_TXOneCount <= 4'h0;`
228			`//reset 'TXOneCount'`
229			`if (TXLineState == JBit)`
230			`next_TXLineState <= KBit;`
231			`//toggle the line state`
232			`else`
233			`next_TXLineState <= JBit;`
234			`end`
235			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY;
236			`end`
237			`SEND_BYTE_WAIT_RDY:
238			`if (USBWireRdy == 1'b1)`
239			`begin`
240			NextState_prcTxB <= `SEND_BYTE_CHK;
241			`next_USBWireWEn <= 1'b1;`
242			`next_USBWireData <= TXLineState;`
243			next_USBWireCtrl <= `DRIVE;
244			`end`
245			`SEND_BYTE_CHK:
246			`begin`
247			`next_USBWireWEn <= 1'b0;`
248			if (TXOneCount == `MAX_CONSEC_SAME_BITS)
249			NextState_prcTxB <= `SEND_BYTE_BIT_STUFF;
250			`else if (i != 4'h8)`
251			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
252			`else`
253			NextState_prcTxB <= `STOP_CHK;
254			`end`
255			`SEND_BYTE_BIT_STUFF:
256			`begin`
257			`next_TXOneCount <= 4'h0;`
258			`//reset 'TXOneCount'`
259			`if (TXLineState == JBit)`
260			`next_TXLineState <= KBit;`
261			`//toggle the line state`
262			`else`
263			`next_TXLineState <= JBit;`
264			NextState_prcTxB <= `SEND_BYTE_WAIT_RDY2;
265			`end`
266			`SEND_BYTE_WAIT_RDY2:
267			`if (USBWireRdy == 1'b1)`
268			`begin`
269			NextState_prcTxB <= `SEND_BYTE_CHK_FIN;
270			`next_USBWireWEn <= 1'b1;`
271			`next_USBWireData <= TXLineState;`
272			next_USBWireCtrl <= `DRIVE;
273			`end`
274			`SEND_BYTE_CHK_FIN:
275			`begin`
276			`next_USBWireWEn <= 1'b0;`
277			`if (i == 4'h8)`
278			NextState_prcTxB <= `STOP_CHK;
279			`else`
280			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
281			`end`
282			`STOP_SND_SE0_2:
283			`begin`
284			`next_USBWireWEn <= 1'b0;`
285			NextState_prcTxB <= `STOP_W_RDY2;
286			`end`
287			`STOP_SND_SE0_1:
288			NextState_prcTxB <= `STOP_W_RDY1;
289			`STOP_CHK:
290			if (TxByteCtrl == `DATA_STOP)
291			NextState_prcTxB <= `STOP_SND_SE0_1;
292			`else`
293			NextState_prcTxB <= `PTBY_WAIT_EN;
294			`STOP_SND_J:
295			`begin`
296			`next_USBWireWEn <= 1'b0;`
297			NextState_prcTxB <= `STOP_W_RDY3;
298			`end`
299			`STOP_SND_IDLE:
300			`begin`
301			`next_USBWireWEn <= 1'b0;`
302			NextState_prcTxB <= `STOP_W_RDY4;
303			`end`
304			`STOP_FIN:
305			`begin`
306			`next_USBWireWEn <= 1'b0;`
307			`next_USBWireReq <= 1'b0;`
308			`//release the wire`
309			NextState_prcTxB <= `PTBY_WAIT_EN;
310			`end`
311			`STOP_W_RDY1:
312			`if (USBWireRdy == 1'b1)`
313			`begin`
314			NextState_prcTxB <= `STOP_SND_SE0_2;
315			`next_USBWireWEn <= 1'b1;`
316			next_USBWireData <= `SE0;
317			next_USBWireCtrl <= `DRIVE;
318			`end`
319			`STOP_W_RDY2:
320			`if (USBWireRdy == 1'b1)`
321			`begin`
322			NextState_prcTxB <= `STOP_SND_J;
323			`next_USBWireWEn <= 1'b1;`
324			next_USBWireData <= `SE0;
325			next_USBWireCtrl <= `DRIVE;
326			`end`
327			`STOP_W_RDY3:
328			`if (USBWireRdy == 1'b1)`
329			`begin`
330			NextState_prcTxB <= `STOP_SND_IDLE;
331			`next_USBWireWEn <= 1'b1;`
332			`next_USBWireData <= JBit;`
333			next_USBWireCtrl <= `DRIVE;
334			`end`
335			`STOP_W_RDY4:
336			`if (USBWireRdy == 1'b1)`
337			`begin`
338			NextState_prcTxB <= `STOP_FIN;
339			`next_USBWireWEn <= 1'b1;`
340			`next_USBWireData <= JBit;`
341			next_USBWireCtrl <= `TRI_STATE;
342			`end`
343			`LS_START_SND_IDLE3:
344			`begin`
345			`next_USBWireWEn <= 1'b0;`
346			NextState_prcTxB <= `LS_START_W_RDY2;
347			`end`
348			`LS_START_SND_J1:
349			`begin`
350			`next_USBWireWEn <= 1'b0;`
351			NextState_prcTxB <= `LS_START_W_RDY3;
352			`end`
353			`LS_START_SND_IDLE1:
354			`if (USBWireRdy == 1'b1)`
355			`begin`
356			NextState_prcTxB <= `LS_START_SND_IDLE2;
357			`next_USBWireWEn <= 1'b1;`
358			`next_USBWireData <= JBit;`
359			next_USBWireCtrl <= `TRI_STATE;
360			`end`
361			`LS_START_SND_IDLE2:
362			`begin`
363			`next_USBWireWEn <= 1'b0;`
364			NextState_prcTxB <= `LS_START_W_RDY1;
365			`end`
366			`LS_START_FIN:
367			`begin`
368			`next_USBWireWEn <= 1'b0;`
369			NextState_prcTxB <= `SEND_BYTE_UPDATE_BYTE;
370			`next_i <= 4'h0;`
371			`end`
372			`LS_START_W_RDY1:
373			`if (USBWireRdy == 1'b1)`
374			`begin`
375			NextState_prcTxB <= `LS_START_SND_IDLE3;
376			`next_USBWireWEn <= 1'b1;`
377			`next_USBWireData <= JBit;`
378			next_USBWireCtrl <= `TRI_STATE;
379			`end`
380			`LS_START_W_RDY2:
381			`if (USBWireRdy == 1'b1)`
382			`begin`
383			NextState_prcTxB <= `LS_START_SND_J1;
384			`next_USBWireWEn <= 1'b1;`
385			`next_USBWireData <= JBit;`
386			next_USBWireCtrl <= `TRI_STATE;
387			`end`
388			`LS_START_W_RDY3:
389			`if (USBWireRdy == 1'b1)`
390			`begin`
391			NextState_prcTxB <= `LS_START_FIN;
392			`//Drive the first JBit`
393			`next_USBWireWEn <= 1'b1;`
394			`next_USBWireData <= JBit;`
395			next_USBWireCtrl <= `DRIVE;
396			`end`
397			`endcase`
398			`end`
399
400			`//----------------------------------`
401			`// Current State Logic (sequential)`
402			`//----------------------------------`
403			`always @ (posedge clk)`
404			`begin : prcTxB_CurrentState`
405			`if (rst)`
406			CurrState_prcTxB <= `START_PTBY;
407			`else`
408			`CurrState_prcTxB <= NextState_prcTxB;`
409			`end`
410
411			`//----------------------------------`
412			`// Registered outputs logic`
413			`//----------------------------------`
414			`always @ (posedge clk)`
415			`begin : prcTxB_RegOutput`
416			`if (rst)`
417			`begin`
418			`i <= 4'h0;`
419			`TxByte <= 8'h00;`
420			`TxByteCtrl <= 8'h00;`
421			`TXLineState <= 2'b0;`
422			`TXOneCount <= 4'h0;`
423			`TxByteFullSpeedRate <= 1'b0;`
424			`processTxByteRdy <= 1'b0;`
425			`USBWireData <= 2'b00;`
426			USBWireCtrl <= `TRI_STATE;
427			`USBWireReq <= 1'b0;`
428			`USBWireWEn <= 1'b0;`
429			`USBWireFullSpeedRate <= 1'b0;`
430			`end`
431			`else`
432			`begin`
433			`i <= next_i;`
434			`TxByte <= next_TxByte;`
435			`TxByteCtrl <= next_TxByteCtrl;`
436			`TXLineState <= next_TXLineState;`
437			`TXOneCount <= next_TXOneCount;`
438			`TxByteFullSpeedRate <= next_TxByteFullSpeedRate;`
439			`processTxByteRdy <= next_processTxByteRdy;`
440			`USBWireData <= next_USBWireData;`
441			`USBWireCtrl <= next_USBWireCtrl;`
442			`USBWireReq <= next_USBWireReq;`
443			`USBWireWEn <= next_USBWireWEn;`
444			`USBWireFullSpeedRate <= next_USBWireFullSpeedRate;`
445			`end`
446			`end`
447
448			`endmodule`