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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [readUSBWireData.v] - Blame information for rev 408

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1 408 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// readUSBWireData.v                                            ////
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////                                                              ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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////      This module reads data from the differential USB data lines
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////      and writes into a 4 entry FIFO. The data is read from
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////      the fifo and output from the module when the higher level
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////      state machine is ready to receive the data.
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////      This module must recover the clock phase from the incoming
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////      USB data. 'sampleCnt' is reset to zero whenever a RX data
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////      edge is detected. Note that due to metastability the data
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////      at the edge may not be registered correctly, but this does
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////      not matter. All that matters is that an edge was detected. The
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////      data will be accurately sampled in the middle of the USB bit 
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////      period without metastability issues. 
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////      After the edge detect, 'sampleCnt' is incremented at every clock
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////      tick, and when it indicates the middle of a USB bit period
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////      the RX data is sampled and written to the input buffer.
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////      Single clock tick adjustments to 'sampleCnt' can be made at 
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////      every RX data edge detect without double sampling the incoming
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////      data. However, the first RX data bit in a packet may cause 
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////      'sampleCnt' to be adjusted by a value greater than a single 
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////      clock tick, and this can result in double sampling of the 
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////      first data bit a RX packet. This 
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////      double sampled data must be rejected by the higher level module.
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////      This is achieved by 
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////      qualifying the outgoing data with 'RxWireActive'. Thus 
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////      the first data bit in a RX packet may be double sampled
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////      as the clock recovery mechanism synchronizes to 'RxBitsIn'
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////      but the double sampled data will be rejected by the higher 
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////      level module.
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbhostslave_serialinterfaceengine_h.v"
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module readUSBWireData (RxBitsIn, RxDataInTick, RxBitsOut, SIERxRdyIn, SIERxWEn, fullSpeedRate, TxWireActiveDrive, clk, rst, noActivityTimeOut, RxWireActive, noActivityTimeOutEnable);
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input   [1:0] RxBitsIn;
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output  RxDataInTick;
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input   SIERxRdyIn;
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input   clk;
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input   fullSpeedRate;
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input   rst;
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input   TxWireActiveDrive;
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output  [1:0] RxBitsOut;
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output  SIERxWEn;
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output noActivityTimeOut;
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output RxWireActive;
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input  noActivityTimeOutEnable;
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wire   [1:0] RxBitsIn;
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reg    RxDataInTick;
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wire   SIERxRdyIn;
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wire   clk;
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wire   fullSpeedRate;
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wire   rst;
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reg    [1:0] RxBitsOut;
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reg    SIERxWEn;
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reg    noActivityTimeOut;
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reg    RxWireActive;
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wire   noActivityTimeOutEnable;
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// local registers
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reg  [2:0]buffer0;
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reg  [2:0]buffer1;
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reg  [2:0]buffer2;
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reg  [2:0]buffer3;
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reg  [2:0]bufferCnt;
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reg  [1:0]bufferInIndex;
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reg  [1:0]bufferOutIndex;
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reg decBufferCnt;
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reg  [4:0]sampleCnt;
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reg incBufferCnt;
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reg  [1:0]oldRxBitsIn;
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reg [1:0] RxBitsInReg;
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reg [15:0] timeOutCnt;
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reg [7:0] rxActiveCnt;
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reg RxWireEdgeDetect;
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reg RxWireActiveReg;
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reg RxWireActiveReg2;
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reg [1:0] RxBitsInSyncReg1;
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reg [1:0] RxBitsInSyncReg2;
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// buffer output state machine state codes:
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`define WAIT_BUFFER_NOT_EMPTY 2'b00
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`define WAIT_SIE_RX_READY 2'b01
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`define SIE_RX_WRITE 2'b10
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// re-synchronize incoming bits
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always @(posedge clk) begin
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  RxBitsInSyncReg1 <= RxBitsIn;
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  RxBitsInSyncReg2 <= RxBitsInSyncReg1;
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end
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reg [1:0] bufferOutStMachCurrState;
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always @(posedge clk) begin
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  if (rst == 1'b1)
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  begin
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    bufferCnt <= 3'b000;
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  end
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  else begin
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    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
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      bufferCnt <= bufferCnt + 1'b1;
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    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
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      bufferCnt <= bufferCnt - 1'b1;
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  end
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end
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//Perform line rate clock recovery
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//Recover the wire data, and store data to buffer
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always @(posedge clk) begin
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  if (rst == 1'b1)
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  begin
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    sampleCnt <= 5'b00000;
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    incBufferCnt <= 1'b0;
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    bufferInIndex <= 2'b00;
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    buffer0 <= 3'b000;
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    buffer1 <= 3'b000;
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    buffer2 <= 3'b000;
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    buffer3 <= 3'b000;
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    RxDataInTick <= 1'b0;
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    RxWireEdgeDetect <= 1'b0;
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    RxWireActiveReg <= 1'b0;
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    RxWireActiveReg2 <= 1'b0;
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  end
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  else begin
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    RxWireActiveReg2 <= RxWireActiveReg; //Delay 'RxWireActiveReg' until after 'sampleCnt' has been reset
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    RxBitsInReg <= RxBitsInSyncReg2;
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    oldRxBitsIn <= RxBitsInReg;
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    incBufferCnt <= 1'b0;         //default value
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    if ( (TxWireActiveDrive == 1'b0) && (RxBitsInSyncReg2 != RxBitsInReg)) begin  //if edge detected then
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      sampleCnt <= 5'b00000;
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      RxWireEdgeDetect <= 1'b1;   // flag receive activity 
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      RxWireActiveReg <= 1'b1;
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      rxActiveCnt <= 8'h00;
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    end
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    else begin
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      sampleCnt <= sampleCnt + 1'b1;
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      RxWireEdgeDetect <= 1'b0;
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      rxActiveCnt <= rxActiveCnt + 1'b1;
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      //clear 'RxWireActiveReg' if no RX transitions for RX_EDGE_DET_TOUT USB bit periods 
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      if ( (fullSpeedRate == 1'b1 && rxActiveCnt == `RX_EDGE_DET_TOUT * `FS_OVER_SAMPLE_RATE)
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        || (fullSpeedRate == 1'b0 && rxActiveCnt == `RX_EDGE_DET_TOUT * `LS_OVER_SAMPLE_RATE) )
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        RxWireActiveReg <= 1'b0;
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    end
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    if ( (fullSpeedRate == 1'b1 && sampleCnt[1:0] == 2'b10) || (fullSpeedRate == 1'b0 && sampleCnt == 5'b10000) )
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    begin
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      RxDataInTick <= !RxDataInTick;
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      if (TxWireActiveDrive != 1'b1)  //do not read wire data when transmitter is active
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      begin
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        incBufferCnt <= 1'b1;
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        bufferInIndex <= bufferInIndex + 1'b1;
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        case (bufferInIndex)
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          2'b00 : buffer0 <= {RxWireActiveReg2, oldRxBitsIn};
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          2'b01 : buffer1 <= {RxWireActiveReg2, oldRxBitsIn};
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          2'b10 : buffer2 <= {RxWireActiveReg2, oldRxBitsIn};
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          2'b11 : buffer3 <= {RxWireActiveReg2, oldRxBitsIn};
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        endcase
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      end
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    end
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  end
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end
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//read from buffer, and output to SIEReceiver
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always @(posedge clk) begin
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  if (rst == 1'b1)
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  begin
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    decBufferCnt <= 1'b0;
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    bufferOutIndex <= 2'b00;
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    RxBitsOut <= 2'b00;
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    SIERxWEn <= 1'b0;
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    bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
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  end
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  else begin
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    case (bufferOutStMachCurrState)
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      `WAIT_BUFFER_NOT_EMPTY:
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      begin
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        if (bufferCnt != 3'b000)
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          bufferOutStMachCurrState <= `WAIT_SIE_RX_READY;
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      end
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      `WAIT_SIE_RX_READY:
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      begin
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        if (SIERxRdyIn == 1'b1)
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        begin
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          SIERxWEn <= 1'b1;
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          bufferOutStMachCurrState <= `SIE_RX_WRITE;
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          decBufferCnt <= 1'b1;
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          bufferOutIndex <= bufferOutIndex + 1'b1;
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          case (bufferOutIndex)
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            2'b00 : begin RxBitsOut <= buffer0[1:0]; RxWireActive <= buffer0[2]; end
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            2'b01 : begin RxBitsOut <= buffer1[1:0]; RxWireActive <= buffer1[2]; end
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            2'b10 : begin RxBitsOut <= buffer2[1:0]; RxWireActive <= buffer2[2]; end
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            2'b11 : begin RxBitsOut <= buffer3[1:0]; RxWireActive <= buffer3[2]; end
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          endcase
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        end
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      end
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      `SIE_RX_WRITE:
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      begin
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        SIERxWEn <= 1'b0;
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        decBufferCnt <= 1'b0;
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        bufferOutStMachCurrState <= `WAIT_BUFFER_NOT_EMPTY;
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      end
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    endcase
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  end
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end
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//generate 'noActivityTimeOut' pulse if no tx or rx activity for RX_PACKET_TOUT USB bit periods
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//'noActivityTimeOut'  pulse can only be generated when the host or slave getPacket
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//process enables via 'noActivityTimeOutEnable' signal
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//'noActivityTimeOut' pulse is used by host and slave getPacket processes to determine if 
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//there has been a response time out.
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always @(posedge clk) begin
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  if (rst) begin
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    timeOutCnt <= 16'h0000;
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    noActivityTimeOut <= 1'b0;
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  end
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  else begin
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    if (TxWireActiveDrive == 1'b1 || RxWireEdgeDetect == 1'b1 || noActivityTimeOutEnable == 1'b0)
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      timeOutCnt <= 16'h0000;
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    else
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      timeOutCnt <= timeOutCnt + 1'b1;
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    if ( (fullSpeedRate == 1'b1 && timeOutCnt == `RX_PACKET_TOUT * `FS_OVER_SAMPLE_RATE)
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      || (fullSpeedRate == 1'b0 && timeOutCnt == `RX_PACKET_TOUT * `LS_OVER_SAMPLE_RATE) )
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      noActivityTimeOut <= 1'b1;
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    else
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      noActivityTimeOut <= 1'b0;
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  end
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end
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endmodule

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