| 1 | 408 | julius | //////////////////////////////////////////////////////////////////////
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         | 2 |  |  | ////                                                              ////
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         | 3 |  |  | //// rxStatusMonitor.v                                            ////
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         | 4 |  |  | ////                                                              ////
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         | 5 |  |  | //// This file is part of the usbhostslave opencores effort.
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         | 6 |  |  | //// <http://www.opencores.org/cores//>                           ////
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         | 7 |  |  | ////                                                              ////
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         | 8 |  |  | //// Module Description:                                          ////
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         | 9 |  |  | //// 
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         | 10 |  |  | ////                                                              ////
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         | 11 |  |  | //// To Do:                                                       ////
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         | 12 |  |  | //// 
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         | 13 |  |  | ////                                                              ////
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         | 14 |  |  | //// Author(s):                                                   ////
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         | 15 |  |  | //// - Steve Fielding, sfielding@base2designs.com                 ////
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         | 16 |  |  | ////                                                              ////
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         | 17 |  |  | //////////////////////////////////////////////////////////////////////
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         | 18 |  |  | ////                                                              ////
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         | 19 |  |  | //// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
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         | 20 |  |  | ////                                                              ////
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         | 21 |  |  | //// This source file may be used and distributed without         ////
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         | 22 |  |  | //// restriction provided that this copyright statement is not    ////
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         | 23 |  |  | //// removed from the file and that any derivative work contains  ////
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         | 24 |  |  | //// the original copyright notice and the associated disclaimer. ////
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         | 25 |  |  | ////                                                              ////
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         | 26 |  |  | //// This source file is free software; you can redistribute it   ////
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         | 27 |  |  | //// and/or modify it under the terms of the GNU Lesser General   ////
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         | 28 |  |  | //// Public License as published by the Free Software Foundation; ////
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         | 29 |  |  | //// either version 2.1 of the License, or (at your option) any   ////
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         | 30 |  |  | //// later version.                                               ////
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         | 31 |  |  | ////                                                              ////
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         | 32 |  |  | //// This source is distributed in the hope that it will be       ////
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         | 33 |  |  | //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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         | 34 |  |  | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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         | 35 |  |  | //// PURPOSE. See the GNU Lesser General Public License for more  ////
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         | 36 |  |  | //// details.                                                     ////
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         | 37 |  |  | ////                                                              ////
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         | 38 |  |  | //// You should have received a copy of the GNU Lesser General    ////
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         | 39 |  |  | //// Public License along with this source; if not, download it   ////
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         | 40 |  |  | //// from <http://www.opencores.org/lgpl.shtml>                   ////
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         | 41 |  |  | ////                                                              ////
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         | 42 |  |  | //////////////////////////////////////////////////////////////////////
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         | 43 |  |  | //
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         | 44 |  |  | `include "timescale.v"
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         | 45 |  |  |  
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         | 46 |  |  | module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
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         | 47 |  |  |  
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         | 48 |  |  | input [1:0] connectStateIn;
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         | 49 |  |  | input resumeDetectedIn;
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         | 50 |  |  | input clk;
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         | 51 |  |  | input rst;
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         | 52 |  |  | output connectionEventOut;
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         | 53 |  |  | output [1:0] connectStateOut;
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         | 54 |  |  | output resumeIntOut;
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         | 55 |  |  |  
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         | 56 |  |  | wire [1:0] connectStateIn;
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         | 57 |  |  | wire resumeDetectedIn;
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         | 58 |  |  | reg connectionEventOut;
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         | 59 |  |  | reg [1:0] connectStateOut;
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         | 60 |  |  | reg resumeIntOut;
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         | 61 |  |  | wire clk;
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         | 62 |  |  | wire rst;
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         | 63 |  |  |  
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         | 64 |  |  | reg [1:0]oldConnectState;
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         | 65 |  |  | reg oldResumeDetected;
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         | 66 |  |  |  
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         | 67 |  |  | always @(connectStateIn)
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         | 68 |  |  | begin
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         | 69 |  |  |   connectStateOut <= connectStateIn;
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         | 70 |  |  | end
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         | 71 |  |  |  
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         | 72 |  |  |  
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         | 73 |  |  | always @(posedge clk)
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         | 74 |  |  | begin
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         | 75 |  |  |   if (rst == 1'b1)
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         | 76 |  |  |   begin
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         | 77 |  |  |     oldConnectState <= connectStateIn;
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         | 78 |  |  |     oldResumeDetected <= resumeDetectedIn;
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         | 79 |  |  |   end
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         | 80 |  |  |   else
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         | 81 |  |  |   begin
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         | 82 |  |  |     oldConnectState <= connectStateIn;
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         | 83 |  |  |     oldResumeDetected <= resumeDetectedIn;
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         | 84 |  |  |     if (oldConnectState != connectStateIn)
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         | 85 |  |  |       connectionEventOut <= 1'b1;
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         | 86 |  |  |     else
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         | 87 |  |  |       connectionEventOut <= 1'b0;
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         | 88 |  |  |     if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
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         | 89 |  |  |       resumeIntOut <= 1'b1;
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         | 90 |  |  |     else
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         | 91 |  |  |       resumeIntOut <= 1'b0;
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         | 92 |  |  |   end
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         | 93 |  |  | end
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         | 94 |  |  |  
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         | 95 |  |  | endmodule
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