OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [rxStatusMonitor.v] - Blame information for rev 522

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
//// rxStatusMonitor.v                                            ////
4
////                                                              ////
5
//// This file is part of the usbhostslave opencores effort.
6
//// <http://www.opencores.org/cores//>                           ////
7
////                                                              ////
8
//// Module Description:                                          ////
9
//// 
10
////                                                              ////
11
//// To Do:                                                       ////
12
//// 
13
////                                                              ////
14
//// Author(s):                                                   ////
15
//// - Steve Fielding, sfielding@base2designs.com                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE. See the GNU Lesser General Public License for more  ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from <http://www.opencores.org/lgpl.shtml>                   ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
`include "timescale.v"
45
 
46
module rxStatusMonitor(connectStateIn, connectStateOut, resumeDetectedIn, connectionEventOut, resumeIntOut, clk, rst);
47
 
48
input [1:0] connectStateIn;
49
input resumeDetectedIn;
50
input clk;
51
input rst;
52
output connectionEventOut;
53
output [1:0] connectStateOut;
54
output resumeIntOut;
55
 
56
wire [1:0] connectStateIn;
57
wire resumeDetectedIn;
58
reg connectionEventOut;
59
reg [1:0] connectStateOut;
60
reg resumeIntOut;
61
wire clk;
62
wire rst;
63
 
64
reg [1:0]oldConnectState;
65
reg oldResumeDetected;
66
 
67
always @(connectStateIn)
68
begin
69
  connectStateOut <= connectStateIn;
70
end
71
 
72
 
73
always @(posedge clk)
74
begin
75
  if (rst == 1'b1)
76
  begin
77
    oldConnectState <= connectStateIn;
78
    oldResumeDetected <= resumeDetectedIn;
79
  end
80
  else
81
  begin
82
    oldConnectState <= connectStateIn;
83
    oldResumeDetected <= resumeDetectedIn;
84
    if (oldConnectState != connectStateIn)
85
      connectionEventOut <= 1'b1;
86
    else
87
      connectionEventOut <= 1'b0;
88
    if (resumeDetectedIn == 1'b1 && oldResumeDetected == 1'b0)
89
      resumeIntOut <= 1'b1;
90
    else
91
      resumeIntOut <= 1'b0;
92
  end
93
end
94
 
95
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.