OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [sendPacketCheckPreamble.v] - Blame information for rev 408

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 408 julius
 
2
// File        : ../RTL/hostController/sendpacketcheckpreamble.v
3
// Generated   : 11/10/06 05:37:21
4
// From        : ../RTL/hostController/sendpacketcheckpreamble.asf
5
// By          : FSM2VHDL ver. 5.0.0.9
6
 
7
//////////////////////////////////////////////////////////////////////
8
////                                                              ////
9
//// sendpacketcheckpreamble
10
////                                                              ////
11
//// This file is part of the usbhostslave opencores effort.
12
//// http://www.opencores.org/cores/usbhostslave/                 ////
13
////                                                              ////
14
//// Module Description:                                          ////
15
//// 
16
////                                                              ////
17
//// To Do:                                                       ////
18
//// 
19
////                                                              ////
20
//// Author(s):                                                   ////
21
//// - Steve Fielding, sfielding@base2designs.com                 ////
22
////                                                              ////
23
//////////////////////////////////////////////////////////////////////
24
////                                                              ////
25
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
26
////                                                              ////
27
//// This source file may be used and distributed without         ////
28
//// restriction provided that this copyright statement is not    ////
29
//// removed from the file and that any derivative work contains  ////
30
//// the original copyright notice and the associated disclaimer. ////
31
////                                                              ////
32
//// This source file is free software; you can redistribute it   ////
33
//// and/or modify it under the terms of the GNU Lesser General   ////
34
//// Public License as published by the Free Software Foundation; ////
35
//// either version 2.1 of the License, or (at your option) any   ////
36
//// later version.                                               ////
37
////                                                              ////
38
//// This source is distributed in the hope that it will be       ////
39
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
40
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
41
//// PURPOSE. See the GNU Lesser General Public License for more  ////
42
//// details.                                                     ////
43
////                                                              ////
44
//// You should have received a copy of the GNU Lesser General    ////
45
//// Public License along with this source; if not, download it   ////
46
//// from http://www.opencores.org/lgpl.shtml                     ////
47
////                                                              ////
48
//////////////////////////////////////////////////////////////////////
49
//
50
`include "timescale.v"
51
`include "usbhostslave_constants_h.v"
52
 
53
module sendPacketCheckPreamble (clk, preAmbleEnable, rst, sendPacketCPPID, sendPacketCPReady, sendPacketCPWEn, sendPacketPID, sendPacketRdy, sendPacketWEn);
54
input   clk;
55
input   preAmbleEnable;
56
input   rst;
57
input   [3:0] sendPacketCPPID;
58
input   sendPacketCPWEn;
59
input   sendPacketRdy;
60
output  sendPacketCPReady;
61
output  [3:0] sendPacketPID;
62
output  sendPacketWEn;
63
 
64
wire    clk;
65
wire    preAmbleEnable;
66
wire    rst;
67
wire    [3:0] sendPacketCPPID;
68
reg     sendPacketCPReady, next_sendPacketCPReady;
69
wire    sendPacketCPWEn;
70
reg     [3:0] sendPacketPID, next_sendPacketPID;
71
wire    sendPacketRdy;
72
reg     sendPacketWEn, next_sendPacketWEn;
73
 
74
// BINARY ENCODED state machine: sendPktCP
75
// State codes definitions:
76
`define SPC_WAIT_EN 4'b0000
77
`define START_SPC 4'b0001
78
`define CHK_PREAM 4'b0010
79
`define PREAM_PKT_SND_PREAM 4'b0011
80
`define PREAM_PKT_WAIT_RDY1 4'b0100
81
`define PREAM_PKT_PREAM_SENT 4'b0101
82
`define PREAM_PKT_SND_PID 4'b0110
83
`define PREAM_PKT_PID_SENT 4'b0111
84
`define REG_PKT_SEND_PID 4'b1000
85
`define REG_PKT_WAIT_RDY1 4'b1001
86
`define REG_PKT_WAIT_RDY 4'b1010
87
`define READY 4'b1011
88
`define PREAM_PKT_WAIT_RDY2 4'b1100
89
`define PREAM_PKT_WAIT_RDY3 4'b1101
90
 
91
reg [3:0] CurrState_sendPktCP;
92
reg [3:0] NextState_sendPktCP;
93
 
94
 
95
//--------------------------------------------------------------------
96
// Machine: sendPktCP
97
//--------------------------------------------------------------------
98
//----------------------------------
99
// Next State Logic (combinatorial)
100
//----------------------------------
101
always @ (sendPacketCPPID or sendPacketCPWEn or preAmbleEnable or sendPacketRdy or sendPacketCPReady or sendPacketWEn or sendPacketPID or CurrState_sendPktCP)
102
begin : sendPktCP_NextState
103
  NextState_sendPktCP <= CurrState_sendPktCP;
104
  // Set default values for outputs and signals
105
  next_sendPacketCPReady <= sendPacketCPReady;
106
  next_sendPacketWEn <= sendPacketWEn;
107
  next_sendPacketPID <= sendPacketPID;
108
  case (CurrState_sendPktCP)
109
    `SPC_WAIT_EN:
110
      if (sendPacketCPWEn == 1'b1)
111
      begin
112
        NextState_sendPktCP <= `CHK_PREAM;
113
        next_sendPacketCPReady <= 1'b0;
114
      end
115
    `START_SPC:
116
      NextState_sendPktCP <= `SPC_WAIT_EN;
117
    `CHK_PREAM:
118
      if (preAmbleEnable == 1'b1)
119
        NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY1;
120
      else
121
        NextState_sendPktCP <= `REG_PKT_WAIT_RDY1;
122
    `READY:
123
    begin
124
      next_sendPacketCPReady <= 1'b1;
125
      NextState_sendPktCP <= `SPC_WAIT_EN;
126
    end
127
    `PREAM_PKT_SND_PREAM:
128
    begin
129
      next_sendPacketWEn <= 1'b1;
130
      next_sendPacketPID <= `PREAMBLE;
131
      NextState_sendPktCP <= `PREAM_PKT_PREAM_SENT;
132
    end
133
    `PREAM_PKT_WAIT_RDY1:
134
      if (sendPacketRdy == 1'b1)
135
        NextState_sendPktCP <= `PREAM_PKT_SND_PREAM;
136
    `PREAM_PKT_PREAM_SENT:
137
    begin
138
      next_sendPacketWEn <= 1'b0;
139
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY2;
140
    end
141
    `PREAM_PKT_SND_PID:
142
    begin
143
      next_sendPacketWEn <= 1'b1;
144
      next_sendPacketPID <= sendPacketCPPID;
145
      NextState_sendPktCP <= `PREAM_PKT_PID_SENT;
146
    end
147
    `PREAM_PKT_PID_SENT:
148
    begin
149
      next_sendPacketWEn <= 1'b0;
150
      NextState_sendPktCP <= `PREAM_PKT_WAIT_RDY3;
151
    end
152
    `PREAM_PKT_WAIT_RDY2:
153
      if (sendPacketRdy == 1'b1)
154
        NextState_sendPktCP <= `PREAM_PKT_SND_PID;
155
    `PREAM_PKT_WAIT_RDY3:
156
      if (sendPacketRdy == 1'b1)
157
        NextState_sendPktCP <= `READY;
158
    `REG_PKT_SEND_PID:
159
    begin
160
      next_sendPacketWEn <= 1'b1;
161
      next_sendPacketPID <= sendPacketCPPID;
162
      NextState_sendPktCP <= `REG_PKT_WAIT_RDY;
163
    end
164
    `REG_PKT_WAIT_RDY1:
165
      if (sendPacketRdy == 1'b1)
166
        NextState_sendPktCP <= `REG_PKT_SEND_PID;
167
    `REG_PKT_WAIT_RDY:
168
    begin
169
      next_sendPacketWEn <= 1'b0;
170
      NextState_sendPktCP <= `READY;
171
    end
172
  endcase
173
end
174
 
175
//----------------------------------
176
// Current State Logic (sequential)
177
//----------------------------------
178
always @ (posedge clk)
179
begin : sendPktCP_CurrentState
180
  if (rst)
181
    CurrState_sendPktCP <= `START_SPC;
182
  else
183
    CurrState_sendPktCP <= NextState_sendPktCP;
184
end
185
 
186
//----------------------------------
187
// Registered outputs logic
188
//----------------------------------
189
always @ (posedge clk)
190
begin : sendPktCP_RegOutput
191
  if (rst)
192
  begin
193
    sendPacketWEn <= 1'b0;
194
    sendPacketPID <= 4'b0;
195
    sendPacketCPReady <= 1'b1;
196
  end
197
  else
198
  begin
199
    sendPacketWEn <= next_sendPacketWEn;
200
    sendPacketPID <= next_sendPacketPID;
201
    sendPacketCPReady <= next_sendPacketCPReady;
202
  end
203
end
204
 
205
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.