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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [writeUSBWireData.v] - Blame information for rev 862

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// writeUSBWireData.v                                           ////
////                                                              ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbhostslave_serialinterfaceengine_h.v"
 
`define BUFFER_FULL  3'b100
 
module writeUSBWireData (
  TxBitsIn,
  TxBitsOut,
   TxDataOutTick,
  TxCtrlIn,
  TxCtrlOut,
  USBWireRdy,
  USBWireWEn,
  TxWireActiveDrive,
  fullSpeedRate,
  clk,
  rst
   );
 
input   [1:0] TxBitsIn;
input   TxCtrlIn;
input   USBWireWEn;
input   clk;
input   fullSpeedRate;
input   rst;
output  [1:0] TxBitsOut;
output TxDataOutTick;
output  TxCtrlOut;
output  USBWireRdy;
output  TxWireActiveDrive;
 
wire    [1:0] TxBitsIn;
reg     [1:0] TxBitsOut;
reg     TxDataOutTick;
wire    TxCtrlIn;
reg     TxCtrlOut;
reg     USBWireRdy;
wire    USBWireWEn;
wire    clk;
wire    fullSpeedRate;
wire    rst;
reg     TxWireActiveDrive;
 
// local registers
reg  [2:0]buffer0;
reg  [2:0]buffer1;
reg  [2:0]buffer2;
reg  [2:0]buffer3;
reg  [2:0]bufferCnt;
reg  [1:0]bufferInIndex;
reg  [1:0]bufferOutIndex;
reg decBufferCnt;
reg  [4:0]i;
reg incBufferCnt;
reg fullSpeedTick;
reg lowSpeedTick;
 
// buffer in state machine state codes:
`define WAIT_BUFFER_NOT_FULL 2'b00
`define WAIT_WRITE_REQ 2'b01
`define CLR_INC_BUFFER_CNT 2'b10
 
// buffer output state machine state codes:
`define WAIT_BUFFER_FULL 2'b00
`define WAIT_LINE_WRITE 2'b01
`define LINE_WRITE 2'b10
 
reg [1:0] bufferInStMachCurrState;
reg [1:0] bufferOutStMachCurrState;
 
// buffer control
always @(posedge clk)
begin
  if (rst == 1'b1)
  begin
    bufferCnt <= 3'b000;
  end
  else
  begin
    if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)
      bufferCnt <= bufferCnt + 1'b1;
    else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)
      bufferCnt <= bufferCnt - 1'b1;
  end
end
 
 
//buffer input state machine 
always @(posedge clk) begin
  if (rst == 1'b1) begin
     incBufferCnt <= 1'b0;
    bufferInIndex <= 2'b00;
    buffer0 <= 3'b000;
    buffer1 <= 3'b000;
    buffer2 <= 3'b000;
    buffer3 <= 3'b000;
    USBWireRdy <= 1'b0;
    bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
  end
  else begin
    case (bufferInStMachCurrState)
      `WAIT_BUFFER_NOT_FULL:
      begin
        if (bufferCnt != `BUFFER_FULL)
        begin
          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
          USBWireRdy <= 1'b1;
        end
      end
      `WAIT_WRITE_REQ:
      begin
        if (USBWireWEn == 1'b1)
        begin
          incBufferCnt <= 1'b1;
          USBWireRdy <= 1'b0;
          bufferInIndex <= bufferInIndex + 1'b1;
          case (bufferInIndex)
            2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};
            2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};
            2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};
            2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};
          endcase
          bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
        end
      end
      `CLR_INC_BUFFER_CNT:
      begin
        incBufferCnt <= 1'b0;
        if (bufferCnt != (`BUFFER_FULL - 1'b1) )
        begin
          bufferInStMachCurrState <= `WAIT_WRITE_REQ;
          USBWireRdy <= 1'b1;
        end
        else begin
          bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
        end
      end
    endcase
  end
end
 
//increment counter used to generate USB bit rate
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    i <= 5'b00000;
    fullSpeedTick <= 1'b0;
    lowSpeedTick <= 1'b0;
  end
  else
  begin
    i <= i + 1'b1;
    if (i[1:0] == 2'b00)
      fullSpeedTick <= 1'b1;
    else
      fullSpeedTick <= 1'b0;
    if (i == 5'b00000)
      lowSpeedTick <= 1'b1;
    else
      lowSpeedTick <= 1'b0;
  end
end
 
//buffer output state machine
//buffer is constantly emptied at either
//the full or low speed rate
//if the buffer is empty, then the output is forced to tri-state
always @(posedge clk) begin
  if (rst == 1'b1)
  begin
    bufferOutIndex <= 2'b00;
    decBufferCnt <= 1'b0;
    TxBitsOut <= 2'b00;
    TxCtrlOut <= `TRI_STATE;
    TxDataOutTick <= 1'b0;
    bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
  end
  else
  begin
    case (bufferOutStMachCurrState)
      `WAIT_LINE_WRITE:
      begin
        if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) || (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )
        begin
          TxDataOutTick <= !TxDataOutTick;
          if (bufferCnt == 0) begin
            TxBitsOut <= 2'b00;
            TxCtrlOut <= `TRI_STATE;
          end
          else begin
            bufferOutStMachCurrState <= `LINE_WRITE;
            decBufferCnt <= 1'b1;
            bufferOutIndex <= bufferOutIndex + 1'b1;
            case (bufferOutIndex)
              2'b00 :
            begin
              TxBitsOut <= buffer0[2:1];
              TxCtrlOut <= buffer0[0];
            end
            2'b01 :
            begin
              TxBitsOut <= buffer1[2:1];
              TxCtrlOut <= buffer1[0];
            end
            2'b10 :
            begin
              TxBitsOut <= buffer2[2:1];
              TxCtrlOut <= buffer2[0];
            end
            2'b11 :
            begin
              TxBitsOut <= buffer3[2:1];
              TxCtrlOut <= buffer3[0];
            end
            endcase
          end
        end
      end
      `LINE_WRITE:
      begin
        decBufferCnt <= 1'b0;
        bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
      end
    endcase
  end
end
 
// control 'TxWireActiveDrive' 
always @(TxCtrlOut)
begin
  if (TxCtrlOut == `DRIVE)
    TxWireActiveDrive <= 1'b1;
  else
    TxWireActiveDrive <= 1'b0;
end
 
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [usbhostslave/] [writeUSBWireData.v] - Blame information for rev 862

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// writeUSBWireData.v ////`
4			`//// ////`
5			`//// This file is part of the usbhostslave opencores effort.`
6			`//// <http://www.opencores.org/cores//> ////`
7			`//// ////`
8			`//// Module Description: ////`
9			`////`
10			`//// ////`
11			`//// To Do: ////`
12			`////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Steve Fielding, sfielding@base2designs.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from <http://www.opencores.org/lgpl.shtml> ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`include "timescale.v"
45			`include "usbhostslave_serialinterfaceengine_h.v"
46
47			`define BUFFER_FULL 3'b100
48
49			`module writeUSBWireData (`
50			`TxBitsIn,`
51			`TxBitsOut,`
52			`TxDataOutTick,`
53			`TxCtrlIn,`
54			`TxCtrlOut,`
55			`USBWireRdy,`
56			`USBWireWEn,`
57			`TxWireActiveDrive,`
58			`fullSpeedRate,`
59			`clk,`
60			`rst`
61			`);`
62
63			`input [1:0] TxBitsIn;`
64			`input TxCtrlIn;`
65			`input USBWireWEn;`
66			`input clk;`
67			`input fullSpeedRate;`
68			`input rst;`
69			`output [1:0] TxBitsOut;`
70			`output TxDataOutTick;`
71			`output TxCtrlOut;`
72			`output USBWireRdy;`
73			`output TxWireActiveDrive;`
74
75			`wire [1:0] TxBitsIn;`
76			`reg [1:0] TxBitsOut;`
77			`reg TxDataOutTick;`
78			`wire TxCtrlIn;`
79			`reg TxCtrlOut;`
80			`reg USBWireRdy;`
81			`wire USBWireWEn;`
82			`wire clk;`
83			`wire fullSpeedRate;`
84			`wire rst;`
85			`reg TxWireActiveDrive;`
86
87			`// local registers`
88			`reg [2:0]buffer0;`
89			`reg [2:0]buffer1;`
90			`reg [2:0]buffer2;`
91			`reg [2:0]buffer3;`
92			`reg [2:0]bufferCnt;`
93			`reg [1:0]bufferInIndex;`
94			`reg [1:0]bufferOutIndex;`
95			`reg decBufferCnt;`
96			`reg [4:0]i;`
97			`reg incBufferCnt;`
98			`reg fullSpeedTick;`
99			`reg lowSpeedTick;`
100
101			`// buffer in state machine state codes:`
102			`define WAIT_BUFFER_NOT_FULL 2'b00
103			`define WAIT_WRITE_REQ 2'b01
104			`define CLR_INC_BUFFER_CNT 2'b10
105
106			`// buffer output state machine state codes:`
107			`define WAIT_BUFFER_FULL 2'b00
108			`define WAIT_LINE_WRITE 2'b01
109			`define LINE_WRITE 2'b10
110
111			`reg [1:0] bufferInStMachCurrState;`
112			`reg [1:0] bufferOutStMachCurrState;`
113
114			`// buffer control`
115			`always @(posedge clk)`
116			`begin`
117			`if (rst == 1'b1)`
118			`begin`
119			`bufferCnt <= 3'b000;`
120			`end`
121			`else`
122			`begin`
123			`if (incBufferCnt == 1'b1 && decBufferCnt == 1'b0)`
124			`bufferCnt <= bufferCnt + 1'b1;`
125			`else if (incBufferCnt == 1'b0 && decBufferCnt == 1'b1)`
126			`bufferCnt <= bufferCnt - 1'b1;`
127			`end`
128			`end`
129
130
131			`//buffer input state machine`
132			`always @(posedge clk) begin`
133			`if (rst == 1'b1) begin`
134			`incBufferCnt <= 1'b0;`
135			`bufferInIndex <= 2'b00;`
136			`buffer0 <= 3'b000;`
137			`buffer1 <= 3'b000;`
138			`buffer2 <= 3'b000;`
139			`buffer3 <= 3'b000;`
140			`USBWireRdy <= 1'b0;`
141			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
142			`end`
143			`else begin`
144			`case (bufferInStMachCurrState)`
145			`WAIT_BUFFER_NOT_FULL:
146			`begin`
147			if (bufferCnt != `BUFFER_FULL)
148			`begin`
149			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
150			`USBWireRdy <= 1'b1;`
151			`end`
152			`end`
153			`WAIT_WRITE_REQ:
154			`begin`
155			`if (USBWireWEn == 1'b1)`
156			`begin`
157			`incBufferCnt <= 1'b1;`
158			`USBWireRdy <= 1'b0;`
159			`bufferInIndex <= bufferInIndex + 1'b1;`
160			`case (bufferInIndex)`
161			`2'b00 : buffer0 <= {TxBitsIn, TxCtrlIn};`
162			`2'b01 : buffer1 <= {TxBitsIn, TxCtrlIn};`
163			`2'b10 : buffer2 <= {TxBitsIn, TxCtrlIn};`
164			`2'b11 : buffer3 <= {TxBitsIn, TxCtrlIn};`
165			`endcase`
166			bufferInStMachCurrState <= `CLR_INC_BUFFER_CNT;
167			`end`
168			`end`
169			`CLR_INC_BUFFER_CNT:
170			`begin`
171			`incBufferCnt <= 1'b0;`
172			if (bufferCnt != (`BUFFER_FULL - 1'b1) )
173			`begin`
174			bufferInStMachCurrState <= `WAIT_WRITE_REQ;
175			`USBWireRdy <= 1'b1;`
176			`end`
177			`else begin`
178			bufferInStMachCurrState <= `WAIT_BUFFER_NOT_FULL;
179			`end`
180			`end`
181			`endcase`
182			`end`
183			`end`
184
185			`//increment counter used to generate USB bit rate`
186			`always @(posedge clk) begin`
187			`if (rst == 1'b1)`
188			`begin`
189			`i <= 5'b00000;`
190			`fullSpeedTick <= 1'b0;`
191			`lowSpeedTick <= 1'b0;`
192			`end`
193			`else`
194			`begin`
195			`i <= i + 1'b1;`
196			`if (i[1:0] == 2'b00)`
197			`fullSpeedTick <= 1'b1;`
198			`else`
199			`fullSpeedTick <= 1'b0;`
200			`if (i == 5'b00000)`
201			`lowSpeedTick <= 1'b1;`
202			`else`
203			`lowSpeedTick <= 1'b0;`
204			`end`
205			`end`
206
207			`//buffer output state machine`
208			`//buffer is constantly emptied at either`
209			`//the full or low speed rate`
210			`//if the buffer is empty, then the output is forced to tri-state`
211			`always @(posedge clk) begin`
212			`if (rst == 1'b1)`
213			`begin`
214			`bufferOutIndex <= 2'b00;`
215			`decBufferCnt <= 1'b0;`
216			`TxBitsOut <= 2'b00;`
217			TxCtrlOut <= `TRI_STATE;
218			`TxDataOutTick <= 1'b0;`
219			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
220			`end`
221			`else`
222			`begin`
223			`case (bufferOutStMachCurrState)`
224			`WAIT_LINE_WRITE:
225			`begin`
226			`if ((fullSpeedRate == 1'b1 && fullSpeedTick == 1'b1) \|\| (fullSpeedRate == 1'b0 && lowSpeedTick == 1'b1) )`
227			`begin`
228			`TxDataOutTick <= !TxDataOutTick;`
229			`if (bufferCnt == 0) begin`
230			`TxBitsOut <= 2'b00;`
231			TxCtrlOut <= `TRI_STATE;
232			`end`
233			`else begin`
234			bufferOutStMachCurrState <= `LINE_WRITE;
235			`decBufferCnt <= 1'b1;`
236			`bufferOutIndex <= bufferOutIndex + 1'b1;`
237			`case (bufferOutIndex)`
238			`2'b00 :`
239			`begin`
240			`TxBitsOut <= buffer0[2:1];`
241			`TxCtrlOut <= buffer0[0];`
242			`end`
243			`2'b01 :`
244			`begin`
245			`TxBitsOut <= buffer1[2:1];`
246			`TxCtrlOut <= buffer1[0];`
247			`end`
248			`2'b10 :`
249			`begin`
250			`TxBitsOut <= buffer2[2:1];`
251			`TxCtrlOut <= buffer2[0];`
252			`end`
253			`2'b11 :`
254			`begin`
255			`TxBitsOut <= buffer3[2:1];`
256			`TxCtrlOut <= buffer3[0];`
257			`end`
258			`endcase`
259			`end`
260			`end`
261			`end`
262			`LINE_WRITE:
263			`begin`
264			`decBufferCnt <= 1'b0;`
265			bufferOutStMachCurrState <= `WAIT_LINE_WRITE;
266			`end`
267			`endcase`
268			`end`
269			`end`
270
271			`// control 'TxWireActiveDrive'`
272			`always @(TxCtrlOut)`
273			`begin`
274			if (TxCtrlOut == `DRIVE)
275			`TxWireActiveDrive <= 1'b1;`
276			`else`
277			`TxWireActiveDrive <= 1'b0;`
278			`end`
279
280
281			`endmodule`