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351 |
julius |
// Switch network arbiter
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// Wishbone B3 signals compliant
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`define NUM_MASTERS_4
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`define NUM_SLAVES_5
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`define WATCHDOG_TIMER
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`ifdef NUM_MASTERS_6
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`define NUM_MASTERS 6
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`define WBM5
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`define WBM4
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`define WBM3
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`define WBM2
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`define WBM1
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`else
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`ifdef NUM_MASTERS_5
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`define NUM_MASTERS 5
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`define WBM4
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`define WBM3
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`define WBM2
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`define WBM1
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`else
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`ifdef NUM_MASTERS_4
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`define NUM_MASTERS 4
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`define WBM3
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`define WBM2
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`define WBM1
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`else
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`ifdef NUM_MASTERS_3
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`define NUM_MASTERS 3
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`define WBM2
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`define WBM1
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`else
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`ifdef NUM_MASTERS_2
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`define NUM_MASTERS 2
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`define WBM1
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`else
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`define NUM_MASTERS 1
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`endif
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`endif // !`ifdef NUM_MASTERS_3
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`endif // !`ifdef NUM_MASTERS_4
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`endif // !`ifdef NUM_MASTERS_5
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`endif // !`ifdef NUM_MASTERS_6
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`ifdef NUM_SLAVES_8
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`define NUM_SLAVES 8
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`define WBS7
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`define WBS6
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`define WBS5
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`define WBS4
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`define WBS3
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`define WBS2
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`define WBS1
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`else
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`ifdef NUM_SLAVES_7
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`define NUM_SLAVES 7
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`define WBS6
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`define WBS5
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`define WBS4
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`define WBS3
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`define WBS2
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`define WBS1
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`else
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`ifdef NUM_SLAVES_6
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`define NUM_SLAVES 6
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`define WBS5
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`define WBS4
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`define WBS3
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`define WBS2
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`define WBS1
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`else
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`ifdef NUM_SLAVES_5
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`define NUM_SLAVES 5
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`define WBS4
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`define WBS3
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`define WBS2
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`define WBS1
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`else
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`ifdef NUM_SLAVES_4
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`define NUM_SLAVES 4
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`define WBS3
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`define WBS2
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`define WBS1
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`else
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`ifdef NUM_SLAVES_3
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`define NUM_SLAVES 3
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`define WBS2
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`define WBS1
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`else
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`ifdef NUM_SLAVES_2
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`define NUM_SLAVES 2
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`define WBS1
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`else
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`define NUM_SLAVES 1
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`endif
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`endif
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`endif // !`ifdef NUM_SLAVES_4
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`endif // !`ifdef NUM_SLAVES_5
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`endif // !`ifdef NUM_SLAVES_6
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`endif // !`ifdef NUM_SLAVES_7
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`endif // !`ifdef NUM_SLAVES_8
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module wb_switch_b3
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(
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// Master ports
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wbm0_adr_o, wbm0_bte_o, wbm0_cti_o, wbm0_cyc_o, wbm0_dat_o, wbm0_sel_o,
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wbm0_stb_o, wbm0_we_o, wbm0_ack_i, wbm0_err_i, wbm0_rty_i, wbm0_dat_i,
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`ifdef WBM1
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wbm1_adr_o, wbm1_bte_o, wbm1_cti_o, wbm1_cyc_o, wbm1_dat_o, wbm1_sel_o,
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wbm1_stb_o, wbm1_we_o, wbm1_ack_i, wbm1_err_i, wbm1_rty_i, wbm1_dat_i,
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`endif
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`ifdef WBM2
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wbm2_adr_o, wbm2_bte_o, wbm2_cti_o, wbm2_cyc_o, wbm2_dat_o, wbm2_sel_o,
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wbm2_stb_o, wbm2_we_o, wbm2_ack_i, wbm2_err_i, wbm2_rty_i, wbm2_dat_i,
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`endif
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`ifdef WBM3
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wbm3_adr_o, wbm3_bte_o, wbm3_cti_o, wbm3_cyc_o, wbm3_dat_o, wbm3_sel_o,
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wbm3_stb_o, wbm3_we_o, wbm3_ack_i, wbm3_err_i, wbm3_rty_i, wbm3_dat_i,
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`endif
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`ifdef WBM4
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wbm4_adr_o, wbm4_bte_o, wbm4_cti_o, wbm4_cyc_o, wbm4_dat_o, wbm4_sel_o,
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wbm4_stb_o, wbm4_we_o, wbm4_ack_i, wbm4_err_i, wbm4_rty_i, wbm4_dat_i,
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`endif
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`ifdef WBM5
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wbm5_adr_o, wbm5_bte_o, wbm5_cti_o, wbm5_cyc_o, wbm5_dat_o, wbm5_sel_o,
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wbm5_stb_o, wbm5_we_o, wbm5_ack_i, wbm5_err_i, wbm5_rty_i, wbm5_dat_i,
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`endif
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// Slave ports
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wbs0_adr_i, wbs0_bte_i, wbs0_cti_i, wbs0_cyc_i, wbs0_dat_i, wbs0_sel_i,
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wbs0_stb_i, wbs0_we_i, wbs0_ack_o, wbs0_err_o, wbs0_rty_o, wbs0_dat_o,
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`ifdef WBS1
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wbs1_adr_i, wbs1_bte_i, wbs1_cti_i, wbs1_cyc_i, wbs1_dat_i, wbs1_sel_i,
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wbs1_stb_i, wbs1_we_i, wbs1_ack_o, wbs1_err_o, wbs1_rty_o, wbs1_dat_o,
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`endif
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`ifdef WBS2
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wbs2_adr_i, wbs2_bte_i, wbs2_cti_i, wbs2_cyc_i, wbs2_dat_i, wbs2_sel_i,
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wbs2_stb_i, wbs2_we_i, wbs2_ack_o, wbs2_err_o, wbs2_rty_o, wbs2_dat_o,
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`endif
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`ifdef WBS3
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wbs3_adr_i, wbs3_bte_i, wbs3_cti_i, wbs3_cyc_i, wbs3_dat_i, wbs3_sel_i,
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wbs3_stb_i, wbs3_we_i, wbs3_ack_o, wbs3_err_o, wbs3_rty_o, wbs3_dat_o,
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`endif
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`ifdef WBS4
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wbs4_adr_i, wbs4_bte_i, wbs4_cti_i, wbs4_cyc_i, wbs4_dat_i, wbs4_sel_i,
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wbs4_stb_i, wbs4_we_i, wbs4_ack_o, wbs4_err_o, wbs4_rty_o, wbs4_dat_o,
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`endif
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`ifdef WBS5
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wbs5_adr_i, wbs5_bte_i, wbs5_cti_i, wbs5_cyc_i, wbs5_dat_i, wbs5_sel_i,
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wbs5_stb_i, wbs5_we_i, wbs5_ack_o, wbs5_err_o, wbs5_rty_o, wbs5_dat_o,
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`endif
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`ifdef WBS6
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wbs6_adr_i, wbs6_bte_i, wbs6_cti_i, wbs6_cyc_i, wbs6_dat_i, wbs6_sel_i,
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wbs6_stb_i, wbs6_we_i, wbs6_ack_o, wbs6_err_o, wbs6_rty_o, wbs6_dat_o,
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`endif
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`ifdef WBS7
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wbs7_adr_i, wbs7_bte_i, wbs7_cti_i, wbs7_cyc_i, wbs7_dat_i, wbs7_sel_i,
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wbs7_stb_i, wbs7_we_i, wbs7_ack_o, wbs7_err_o, wbs7_rty_o, wbs7_dat_o,
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`endif
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// Clocks, resets
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wb_clk, wb_rst
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);
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// Data and address width parameters
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parameter dw = 32;
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parameter aw = 32;
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input [aw-1:0] wbm0_adr_o;input [1:0] wbm0_bte_o;input [2:0] wbm0_cti_o;input wbm0_cyc_o;input [dw-1:0] wbm0_dat_o;input [3:0] wbm0_sel_o;input wbm0_stb_o;input wbm0_we_o;output wbm0_ack_i;output wbm0_err_i;output wbm0_rty_i;output [dw-1:0] wbm0_dat_i;
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`ifdef WBM1
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input [aw-1:0] wbm1_adr_o;input [1:0] wbm1_bte_o;input [2:0] wbm1_cti_o;input wbm1_cyc_o;input [dw-1:0] wbm1_dat_o;input [3:0] wbm1_sel_o;input wbm1_stb_o;input wbm1_we_o;output wbm1_ack_i;output wbm1_err_i;output wbm1_rty_i;output [dw-1:0] wbm1_dat_i;
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`endif
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`ifdef WBM2
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input [aw-1:0] wbm2_adr_o;input [1:0] wbm2_bte_o;input [2:0] wbm2_cti_o;input wbm2_cyc_o;input [dw-1:0] wbm2_dat_o;input [3:0] wbm2_sel_o;input wbm2_stb_o;input wbm2_we_o;output wbm2_ack_i;output wbm2_err_i;output wbm2_rty_i;output [dw-1:0] wbm2_dat_i;
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`endif
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`ifdef WBM3
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input [aw-1:0] wbm3_adr_o;input [1:0] wbm3_bte_o;input [2:0] wbm3_cti_o;input wbm3_cyc_o;input [dw-1:0] wbm3_dat_o;input [3:0] wbm3_sel_o;input wbm3_stb_o;input wbm3_we_o;output wbm3_ack_i;output wbm3_err_i;output wbm3_rty_i;output [dw-1:0] wbm3_dat_i;
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`endif
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`ifdef WBM4
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input [aw-1:0] wbm4_adr_o;input [1:0] wbm4_bte_o;input [2:0] wbm4_cti_o;input wbm4_cyc_o;input [dw-1:0] wbm4_dat_o;input [3:0] wbm4_sel_o;input wbm4_stb_o;input wbm4_we_o;output wbm4_ack_i;output wbm4_err_i;output wbm4_rty_i;output [dw-1:0] wbm4_dat_i;
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`endif
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| 184 |
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`ifdef WBM5
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input [aw-1:0] wbm5_adr_o;input [1:0] wbm5_bte_o;input [2:0] wbm5_cti_o;input wbm5_cyc_o;input [dw-1:0] wbm5_dat_o;input [3:0] wbm5_sel_o;input wbm5_stb_o;input wbm5_we_o;output wbm5_ack_i;output wbm5_err_i;output wbm5_rty_i;output [dw-1:0] wbm5_dat_i;
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`endif
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output [aw-1:0] wbs0_adr_i;output [1:0] wbs0_bte_i;output [2:0] wbs0_cti_i;output wbs0_cyc_i;output [dw-1:0] wbs0_dat_i;output [3:0] wbs0_sel_i;output wbs0_stb_i;output wbs0_we_i;input wbs0_ack_o;input wbs0_err_o;input wbs0_rty_o;input [dw-1:0] wbs0_dat_o;
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| 190 |
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`ifdef WBS1
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output [aw-1:0] wbs1_adr_i;output [1:0] wbs1_bte_i;output [2:0] wbs1_cti_i;output wbs1_cyc_i;output [dw-1:0] wbs1_dat_i;output [3:0] wbs1_sel_i;output wbs1_stb_i;output wbs1_we_i;input wbs1_ack_o;input wbs1_err_o;input wbs1_rty_o;input [dw-1:0] wbs1_dat_o;
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| 192 |
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`endif
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| 193 |
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`ifdef WBS2
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| 194 |
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output [aw-1:0] wbs2_adr_i;output [1:0] wbs2_bte_i;output [2:0] wbs2_cti_i;output wbs2_cyc_i;output [dw-1:0] wbs2_dat_i;output [3:0] wbs2_sel_i;output wbs2_stb_i;output wbs2_we_i;input wbs2_ack_o;input wbs2_err_o;input wbs2_rty_o;input [dw-1:0] wbs2_dat_o;
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| 195 |
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`endif
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| 196 |
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`ifdef WBS3
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output [aw-1:0] wbs3_adr_i;output [1:0] wbs3_bte_i;output [2:0] wbs3_cti_i;output wbs3_cyc_i;output [dw-1:0] wbs3_dat_i;output [3:0] wbs3_sel_i;output wbs3_stb_i;output wbs3_we_i;input wbs3_ack_o;input wbs3_err_o;input wbs3_rty_o;input [dw-1:0] wbs3_dat_o;
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| 198 |
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`endif
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| 199 |
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`ifdef WBS4
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| 200 |
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output [aw-1:0] wbs4_adr_i;output [1:0] wbs4_bte_i;output [2:0] wbs4_cti_i;output wbs4_cyc_i;output [dw-1:0] wbs4_dat_i;output [3:0] wbs4_sel_i;output wbs4_stb_i;output wbs4_we_i;input wbs4_ack_o;input wbs4_err_o;input wbs4_rty_o;input [dw-1:0] wbs4_dat_o;
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| 201 |
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`endif
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| 202 |
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`ifdef WBS5
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| 203 |
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output [aw-1:0] wbs5_adr_i;output [1:0] wbs5_bte_i;output [2:0] wbs5_cti_i;output wbs5_cyc_i;output [dw-1:0] wbs5_dat_i;output [3:0] wbs5_sel_i;output wbs5_stb_i;output wbs5_we_i;input wbs5_ack_o;input wbs5_err_o;input wbs5_rty_o;input [dw-1:0] wbs5_dat_o;
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| 204 |
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`endif
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| 205 |
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`ifdef WBS6
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| 206 |
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output [aw-1:0] wbs6_adr_i;output [1:0] wbs6_bte_i;output [2:0] wbs6_cti_i;output wbs6_cyc_i;output [dw-1:0] wbs6_dat_i;output [3:0] wbs6_sel_i;output wbs6_stb_i;output wbs6_we_i;input wbs6_ack_o;input wbs6_err_o;input wbs6_rty_o;input [dw-1:0] wbs6_dat_o;
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| 207 |
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`endif
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| 208 |
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`ifdef WBS7
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| 209 |
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output [aw-1:0] wbs7_adr_i;output [1:0] wbs7_bte_i;output [2:0] wbs7_cti_i;output wbs7_cyc_i;output [dw-1:0] wbs7_dat_i;output [3:0] wbs7_sel_i;output wbs7_stb_i;output wbs7_we_i;input wbs7_ack_o;input wbs7_err_o;input wbs7_rty_o;input [dw-1:0] wbs7_dat_o;
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| 210 |
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`endif
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| 211 |
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| 212 |
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input wb_clk, wb_rst;
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| 213 |
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| 214 |
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// have a master select for each slave, meaning multiple slaves could be driven at a time
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wire [`NUM_MASTERS-1:0] wbs0_master_sel;
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| 217 |
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wire wbs0_master_sel_new;
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| 218 |
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`ifdef WBS1
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| 219 |
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wire [`NUM_MASTERS-1:0] wbs1_master_sel;
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| 220 |
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wire wbs1_master_sel_new;
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| 221 |
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`endif
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| 222 |
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`ifdef WBS2
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| 223 |
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wire [`NUM_MASTERS-1:0] wbs2_master_sel;
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| 224 |
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wire wbs2_master_sel_new;
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| 225 |
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`endif
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| 226 |
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`ifdef WBS3
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| 227 |
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wire [`NUM_MASTERS-1:0] wbs3_master_sel;
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| 228 |
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wire wbs3_master_sel_new;
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| 229 |
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`endif
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| 230 |
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`ifdef WBS4
|
| 231 |
|
|
wire [`NUM_MASTERS-1:0] wbs4_master_sel;
|
| 232 |
|
|
wire wbs4_master_sel_new;
|
| 233 |
|
|
`endif
|
| 234 |
|
|
`ifdef WBS5
|
| 235 |
|
|
wire [`NUM_MASTERS-1:0] wbs5_master_sel;
|
| 236 |
|
|
wire wbs5_master_sel_new;
|
| 237 |
|
|
`endif
|
| 238 |
|
|
`ifdef WBS6
|
| 239 |
|
|
wire [`NUM_MASTERS-1:0] wbs6_master_sel;
|
| 240 |
|
|
wire wbs6_master_sel_new;
|
| 241 |
|
|
`endif
|
| 242 |
|
|
`ifdef WBS7
|
| 243 |
|
|
wire [`NUM_MASTERS-1:0] wbs7_master_sel;
|
| 244 |
|
|
wire wbs7_master_sel_new;
|
| 245 |
|
|
`endif
|
| 246 |
|
|
|
| 247 |
|
|
wire [`NUM_SLAVES-1:0] wbm0_slave_sel;
|
| 248 |
|
|
`ifdef WBM1
|
| 249 |
|
|
wire [`NUM_SLAVES-1:0] wbm1_slave_sel;
|
| 250 |
|
|
`endif
|
| 251 |
|
|
`ifdef WBM2
|
| 252 |
|
|
wire [`NUM_SLAVES-1:0] wbm2_slave_sel;
|
| 253 |
|
|
`endif
|
| 254 |
|
|
`ifdef WBM3
|
| 255 |
|
|
wire [`NUM_SLAVES-1:0] wbm3_slave_sel;
|
| 256 |
|
|
`endif
|
| 257 |
|
|
`ifdef WBM4
|
| 258 |
|
|
wire [`NUM_SLAVES-1:0] wbm4_slave_sel;
|
| 259 |
|
|
`endif
|
| 260 |
|
|
`ifdef WBM5
|
| 261 |
|
|
wire [`NUM_SLAVES-1:0] wbm5_slave_sel;
|
| 262 |
|
|
`endif
|
| 263 |
|
|
|
| 264 |
|
|
// Should probably be def-param'd outside
|
| 265 |
|
|
parameter slave0_sel_width = -1;
|
| 266 |
|
|
parameter slave0_sel_addr = 4'hx;
|
| 267 |
|
|
|
| 268 |
|
|
parameter slave1_sel_width = -1;
|
| 269 |
|
|
parameter slave1_sel_addr = 4'hx;
|
| 270 |
|
|
|
| 271 |
|
|
parameter slave2_sel_width = -1;
|
| 272 |
|
|
parameter slave2_sel_addr = 8'hxx;
|
| 273 |
|
|
|
| 274 |
|
|
parameter slave3_sel_width = -1;
|
| 275 |
|
|
parameter slave3_sel_addr = 8'hxx;
|
| 276 |
|
|
|
| 277 |
|
|
parameter slave4_sel_width = -1;
|
| 278 |
|
|
parameter slave4_sel_addr = 8'hxx;
|
| 279 |
|
|
|
| 280 |
|
|
parameter slave5_sel_width = -1;
|
| 281 |
|
|
parameter slave5_sel_addr = 8'hxx;
|
| 282 |
|
|
|
| 283 |
|
|
parameter slave6_sel_width = -1;
|
| 284 |
|
|
parameter slave6_sel_addr = 8'hxx;
|
| 285 |
|
|
|
| 286 |
|
|
parameter slave7_sel_width = -1;
|
| 287 |
|
|
parameter slave7_sel_addr = 8'hxx;
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 292 |
|
|
// Slave Select logic //
|
| 293 |
|
|
///////////////////////////////////////////////////////////////////////////
|
| 294 |
|
|
|
| 295 |
|
|
// Slave select logic, for each master
|
| 296 |
|
|
wb_b3_switch_slave_sel slave_sel0
|
| 297 |
|
|
(
|
| 298 |
|
|
// Outputs
|
| 299 |
|
|
.wbs_master_sel (wbs0_master_sel),
|
| 300 |
|
|
.wbs_master_sel_new (wbs0_master_sel_new),
|
| 301 |
|
|
// Inputs
|
| 302 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 303 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 304 |
|
|
`ifdef WBM1
|
| 305 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 306 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 307 |
|
|
`endif
|
| 308 |
|
|
`ifdef WBM2
|
| 309 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 310 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 311 |
|
|
`endif
|
| 312 |
|
|
`ifdef WBM3
|
| 313 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 314 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 315 |
|
|
`endif
|
| 316 |
|
|
`ifdef WBM4
|
| 317 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 318 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 319 |
|
|
`endif
|
| 320 |
|
|
`ifdef WBM5
|
| 321 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 322 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 323 |
|
|
`endif
|
| 324 |
|
|
|
| 325 |
|
|
.wb_clk (wb_clk),
|
| 326 |
|
|
.wb_rst (wb_rst));
|
| 327 |
|
|
|
| 328 |
|
|
defparam slave_sel0.num_masters = `NUM_MASTERS;
|
| 329 |
|
|
defparam slave_sel0.slave_sel_bit_width = slave0_sel_width;
|
| 330 |
|
|
defparam slave_sel0.slave_addr = slave0_sel_addr;
|
| 331 |
|
|
|
| 332 |
|
|
|
| 333 |
|
|
`ifdef WBS1
|
| 334 |
|
|
// Slave selec logic, for each master
|
| 335 |
|
|
wb_b3_switch_slave_sel slave_sel1
|
| 336 |
|
|
(
|
| 337 |
|
|
// Outputs
|
| 338 |
|
|
.wbs_master_sel (wbs1_master_sel),
|
| 339 |
|
|
.wbs_master_sel_new (wbs1_master_sel_new),
|
| 340 |
|
|
// Inputs
|
| 341 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 342 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 343 |
|
|
`ifdef WBM1
|
| 344 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 345 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 346 |
|
|
`endif
|
| 347 |
|
|
`ifdef WBM2
|
| 348 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 349 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 350 |
|
|
`endif
|
| 351 |
|
|
`ifdef WBM3
|
| 352 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 353 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 354 |
|
|
`endif
|
| 355 |
|
|
`ifdef WBM4
|
| 356 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 357 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 358 |
|
|
`endif
|
| 359 |
|
|
`ifdef WBM5
|
| 360 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 361 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 362 |
|
|
`endif
|
| 363 |
|
|
|
| 364 |
|
|
.wb_clk (wb_clk),
|
| 365 |
|
|
.wb_rst (wb_rst));
|
| 366 |
|
|
|
| 367 |
|
|
defparam slave_sel1.num_masters = `NUM_MASTERS;
|
| 368 |
|
|
defparam slave_sel1.slave_sel_bit_width = slave1_sel_width;
|
| 369 |
|
|
defparam slave_sel1.slave_addr = slave1_sel_addr;
|
| 370 |
|
|
|
| 371 |
|
|
`endif // `ifdef WBS1
|
| 372 |
|
|
|
| 373 |
|
|
|
| 374 |
|
|
`ifdef WBS2
|
| 375 |
|
|
// Slave selec logic, for each master
|
| 376 |
|
|
wb_b3_switch_slave_sel slave_sel2
|
| 377 |
|
|
(
|
| 378 |
|
|
// Outputs
|
| 379 |
|
|
.wbs_master_sel (wbs2_master_sel),
|
| 380 |
|
|
.wbs_master_sel_new (wbs2_master_sel_new),
|
| 381 |
|
|
// Inputs
|
| 382 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 383 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 384 |
|
|
`ifdef WBM1
|
| 385 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 386 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 387 |
|
|
`endif
|
| 388 |
|
|
`ifdef WBM2
|
| 389 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 390 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 391 |
|
|
`endif
|
| 392 |
|
|
`ifdef WBM3
|
| 393 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 394 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 395 |
|
|
`endif
|
| 396 |
|
|
`ifdef WBM4
|
| 397 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 398 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 399 |
|
|
`endif
|
| 400 |
|
|
`ifdef WBM5
|
| 401 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 402 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 403 |
|
|
`endif
|
| 404 |
|
|
.wb_clk (wb_clk),
|
| 405 |
|
|
.wb_rst (wb_rst));
|
| 406 |
|
|
|
| 407 |
|
|
defparam slave_sel2.num_masters = `NUM_MASTERS;
|
| 408 |
|
|
defparam slave_sel2.slave_sel_bit_width = slave2_sel_width;
|
| 409 |
|
|
defparam slave_sel2.slave_addr = slave2_sel_addr;
|
| 410 |
|
|
|
| 411 |
|
|
`endif // `ifdef WBS2
|
| 412 |
|
|
|
| 413 |
|
|
`ifdef WBS3
|
| 414 |
|
|
// Slave selec logic, for each master
|
| 415 |
|
|
wb_b3_switch_slave_sel slave_sel3
|
| 416 |
|
|
(
|
| 417 |
|
|
// Outputs
|
| 418 |
|
|
.wbs_master_sel (wbs3_master_sel),
|
| 419 |
|
|
.wbs_master_sel_new (wbs3_master_sel_new),
|
| 420 |
|
|
// Inputs
|
| 421 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 422 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 423 |
|
|
`ifdef WBM1
|
| 424 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 425 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 426 |
|
|
`endif
|
| 427 |
|
|
`ifdef WBM2
|
| 428 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 429 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 430 |
|
|
`endif
|
| 431 |
|
|
`ifdef WBM3
|
| 432 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 433 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 434 |
|
|
`endif
|
| 435 |
|
|
`ifdef WBM4
|
| 436 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 437 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 438 |
|
|
`endif
|
| 439 |
|
|
`ifdef WBM5
|
| 440 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 441 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 442 |
|
|
`endif
|
| 443 |
|
|
|
| 444 |
|
|
.wb_clk (wb_clk),
|
| 445 |
|
|
.wb_rst (wb_rst));
|
| 446 |
|
|
|
| 447 |
|
|
defparam slave_sel3.num_masters = `NUM_MASTERS;
|
| 448 |
|
|
defparam slave_sel3.slave_sel_bit_width = slave3_sel_width;
|
| 449 |
|
|
defparam slave_sel3.slave_addr = slave3_sel_addr;
|
| 450 |
|
|
|
| 451 |
|
|
`endif // `ifdef WBS3
|
| 452 |
|
|
|
| 453 |
|
|
`ifdef WBS4
|
| 454 |
|
|
// Slave selec logic, for each master
|
| 455 |
|
|
wb_b3_switch_slave_sel slave_sel4
|
| 456 |
|
|
(
|
| 457 |
|
|
// Outputs
|
| 458 |
|
|
.wbs_master_sel (wbs4_master_sel),
|
| 459 |
|
|
.wbs_master_sel_new (wbs4_master_sel_new),
|
| 460 |
|
|
// Inputs
|
| 461 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 462 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 463 |
|
|
`ifdef WBM1
|
| 464 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 465 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 466 |
|
|
`endif
|
| 467 |
|
|
`ifdef WBM2
|
| 468 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 469 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 470 |
|
|
`endif
|
| 471 |
|
|
`ifdef WBM3
|
| 472 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 473 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 474 |
|
|
`endif
|
| 475 |
|
|
`ifdef WBM4
|
| 476 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 477 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 478 |
|
|
`endif
|
| 479 |
|
|
`ifdef WBM5
|
| 480 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 481 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 482 |
|
|
`endif
|
| 483 |
|
|
|
| 484 |
|
|
.wb_clk (wb_clk),
|
| 485 |
|
|
.wb_rst (wb_rst));
|
| 486 |
|
|
|
| 487 |
|
|
defparam slave_sel4.num_masters = `NUM_MASTERS;
|
| 488 |
|
|
defparam slave_sel4.slave_sel_bit_width = slave4_sel_width;
|
| 489 |
|
|
defparam slave_sel4.slave_addr = slave4_sel_addr;
|
| 490 |
|
|
|
| 491 |
|
|
`endif // `ifdef WBS4
|
| 492 |
|
|
`ifdef WBS5
|
| 493 |
|
|
// Slave selec logic, for each master
|
| 494 |
|
|
wb_b3_switch_slave_sel slave_sel5
|
| 495 |
|
|
(
|
| 496 |
|
|
// Outputs
|
| 497 |
|
|
.wbs_master_sel (wbs5_master_sel),
|
| 498 |
|
|
.wbs_master_sel_new (wbs5_master_sel_new),
|
| 499 |
|
|
// Inputs
|
| 500 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 501 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 502 |
|
|
`ifdef WBM1
|
| 503 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 504 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 505 |
|
|
`endif
|
| 506 |
|
|
`ifdef WBM2
|
| 507 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 508 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 509 |
|
|
`endif
|
| 510 |
|
|
`ifdef WBM3
|
| 511 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 512 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 513 |
|
|
`endif
|
| 514 |
|
|
`ifdef WBM4
|
| 515 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 516 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 517 |
|
|
`endif
|
| 518 |
|
|
`ifdef WBM5
|
| 519 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 520 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 521 |
|
|
`endif
|
| 522 |
|
|
|
| 523 |
|
|
.wb_clk (wb_clk),
|
| 524 |
|
|
.wb_rst (wb_rst));
|
| 525 |
|
|
|
| 526 |
|
|
defparam slave_sel5.num_masters = `NUM_MASTERS;
|
| 527 |
|
|
defparam slave_sel5.slave_sel_bit_width = slave5_sel_width;
|
| 528 |
|
|
defparam slave_sel5.slave_addr = slave5_sel_addr;
|
| 529 |
|
|
|
| 530 |
|
|
`endif // `ifdef WBS5
|
| 531 |
|
|
`ifdef WBS6
|
| 532 |
|
|
// Slave selec logic, for each master
|
| 533 |
|
|
wb_b3_switch_slave_sel slave_sel6
|
| 534 |
|
|
(
|
| 535 |
|
|
// Outputs
|
| 536 |
|
|
.wbs_master_sel (wbs6_master_sel),
|
| 537 |
|
|
.wbs_master_sel_new (wbs6_master_sel_new),
|
| 538 |
|
|
// Inputs
|
| 539 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 540 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 541 |
|
|
`ifdef WBM1
|
| 542 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 543 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 544 |
|
|
`endif
|
| 545 |
|
|
`ifdef WBM2
|
| 546 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 547 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 548 |
|
|
`endif
|
| 549 |
|
|
`ifdef WBM3
|
| 550 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 551 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 552 |
|
|
`endif
|
| 553 |
|
|
`ifdef WBM4
|
| 554 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 555 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 556 |
|
|
`endif
|
| 557 |
|
|
`ifdef WBM5
|
| 558 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 559 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 560 |
|
|
`endif
|
| 561 |
|
|
|
| 562 |
|
|
.wb_clk (wb_clk),
|
| 563 |
|
|
.wb_rst (wb_rst));
|
| 564 |
|
|
|
| 565 |
|
|
defparam slave_sel6.num_masters = `NUM_MASTERS;
|
| 566 |
|
|
defparam slave_sel6.slave_sel_bit_width = slave6_sel_width;
|
| 567 |
|
|
defparam slave_sel6.slave_addr = slave6_sel_addr;
|
| 568 |
|
|
|
| 569 |
|
|
`endif // `ifdef WBS6
|
| 570 |
|
|
`ifdef WBS7
|
| 571 |
|
|
// Slave selec logic, for each master
|
| 572 |
|
|
wb_b3_switch_slave_sel slave_sel7
|
| 573 |
|
|
(
|
| 574 |
|
|
// Outputs
|
| 575 |
|
|
.wbs_master_sel (wbs7_master_sel),
|
| 576 |
|
|
.wbs_master_sel_new (wbs7_master_sel_new),
|
| 577 |
|
|
// Inputs
|
| 578 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 579 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 580 |
|
|
`ifdef WBM1
|
| 581 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 582 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 583 |
|
|
`endif
|
| 584 |
|
|
`ifdef WBM2
|
| 585 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 586 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 587 |
|
|
`endif
|
| 588 |
|
|
`ifdef WBM3
|
| 589 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 590 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 591 |
|
|
`endif
|
| 592 |
|
|
`ifdef WBM4
|
| 593 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 594 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 595 |
|
|
`endif
|
| 596 |
|
|
`ifdef WBM5
|
| 597 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 598 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 599 |
|
|
`endif
|
| 600 |
|
|
|
| 601 |
|
|
.wb_clk (wb_clk),
|
| 602 |
|
|
.wb_rst (wb_rst));
|
| 603 |
|
|
|
| 604 |
|
|
defparam slave_sel7.num_masters = `NUM_MASTERS;
|
| 605 |
|
|
defparam slave_sel7.slave_sel_bit_width = slave7_sel_width;
|
| 606 |
|
|
defparam slave_sel7.slave_addr = slave7_sel_addr;
|
| 607 |
|
|
|
| 608 |
|
|
`endif // `ifdef WBS7
|
| 609 |
|
|
|
| 610 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
| 611 |
|
|
// Master slave detection: detect which slave has selected each master
|
| 612 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
| 613 |
|
|
wb_b3_switch_master_detect_slave_sel master_detect_slave0
|
| 614 |
|
|
(
|
| 615 |
|
|
// Outputs
|
| 616 |
|
|
.wbm_slave_sel (wbm0_slave_sel),
|
| 617 |
|
|
// Inputs
|
| 618 |
|
|
.wbs0_master_sel (wbs0_master_sel),
|
| 619 |
|
|
.wbs0_master_sel_new (wbs0_master_sel_new),
|
| 620 |
|
|
`ifdef WBS1
|
| 621 |
|
|
.wbs1_master_sel (wbs1_master_sel),
|
| 622 |
|
|
.wbs1_master_sel_new (wbs1_master_sel_new),
|
| 623 |
|
|
`endif
|
| 624 |
|
|
`ifdef WBS2
|
| 625 |
|
|
.wbs2_master_sel (wbs2_master_sel),
|
| 626 |
|
|
.wbs2_master_sel_new (wbs2_master_sel_new),
|
| 627 |
|
|
`endif
|
| 628 |
|
|
`ifdef WBS3
|
| 629 |
|
|
.wbs3_master_sel (wbs3_master_sel),
|
| 630 |
|
|
.wbs3_master_sel_new (wbs3_master_sel_new),
|
| 631 |
|
|
`endif
|
| 632 |
|
|
`ifdef WBS4
|
| 633 |
|
|
.wbs4_master_sel (wbs4_master_sel),
|
| 634 |
|
|
.wbs4_master_sel_new (wbs4_master_sel_new),
|
| 635 |
|
|
`endif
|
| 636 |
|
|
`ifdef WBS5
|
| 637 |
|
|
.wbs5_master_sel (wbs5_master_sel),
|
| 638 |
|
|
.wbs5_master_sel_new (wbs5_master_sel_new),
|
| 639 |
|
|
`endif
|
| 640 |
|
|
`ifdef WBS6
|
| 641 |
|
|
.wbs6_master_sel (wbs6_master_sel),
|
| 642 |
|
|
.wbs6_master_sel_new (wbs6_master_sel_new),
|
| 643 |
|
|
`endif
|
| 644 |
|
|
`ifdef WBS7
|
| 645 |
|
|
.wbs7_master_sel (wbs7_master_sel),
|
| 646 |
|
|
.wbs7_master_sel_new (wbs7_master_sel_new),
|
| 647 |
|
|
`endif
|
| 648 |
|
|
.wb_clk(wb_clk),
|
| 649 |
|
|
.wb_rst(wb_rst)
|
| 650 |
|
|
);
|
| 651 |
|
|
defparam master_detect_slave0.slave_bit = 0;
|
| 652 |
|
|
|
| 653 |
|
|
`ifdef WBM1
|
| 654 |
|
|
wb_b3_switch_master_detect_slave_sel master_detect_slave1
|
| 655 |
|
|
(
|
| 656 |
|
|
// Outputs
|
| 657 |
|
|
.wbm_slave_sel (wbm1_slave_sel),
|
| 658 |
|
|
// Inputs
|
| 659 |
|
|
.wbs0_master_sel (wbs0_master_sel),
|
| 660 |
|
|
.wbs0_master_sel_new (wbs0_master_sel_new),
|
| 661 |
|
|
`ifdef WBS1
|
| 662 |
|
|
.wbs1_master_sel (wbs1_master_sel),
|
| 663 |
|
|
.wbs1_master_sel_new (wbs1_master_sel_new),
|
| 664 |
|
|
`endif
|
| 665 |
|
|
`ifdef WBS2
|
| 666 |
|
|
.wbs2_master_sel (wbs2_master_sel),
|
| 667 |
|
|
.wbs2_master_sel_new (wbs2_master_sel_new),
|
| 668 |
|
|
`endif
|
| 669 |
|
|
`ifdef WBS3
|
| 670 |
|
|
.wbs3_master_sel (wbs3_master_sel),
|
| 671 |
|
|
.wbs3_master_sel_new (wbs3_master_sel_new),
|
| 672 |
|
|
`endif
|
| 673 |
|
|
`ifdef WBS4
|
| 674 |
|
|
.wbs4_master_sel (wbs4_master_sel),
|
| 675 |
|
|
.wbs4_master_sel_new (wbs4_master_sel_new),
|
| 676 |
|
|
`endif
|
| 677 |
|
|
`ifdef WBS5
|
| 678 |
|
|
.wbs5_master_sel (wbs5_master_sel),
|
| 679 |
|
|
.wbs5_master_sel_new (wbs5_master_sel_new),
|
| 680 |
|
|
`endif
|
| 681 |
|
|
`ifdef WBS6
|
| 682 |
|
|
.wbs6_master_sel (wbs6_master_sel),
|
| 683 |
|
|
.wbs6_master_sel_new (wbs6_master_sel_new),
|
| 684 |
|
|
`endif
|
| 685 |
|
|
`ifdef WBS7
|
| 686 |
|
|
.wbs7_master_sel (wbs7_master_sel),
|
| 687 |
|
|
.wbs7_master_sel_new (wbs7_master_sel_new),
|
| 688 |
|
|
`endif
|
| 689 |
|
|
.wb_clk(wb_clk),
|
| 690 |
|
|
.wb_rst(wb_rst)
|
| 691 |
|
|
);
|
| 692 |
|
|
defparam master_detect_slave1.slave_bit = 1;
|
| 693 |
|
|
`endif // `ifdef WBM1
|
| 694 |
|
|
|
| 695 |
|
|
`ifdef WBM2
|
| 696 |
|
|
wb_b3_switch_master_detect_slave_sel master_detect_slave2
|
| 697 |
|
|
(
|
| 698 |
|
|
// Outputs
|
| 699 |
|
|
.wbm_slave_sel (wbm2_slave_sel),
|
| 700 |
|
|
// Inputs
|
| 701 |
|
|
.wbs0_master_sel (wbs0_master_sel),
|
| 702 |
|
|
.wbs0_master_sel_new (wbs0_master_sel_new),
|
| 703 |
|
|
`ifdef WBS1
|
| 704 |
|
|
.wbs1_master_sel (wbs1_master_sel),
|
| 705 |
|
|
.wbs1_master_sel_new (wbs1_master_sel_new),
|
| 706 |
|
|
`endif
|
| 707 |
|
|
`ifdef WBS2
|
| 708 |
|
|
.wbs2_master_sel (wbs2_master_sel),
|
| 709 |
|
|
.wbs2_master_sel_new (wbs2_master_sel_new),
|
| 710 |
|
|
`endif
|
| 711 |
|
|
`ifdef WBS3
|
| 712 |
|
|
.wbs3_master_sel (wbs3_master_sel),
|
| 713 |
|
|
.wbs3_master_sel_new (wbs3_master_sel_new),
|
| 714 |
|
|
`endif
|
| 715 |
|
|
`ifdef WBS4
|
| 716 |
|
|
.wbs4_master_sel (wbs4_master_sel),
|
| 717 |
|
|
.wbs4_master_sel_new (wbs4_master_sel_new),
|
| 718 |
|
|
`endif
|
| 719 |
|
|
`ifdef WBS5
|
| 720 |
|
|
.wbs5_master_sel (wbs5_master_sel),
|
| 721 |
|
|
.wbs5_master_sel_new (wbs5_master_sel_new),
|
| 722 |
|
|
`endif
|
| 723 |
|
|
`ifdef WBS6
|
| 724 |
|
|
.wbs6_master_sel (wbs6_master_sel),
|
| 725 |
|
|
.wbs6_master_sel_new (wbs6_master_sel_new),
|
| 726 |
|
|
`endif
|
| 727 |
|
|
`ifdef WBS7
|
| 728 |
|
|
.wbs7_master_sel (wbs7_master_sel),
|
| 729 |
|
|
.wbs7_master_sel_new (wbs7_master_sel_new),
|
| 730 |
|
|
`endif
|
| 731 |
|
|
.wb_clk(wb_clk),
|
| 732 |
|
|
.wb_rst(wb_rst)
|
| 733 |
|
|
);
|
| 734 |
|
|
defparam master_detect_slave2.slave_bit = 2;
|
| 735 |
|
|
`endif // `ifdef WBM2
|
| 736 |
|
|
|
| 737 |
|
|
`ifdef WBM3
|
| 738 |
|
|
wb_b3_switch_master_detect_slave_sel master_detect_slave3
|
| 739 |
|
|
(
|
| 740 |
|
|
// Outputs
|
| 741 |
|
|
.wbm_slave_sel (wbm3_slave_sel),
|
| 742 |
|
|
// Inputs
|
| 743 |
|
|
.wbs0_master_sel (wbs0_master_sel),
|
| 744 |
|
|
.wbs0_master_sel_new (wbs0_master_sel_new),
|
| 745 |
|
|
`ifdef WBS1
|
| 746 |
|
|
.wbs1_master_sel (wbs1_master_sel),
|
| 747 |
|
|
.wbs1_master_sel_new (wbs1_master_sel_new),
|
| 748 |
|
|
`endif
|
| 749 |
|
|
`ifdef WBS2
|
| 750 |
|
|
.wbs2_master_sel (wbs2_master_sel),
|
| 751 |
|
|
.wbs2_master_sel_new (wbs2_master_sel_new),
|
| 752 |
|
|
`endif
|
| 753 |
|
|
`ifdef WBS3
|
| 754 |
|
|
.wbs3_master_sel (wbs3_master_sel),
|
| 755 |
|
|
.wbs3_master_sel_new (wbs3_master_sel_new),
|
| 756 |
|
|
`endif
|
| 757 |
|
|
`ifdef WBS4
|
| 758 |
|
|
.wbs4_master_sel (wbs4_master_sel),
|
| 759 |
|
|
.wbs4_master_sel_new (wbs4_master_sel_new),
|
| 760 |
|
|
`endif
|
| 761 |
|
|
`ifdef WBS5
|
| 762 |
|
|
.wbs5_master_sel (wbs5_master_sel),
|
| 763 |
|
|
.wbs5_master_sel_new (wbs5_master_sel_new),
|
| 764 |
|
|
`endif
|
| 765 |
|
|
`ifdef WBS6
|
| 766 |
|
|
.wbs6_master_sel (wbs6_master_sel),
|
| 767 |
|
|
.wbs6_master_sel_new (wbs6_master_sel_new),
|
| 768 |
|
|
`endif
|
| 769 |
|
|
`ifdef WBS7
|
| 770 |
|
|
.wbs7_master_sel (wbs7_master_sel),
|
| 771 |
|
|
.wbs7_master_sel_new (wbs7_master_sel_new),
|
| 772 |
|
|
`endif
|
| 773 |
|
|
.wb_clk(wb_clk),
|
| 774 |
|
|
.wb_rst(wb_rst)
|
| 775 |
|
|
);
|
| 776 |
|
|
defparam master_detect_slave3.slave_bit = 3;
|
| 777 |
|
|
`endif // `ifdef WBM3
|
| 778 |
|
|
|
| 779 |
|
|
`ifdef WBM4
|
| 780 |
|
|
wb_b3_switch_master_detect_slave_sel master_detect_slave4
|
| 781 |
|
|
(
|
| 782 |
|
|
// Outputs
|
| 783 |
|
|
.wbm_slave_sel (wbm4_slave_sel),
|
| 784 |
|
|
// Inputs
|
| 785 |
|
|
.wbs0_master_sel (wbs0_master_sel),
|
| 786 |
|
|
.wbs0_master_sel_new (wbs0_master_sel_new),
|
| 787 |
|
|
`ifdef WBS1
|
| 788 |
|
|
.wbs1_master_sel (wbs1_master_sel),
|
| 789 |
|
|
.wbs1_master_sel_new (wbs1_master_sel_new),
|
| 790 |
|
|
`endif
|
| 791 |
|
|
`ifdef WBS2
|
| 792 |
|
|
.wbs2_master_sel (wbs2_master_sel),
|
| 793 |
|
|
.wbs2_master_sel_new (wbs2_master_sel_new),
|
| 794 |
|
|
`endif
|
| 795 |
|
|
`ifdef WBS3
|
| 796 |
|
|
.wbs3_master_sel (wbs3_master_sel),
|
| 797 |
|
|
.wbs3_master_sel_new (wbs3_master_sel_new),
|
| 798 |
|
|
`endif
|
| 799 |
|
|
`ifdef WBS4
|
| 800 |
|
|
.wbs4_master_sel (wbs4_master_sel),
|
| 801 |
|
|
.wbs4_master_sel_new (wbs4_master_sel_new),
|
| 802 |
|
|
`endif
|
| 803 |
|
|
`ifdef WBS5
|
| 804 |
|
|
.wbs5_master_sel (wbs5_master_sel),
|
| 805 |
|
|
.wbs5_master_sel_new (wbs5_master_sel_new),
|
| 806 |
|
|
`endif
|
| 807 |
|
|
`ifdef WBS6
|
| 808 |
|
|
.wbs6_master_sel (wbs6_master_sel),
|
| 809 |
|
|
.wbs6_master_sel_new (wbs6_master_sel_new),
|
| 810 |
|
|
`endif
|
| 811 |
|
|
`ifdef WBS7
|
| 812 |
|
|
.wbs7_master_sel (wbs7_master_sel),
|
| 813 |
|
|
.wbs7_master_sel_new (wbs7_master_sel_new),
|
| 814 |
|
|
`endif
|
| 815 |
|
|
.wb_clk(wb_clk),
|
| 816 |
|
|
.wb_rst(wb_rst)
|
| 817 |
|
|
);
|
| 818 |
|
|
defparam master_detect_slave4.slave_bit = 4;
|
| 819 |
|
|
`endif // `ifdef WBM4
|
| 820 |
|
|
|
| 821 |
|
|
`ifdef WBM5
|
| 822 |
|
|
wb_b3_switch_master_detect_slave_sel master_detect_slave5
|
| 823 |
|
|
(
|
| 824 |
|
|
// Outputs
|
| 825 |
|
|
.wbm_slave_sel (wbm5_slave_sel),
|
| 826 |
|
|
// Inputs
|
| 827 |
|
|
.wbs0_master_sel (wbs0_master_sel),
|
| 828 |
|
|
.wbs0_master_sel_new (wbs0_master_sel_new),
|
| 829 |
|
|
`ifdef WBS1
|
| 830 |
|
|
.wbs1_master_sel (wbs1_master_sel),
|
| 831 |
|
|
.wbs1_master_sel_new (wbs1_master_sel_new),
|
| 832 |
|
|
`endif
|
| 833 |
|
|
`ifdef WBS2
|
| 834 |
|
|
.wbs2_master_sel (wbs2_master_sel),
|
| 835 |
|
|
.wbs2_master_sel_new (wbs2_master_sel_new),
|
| 836 |
|
|
`endif
|
| 837 |
|
|
`ifdef WBS3
|
| 838 |
|
|
.wbs3_master_sel (wbs3_master_sel),
|
| 839 |
|
|
.wbs3_master_sel_new (wbs3_master_sel_new),
|
| 840 |
|
|
`endif
|
| 841 |
|
|
`ifdef WBS4
|
| 842 |
|
|
.wbs4_master_sel (wbs4_master_sel),
|
| 843 |
|
|
.wbs4_master_sel_new (wbs4_master_sel_new),
|
| 844 |
|
|
`endif
|
| 845 |
|
|
`ifdef WBS5
|
| 846 |
|
|
.wbs5_master_sel (wbs5_master_sel),
|
| 847 |
|
|
.wbs5_master_sel_new (wbs5_master_sel_new),
|
| 848 |
|
|
`endif
|
| 849 |
|
|
`ifdef WBS6
|
| 850 |
|
|
.wbs6_master_sel (wbs6_master_sel),
|
| 851 |
|
|
.wbs6_master_sel_new (wbs6_master_sel_new),
|
| 852 |
|
|
`endif
|
| 853 |
|
|
`ifdef WBS7
|
| 854 |
|
|
.wbs7_master_sel (wbs7_master_sel),
|
| 855 |
|
|
.wbs7_master_sel_new (wbs7_master_sel_new),
|
| 856 |
|
|
`endif
|
| 857 |
|
|
.wb_clk(wb_clk),
|
| 858 |
|
|
.wb_rst(wb_rst)
|
| 859 |
|
|
);
|
| 860 |
|
|
defparam master_detect_slave5.slave_bit = 5;
|
| 861 |
|
|
`endif // `ifdef WBM5
|
| 862 |
|
|
|
| 863 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
| 864 |
|
|
// Slave Output MUXes
|
| 865 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
| 866 |
|
|
|
| 867 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux0
|
| 868 |
|
|
(
|
| 869 |
|
|
// Outputs
|
| 870 |
|
|
.wbs_adr_i (wbs0_adr_i[aw-1:0]),
|
| 871 |
|
|
.wbs_bte_i (wbs0_bte_i[1:0]),
|
| 872 |
|
|
.wbs_cti_i (wbs0_cti_i[2:0]),
|
| 873 |
|
|
.wbs_cyc_i (wbs0_cyc_i),
|
| 874 |
|
|
.wbs_dat_i (wbs0_dat_i[dw-1:0]),
|
| 875 |
|
|
.wbs_sel_i (wbs0_sel_i[3:0]),
|
| 876 |
|
|
.wbs_stb_i (wbs0_stb_i),
|
| 877 |
|
|
.wbs_we_i (wbs0_we_i),
|
| 878 |
|
|
// Inputs
|
| 879 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 880 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 881 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 882 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 883 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 884 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 885 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 886 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 887 |
|
|
`ifdef WBM1
|
| 888 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 889 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 890 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 891 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 892 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 893 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 894 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 895 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 896 |
|
|
`endif
|
| 897 |
|
|
`ifdef WBM2
|
| 898 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 899 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 900 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 901 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 902 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 903 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 904 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 905 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 906 |
|
|
`endif
|
| 907 |
|
|
`ifdef WBM3
|
| 908 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 909 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 910 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 911 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 912 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 913 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 914 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 915 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 916 |
|
|
`endif
|
| 917 |
|
|
`ifdef WBM4
|
| 918 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 919 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 920 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 921 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 922 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 923 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 924 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 925 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 926 |
|
|
`endif
|
| 927 |
|
|
`ifdef WBM5
|
| 928 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 929 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 930 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 931 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 932 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 933 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 934 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 935 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 936 |
|
|
`endif
|
| 937 |
|
|
.wbs_master_sel (wbs0_master_sel),
|
| 938 |
|
|
.wb_clk (wb_clk),
|
| 939 |
|
|
.wb_rst (wb_rst));
|
| 940 |
|
|
|
| 941 |
|
|
`ifdef WBS1
|
| 942 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux1
|
| 943 |
|
|
(
|
| 944 |
|
|
// Outputs
|
| 945 |
|
|
.wbs_adr_i (wbs1_adr_i[aw-1:0]),
|
| 946 |
|
|
.wbs_bte_i (wbs1_bte_i[1:0]),
|
| 947 |
|
|
.wbs_cti_i (wbs1_cti_i[2:0]),
|
| 948 |
|
|
.wbs_cyc_i (wbs1_cyc_i),
|
| 949 |
|
|
.wbs_dat_i (wbs1_dat_i[dw-1:0]),
|
| 950 |
|
|
.wbs_sel_i (wbs1_sel_i[3:0]),
|
| 951 |
|
|
.wbs_stb_i (wbs1_stb_i),
|
| 952 |
|
|
.wbs_we_i (wbs1_we_i),
|
| 953 |
|
|
// Inputs
|
| 954 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 955 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 956 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 957 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 958 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 959 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 960 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 961 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 962 |
|
|
`ifdef WBM1
|
| 963 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 964 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 965 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 966 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 967 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 968 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 969 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 970 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 971 |
|
|
`endif
|
| 972 |
|
|
`ifdef WBM2
|
| 973 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 974 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 975 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 976 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 977 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 978 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 979 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 980 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 981 |
|
|
`endif
|
| 982 |
|
|
`ifdef WBM3
|
| 983 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 984 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 985 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 986 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 987 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 988 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 989 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 990 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 991 |
|
|
`endif
|
| 992 |
|
|
`ifdef WBM4
|
| 993 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 994 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 995 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 996 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 997 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 998 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 999 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1000 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1001 |
|
|
`endif
|
| 1002 |
|
|
`ifdef WBM5
|
| 1003 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1004 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1005 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1006 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1007 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1008 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1009 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1010 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1011 |
|
|
`endif
|
| 1012 |
|
|
.wbs_master_sel (wbs1_master_sel),
|
| 1013 |
|
|
.wb_clk (wb_clk),
|
| 1014 |
|
|
.wb_rst (wb_rst));
|
| 1015 |
|
|
`endif // `ifdef WBS1
|
| 1016 |
|
|
|
| 1017 |
|
|
`ifdef WBS2
|
| 1018 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux2
|
| 1019 |
|
|
(
|
| 1020 |
|
|
// Outputs
|
| 1021 |
|
|
.wbs_adr_i (wbs2_adr_i[aw-1:0]),
|
| 1022 |
|
|
.wbs_bte_i (wbs2_bte_i[1:0]),
|
| 1023 |
|
|
.wbs_cti_i (wbs2_cti_i[2:0]),
|
| 1024 |
|
|
.wbs_cyc_i (wbs2_cyc_i),
|
| 1025 |
|
|
.wbs_dat_i (wbs2_dat_i[dw-1:0]),
|
| 1026 |
|
|
.wbs_sel_i (wbs2_sel_i[3:0]),
|
| 1027 |
|
|
.wbs_stb_i (wbs2_stb_i),
|
| 1028 |
|
|
.wbs_we_i (wbs2_we_i),
|
| 1029 |
|
|
// Inputs
|
| 1030 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 1031 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 1032 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 1033 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 1034 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 1035 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 1036 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 1037 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 1038 |
|
|
`ifdef WBM1
|
| 1039 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 1040 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 1041 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 1042 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 1043 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 1044 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 1045 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 1046 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 1047 |
|
|
`endif
|
| 1048 |
|
|
`ifdef WBM2
|
| 1049 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 1050 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 1051 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 1052 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 1053 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 1054 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 1055 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 1056 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 1057 |
|
|
`endif
|
| 1058 |
|
|
`ifdef WBM3
|
| 1059 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 1060 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 1061 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 1062 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 1063 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 1064 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 1065 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 1066 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 1067 |
|
|
`endif
|
| 1068 |
|
|
`ifdef WBM4
|
| 1069 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 1070 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 1071 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 1072 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 1073 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 1074 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 1075 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1076 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1077 |
|
|
`endif
|
| 1078 |
|
|
`ifdef WBM5
|
| 1079 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1080 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1081 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1082 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1083 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1084 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1085 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1086 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1087 |
|
|
`endif
|
| 1088 |
|
|
|
| 1089 |
|
|
.wbs_master_sel (wbs2_master_sel),
|
| 1090 |
|
|
.wb_clk (wb_clk),
|
| 1091 |
|
|
.wb_rst (wb_rst));
|
| 1092 |
|
|
`endif // `ifdef WBS2
|
| 1093 |
|
|
|
| 1094 |
|
|
`ifdef WBS3
|
| 1095 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux3
|
| 1096 |
|
|
(
|
| 1097 |
|
|
// Outputs
|
| 1098 |
|
|
.wbs_adr_i (wbs3_adr_i[aw-1:0]),
|
| 1099 |
|
|
.wbs_bte_i (wbs3_bte_i[1:0]),
|
| 1100 |
|
|
.wbs_cti_i (wbs3_cti_i[2:0]),
|
| 1101 |
|
|
.wbs_cyc_i (wbs3_cyc_i),
|
| 1102 |
|
|
.wbs_dat_i (wbs3_dat_i[dw-1:0]),
|
| 1103 |
|
|
.wbs_sel_i (wbs3_sel_i[3:0]),
|
| 1104 |
|
|
.wbs_stb_i (wbs3_stb_i),
|
| 1105 |
|
|
.wbs_we_i (wbs3_we_i),
|
| 1106 |
|
|
// Inputs
|
| 1107 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 1108 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 1109 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 1110 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 1111 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 1112 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 1113 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 1114 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 1115 |
|
|
`ifdef WBM1
|
| 1116 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 1117 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 1118 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 1119 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 1120 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 1121 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 1122 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 1123 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 1124 |
|
|
`endif
|
| 1125 |
|
|
`ifdef WBM2
|
| 1126 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 1127 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 1128 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 1129 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 1130 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 1131 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 1132 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 1133 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 1134 |
|
|
`endif
|
| 1135 |
|
|
`ifdef WBM3
|
| 1136 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 1137 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 1138 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 1139 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 1140 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 1141 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 1142 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 1143 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 1144 |
|
|
`endif
|
| 1145 |
|
|
`ifdef WBM4
|
| 1146 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 1147 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 1148 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 1149 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 1150 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 1151 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 1152 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1153 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1154 |
|
|
`endif
|
| 1155 |
|
|
`ifdef WBM5
|
| 1156 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1157 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1158 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1159 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1160 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1161 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1162 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1163 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1164 |
|
|
`endif
|
| 1165 |
|
|
.wbs_master_sel (wbs3_master_sel),
|
| 1166 |
|
|
.wb_clk (wb_clk),
|
| 1167 |
|
|
.wb_rst (wb_rst));
|
| 1168 |
|
|
`endif // `ifdef WBS3
|
| 1169 |
|
|
`ifdef WBS4
|
| 1170 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux4
|
| 1171 |
|
|
(
|
| 1172 |
|
|
// Outputs
|
| 1173 |
|
|
.wbs_adr_i (wbs4_adr_i[aw-1:0]),
|
| 1174 |
|
|
.wbs_bte_i (wbs4_bte_i[1:0]),
|
| 1175 |
|
|
.wbs_cti_i (wbs4_cti_i[2:0]),
|
| 1176 |
|
|
.wbs_cyc_i (wbs4_cyc_i),
|
| 1177 |
|
|
.wbs_dat_i (wbs4_dat_i[dw-1:0]),
|
| 1178 |
|
|
.wbs_sel_i (wbs4_sel_i[3:0]),
|
| 1179 |
|
|
.wbs_stb_i (wbs4_stb_i),
|
| 1180 |
|
|
.wbs_we_i (wbs4_we_i),
|
| 1181 |
|
|
// Inputs
|
| 1182 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 1183 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 1184 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 1185 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 1186 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 1187 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 1188 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 1189 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 1190 |
|
|
`ifdef WBM1
|
| 1191 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 1192 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 1193 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 1194 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 1195 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 1196 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 1197 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 1198 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 1199 |
|
|
`endif
|
| 1200 |
|
|
`ifdef WBM2
|
| 1201 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 1202 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 1203 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 1204 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 1205 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 1206 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 1207 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 1208 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 1209 |
|
|
`endif
|
| 1210 |
|
|
`ifdef WBM3
|
| 1211 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 1212 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 1213 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 1214 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 1215 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 1216 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 1217 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 1218 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 1219 |
|
|
`endif
|
| 1220 |
|
|
`ifdef WBM4
|
| 1221 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 1222 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 1223 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 1224 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 1225 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 1226 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 1227 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1228 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1229 |
|
|
`endif
|
| 1230 |
|
|
`ifdef WBM5
|
| 1231 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1232 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1233 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1234 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1235 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1236 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1237 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1238 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1239 |
|
|
`endif
|
| 1240 |
|
|
.wbs_master_sel (wbs4_master_sel),
|
| 1241 |
|
|
.wb_clk (wb_clk),
|
| 1242 |
|
|
.wb_rst (wb_rst));
|
| 1243 |
|
|
`endif // `ifdef WBS4
|
| 1244 |
|
|
`ifdef WBS5
|
| 1245 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux5
|
| 1246 |
|
|
(
|
| 1247 |
|
|
// Outputs
|
| 1248 |
|
|
.wbs_adr_i (wbs5_adr_i[aw-1:0]),
|
| 1249 |
|
|
.wbs_bte_i (wbs5_bte_i[1:0]),
|
| 1250 |
|
|
.wbs_cti_i (wbs5_cti_i[2:0]),
|
| 1251 |
|
|
.wbs_cyc_i (wbs5_cyc_i),
|
| 1252 |
|
|
.wbs_dat_i (wbs5_dat_i[dw-1:0]),
|
| 1253 |
|
|
.wbs_sel_i (wbs5_sel_i[3:0]),
|
| 1254 |
|
|
.wbs_stb_i (wbs5_stb_i),
|
| 1255 |
|
|
.wbs_we_i (wbs5_we_i),
|
| 1256 |
|
|
// Inputs
|
| 1257 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 1258 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 1259 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 1260 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 1261 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 1262 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 1263 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 1264 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 1265 |
|
|
`ifdef WBM1
|
| 1266 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 1267 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 1268 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 1269 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 1270 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 1271 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 1272 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 1273 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 1274 |
|
|
`endif
|
| 1275 |
|
|
`ifdef WBM2
|
| 1276 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 1277 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 1278 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 1279 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 1280 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 1281 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 1282 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 1283 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 1284 |
|
|
`endif
|
| 1285 |
|
|
`ifdef WBM3
|
| 1286 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 1287 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 1288 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 1289 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 1290 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 1291 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 1292 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 1293 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 1294 |
|
|
`endif
|
| 1295 |
|
|
`ifdef WBM4
|
| 1296 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 1297 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 1298 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 1299 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 1300 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 1301 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 1302 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1303 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1304 |
|
|
`endif
|
| 1305 |
|
|
`ifdef WBM5
|
| 1306 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1307 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1308 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1309 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1310 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1311 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1312 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1313 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1314 |
|
|
`endif
|
| 1315 |
|
|
.wbs_master_sel (wbs5_master_sel),
|
| 1316 |
|
|
.wb_clk (wb_clk),
|
| 1317 |
|
|
.wb_rst (wb_rst));
|
| 1318 |
|
|
`endif // `ifdef WBS5
|
| 1319 |
|
|
`ifdef WBS6
|
| 1320 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux6
|
| 1321 |
|
|
(
|
| 1322 |
|
|
// Outputs
|
| 1323 |
|
|
.wbs_adr_i (wbs6_adr_i[aw-1:0]),
|
| 1324 |
|
|
.wbs_bte_i (wbs6_bte_i[1:0]),
|
| 1325 |
|
|
.wbs_cti_i (wbs6_cti_i[2:0]),
|
| 1326 |
|
|
.wbs_cyc_i (wbs6_cyc_i),
|
| 1327 |
|
|
.wbs_dat_i (wbs6_dat_i[dw-1:0]),
|
| 1328 |
|
|
.wbs_sel_i (wbs6_sel_i[3:0]),
|
| 1329 |
|
|
.wbs_stb_i (wbs6_stb_i),
|
| 1330 |
|
|
.wbs_we_i (wbs6_we_i),
|
| 1331 |
|
|
// Inputs
|
| 1332 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 1333 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 1334 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 1335 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 1336 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 1337 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 1338 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 1339 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 1340 |
|
|
`ifdef WBM1
|
| 1341 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 1342 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 1343 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 1344 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 1345 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 1346 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 1347 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 1348 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 1349 |
|
|
`endif
|
| 1350 |
|
|
`ifdef WBM2
|
| 1351 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 1352 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 1353 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 1354 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 1355 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 1356 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 1357 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 1358 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 1359 |
|
|
`endif
|
| 1360 |
|
|
`ifdef WBM3
|
| 1361 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 1362 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 1363 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 1364 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 1365 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 1366 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 1367 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 1368 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 1369 |
|
|
`endif
|
| 1370 |
|
|
`ifdef WBM4
|
| 1371 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 1372 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 1373 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 1374 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 1375 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 1376 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 1377 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1378 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1379 |
|
|
`endif
|
| 1380 |
|
|
`ifdef WBM5
|
| 1381 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1382 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1383 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1384 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1385 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1386 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1387 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1388 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1389 |
|
|
`endif
|
| 1390 |
|
|
.wbs_master_sel (wbs6_master_sel),
|
| 1391 |
|
|
.wb_clk (wb_clk),
|
| 1392 |
|
|
.wb_rst (wb_rst));
|
| 1393 |
|
|
`endif // `ifdef WBS6
|
| 1394 |
|
|
`ifdef WBS7
|
| 1395 |
|
|
wb_b3_switch_slave_out_mux slave_out_mux7
|
| 1396 |
|
|
(
|
| 1397 |
|
|
// Outputs
|
| 1398 |
|
|
.wbs_adr_i (wbs7_adr_i[aw-1:0]),
|
| 1399 |
|
|
.wbs_bte_i (wbs7_bte_i[1:0]),
|
| 1400 |
|
|
.wbs_cti_i (wbs7_cti_i[2:0]),
|
| 1401 |
|
|
.wbs_cyc_i (wbs7_cyc_i),
|
| 1402 |
|
|
.wbs_dat_i (wbs7_dat_i[dw-1:0]),
|
| 1403 |
|
|
.wbs_sel_i (wbs7_sel_i[3:0]),
|
| 1404 |
|
|
.wbs_stb_i (wbs7_stb_i),
|
| 1405 |
|
|
.wbs_we_i (wbs7_we_i),
|
| 1406 |
|
|
// Inputs
|
| 1407 |
|
|
.wbm0_adr_o (wbm0_adr_o[aw-1:0]),
|
| 1408 |
|
|
.wbm0_bte_o (wbm0_bte_o[1:0]),
|
| 1409 |
|
|
.wbm0_cti_o (wbm0_cti_o[2:0]),
|
| 1410 |
|
|
.wbm0_cyc_o (wbm0_cyc_o),
|
| 1411 |
|
|
.wbm0_dat_o (wbm0_dat_o[dw-1:0]),
|
| 1412 |
|
|
.wbm0_sel_o (wbm0_sel_o[3:0]),
|
| 1413 |
|
|
.wbm0_stb_o (wbm0_stb_o),
|
| 1414 |
|
|
.wbm0_we_o (wbm0_we_o),
|
| 1415 |
|
|
`ifdef WBM1
|
| 1416 |
|
|
.wbm1_adr_o (wbm1_adr_o[aw-1:0]),
|
| 1417 |
|
|
.wbm1_bte_o (wbm1_bte_o[1:0]),
|
| 1418 |
|
|
.wbm1_cti_o (wbm1_cti_o[2:0]),
|
| 1419 |
|
|
.wbm1_cyc_o (wbm1_cyc_o),
|
| 1420 |
|
|
.wbm1_dat_o (wbm1_dat_o[dw-1:0]),
|
| 1421 |
|
|
.wbm1_sel_o (wbm1_sel_o[3:0]),
|
| 1422 |
|
|
.wbm1_stb_o (wbm1_stb_o),
|
| 1423 |
|
|
.wbm1_we_o (wbm1_we_o),
|
| 1424 |
|
|
`endif
|
| 1425 |
|
|
`ifdef WBM2
|
| 1426 |
|
|
.wbm2_adr_o (wbm2_adr_o[aw-1:0]),
|
| 1427 |
|
|
.wbm2_bte_o (wbm2_bte_o[1:0]),
|
| 1428 |
|
|
.wbm2_cti_o (wbm2_cti_o[2:0]),
|
| 1429 |
|
|
.wbm2_cyc_o (wbm2_cyc_o),
|
| 1430 |
|
|
.wbm2_dat_o (wbm2_dat_o[dw-1:0]),
|
| 1431 |
|
|
.wbm2_sel_o (wbm2_sel_o[3:0]),
|
| 1432 |
|
|
.wbm2_stb_o (wbm2_stb_o),
|
| 1433 |
|
|
.wbm2_we_o (wbm2_we_o),
|
| 1434 |
|
|
`endif
|
| 1435 |
|
|
`ifdef WBM3
|
| 1436 |
|
|
.wbm3_adr_o (wbm3_adr_o[aw-1:0]),
|
| 1437 |
|
|
.wbm3_bte_o (wbm3_bte_o[1:0]),
|
| 1438 |
|
|
.wbm3_cti_o (wbm3_cti_o[2:0]),
|
| 1439 |
|
|
.wbm3_cyc_o (wbm3_cyc_o),
|
| 1440 |
|
|
.wbm3_dat_o (wbm3_dat_o[dw-1:0]),
|
| 1441 |
|
|
.wbm3_sel_o (wbm3_sel_o[3:0]),
|
| 1442 |
|
|
.wbm3_stb_o (wbm3_stb_o),
|
| 1443 |
|
|
.wbm3_we_o (wbm3_we_o),
|
| 1444 |
|
|
`endif
|
| 1445 |
|
|
`ifdef WBM4
|
| 1446 |
|
|
.wbm4_adr_o (wbm4_adr_o[aw-1:0]),
|
| 1447 |
|
|
.wbm4_bte_o (wbm4_bte_o[1:0]),
|
| 1448 |
|
|
.wbm4_cti_o (wbm4_cti_o[2:0]),
|
| 1449 |
|
|
.wbm4_cyc_o (wbm4_cyc_o),
|
| 1450 |
|
|
.wbm4_dat_o (wbm4_dat_o[dw-1:0]),
|
| 1451 |
|
|
.wbm4_sel_o (wbm4_sel_o[3:0]),
|
| 1452 |
|
|
.wbm4_stb_o (wbm4_stb_o),
|
| 1453 |
|
|
.wbm4_we_o (wbm4_we_o),
|
| 1454 |
|
|
`endif
|
| 1455 |
|
|
`ifdef WBM5
|
| 1456 |
|
|
.wbm5_adr_o (wbm5_adr_o[aw-1:0]),
|
| 1457 |
|
|
.wbm5_bte_o (wbm5_bte_o[1:0]),
|
| 1458 |
|
|
.wbm5_cti_o (wbm5_cti_o[2:0]),
|
| 1459 |
|
|
.wbm5_cyc_o (wbm5_cyc_o),
|
| 1460 |
|
|
.wbm5_dat_o (wbm5_dat_o[dw-1:0]),
|
| 1461 |
|
|
.wbm5_sel_o (wbm5_sel_o[3:0]),
|
| 1462 |
|
|
.wbm5_stb_o (wbm5_stb_o),
|
| 1463 |
|
|
.wbm5_we_o (wbm5_we_o),
|
| 1464 |
|
|
`endif
|
| 1465 |
|
|
.wbs_master_sel (wbs7_master_sel),
|
| 1466 |
|
|
.wb_clk (wb_clk),
|
| 1467 |
|
|
.wb_rst (wb_rst));
|
| 1468 |
|
|
`endif // `ifdef WBS7
|
| 1469 |
|
|
|
| 1470 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
| 1471 |
|
|
// Master output MUXes
|
| 1472 |
|
|
/////////////////////////////////////////////////////////////////////////////
|
| 1473 |
|
|
|
| 1474 |
|
|
wb_b3_switch_master_out_mux master_out_mux0
|
| 1475 |
|
|
(
|
| 1476 |
|
|
.wbm_stb_o (wbm0_stb_o),
|
| 1477 |
|
|
// Outputs
|
| 1478 |
|
|
.wbm_ack_i (wbm0_ack_i),
|
| 1479 |
|
|
.wbm_err_i (wbm0_err_i),
|
| 1480 |
|
|
.wbm_rty_i (wbm0_rty_i),
|
| 1481 |
|
|
.wbm_dat_i (wbm0_dat_i[dw-1:0]),
|
| 1482 |
|
|
// Inputs
|
| 1483 |
|
|
.wbs0_ack_o (wbs0_ack_o),
|
| 1484 |
|
|
.wbs0_err_o (wbs0_err_o),
|
| 1485 |
|
|
.wbs0_rty_o (wbs0_rty_o),
|
| 1486 |
|
|
.wbs0_dat_o (wbs0_dat_o[dw-1:0]),
|
| 1487 |
|
|
`ifdef WBS1
|
| 1488 |
|
|
.wbs1_ack_o (wbs1_ack_o),
|
| 1489 |
|
|
.wbs1_err_o (wbs1_err_o),
|
| 1490 |
|
|
.wbs1_rty_o (wbs1_rty_o),
|
| 1491 |
|
|
.wbs1_dat_o (wbs1_dat_o[dw-1:0]),
|
| 1492 |
|
|
`endif
|
| 1493 |
|
|
`ifdef WBS2
|
| 1494 |
|
|
.wbs2_ack_o (wbs2_ack_o),
|
| 1495 |
|
|
.wbs2_err_o (wbs2_err_o),
|
| 1496 |
|
|
.wbs2_rty_o (wbs2_rty_o),
|
| 1497 |
|
|
.wbs2_dat_o (wbs2_dat_o[dw-1:0]),
|
| 1498 |
|
|
`endif
|
| 1499 |
|
|
`ifdef WBS3
|
| 1500 |
|
|
.wbs3_ack_o (wbs3_ack_o),
|
| 1501 |
|
|
.wbs3_err_o (wbs3_err_o),
|
| 1502 |
|
|
.wbs3_rty_o (wbs3_rty_o),
|
| 1503 |
|
|
.wbs3_dat_o (wbs3_dat_o[dw-1:0]),
|
| 1504 |
|
|
`endif
|
| 1505 |
|
|
`ifdef WBS4
|
| 1506 |
|
|
.wbs4_ack_o (wbs4_ack_o),
|
| 1507 |
|
|
.wbs4_err_o (wbs4_err_o),
|
| 1508 |
|
|
.wbs4_rty_o (wbs4_rty_o),
|
| 1509 |
|
|
.wbs4_dat_o (wbs4_dat_o[dw-1:0]),
|
| 1510 |
|
|
`endif
|
| 1511 |
|
|
`ifdef WBS5
|
| 1512 |
|
|
.wbs5_ack_o (wbs5_ack_o),
|
| 1513 |
|
|
.wbs5_err_o (wbs5_err_o),
|
| 1514 |
|
|
.wbs5_rty_o (wbs5_rty_o),
|
| 1515 |
|
|
.wbs5_dat_o (wbs5_dat_o[dw-1:0]),
|
| 1516 |
|
|
`endif
|
| 1517 |
|
|
`ifdef WBS6
|
| 1518 |
|
|
.wbs6_ack_o (wbs6_ack_o),
|
| 1519 |
|
|
.wbs6_err_o (wbs6_err_o),
|
| 1520 |
|
|
.wbs6_rty_o (wbs6_rty_o),
|
| 1521 |
|
|
.wbs6_dat_o (wbs6_dat_o[dw-1:0]),
|
| 1522 |
|
|
`endif
|
| 1523 |
|
|
`ifdef WBS7
|
| 1524 |
|
|
.wbs7_ack_o (wbs7_ack_o),
|
| 1525 |
|
|
.wbs7_err_o (wbs7_err_o),
|
| 1526 |
|
|
.wbs7_rty_o (wbs7_rty_o),
|
| 1527 |
|
|
.wbs7_dat_o (wbs7_dat_o[dw-1:0]),
|
| 1528 |
|
|
`endif
|
| 1529 |
|
|
.wbm_slave_sel (wbm0_slave_sel),
|
| 1530 |
|
|
.wb_clk (wb_clk),
|
| 1531 |
|
|
.wb_rst (wb_rst));
|
| 1532 |
|
|
|
| 1533 |
|
|
`ifdef WBM1
|
| 1534 |
|
|
wb_b3_switch_master_out_mux master_out_mux1
|
| 1535 |
|
|
(
|
| 1536 |
|
|
.wbm_stb_o (wbm1_stb_o),
|
| 1537 |
|
|
// Outputs
|
| 1538 |
|
|
.wbm_ack_i (wbm1_ack_i),
|
| 1539 |
|
|
.wbm_err_i (wbm1_err_i),
|
| 1540 |
|
|
.wbm_rty_i (wbm1_rty_i),
|
| 1541 |
|
|
.wbm_dat_i (wbm1_dat_i[dw-1:0]),
|
| 1542 |
|
|
// Inputs
|
| 1543 |
|
|
.wbs0_ack_o (wbs0_ack_o),
|
| 1544 |
|
|
.wbs0_err_o (wbs0_err_o),
|
| 1545 |
|
|
.wbs0_rty_o (wbs0_rty_o),
|
| 1546 |
|
|
.wbs0_dat_o (wbs0_dat_o[dw-1:0]),
|
| 1547 |
|
|
`ifdef WBS1
|
| 1548 |
|
|
.wbs1_ack_o (wbs1_ack_o),
|
| 1549 |
|
|
.wbs1_err_o (wbs1_err_o),
|
| 1550 |
|
|
.wbs1_rty_o (wbs1_rty_o),
|
| 1551 |
|
|
.wbs1_dat_o (wbs1_dat_o[dw-1:0]),
|
| 1552 |
|
|
`endif
|
| 1553 |
|
|
`ifdef WBS2
|
| 1554 |
|
|
.wbs2_ack_o (wbs2_ack_o),
|
| 1555 |
|
|
.wbs2_err_o (wbs2_err_o),
|
| 1556 |
|
|
.wbs2_rty_o (wbs2_rty_o),
|
| 1557 |
|
|
.wbs2_dat_o (wbs2_dat_o[dw-1:0]),
|
| 1558 |
|
|
`endif
|
| 1559 |
|
|
`ifdef WBS3
|
| 1560 |
|
|
.wbs3_ack_o (wbs3_ack_o),
|
| 1561 |
|
|
.wbs3_err_o (wbs3_err_o),
|
| 1562 |
|
|
.wbs3_rty_o (wbs3_rty_o),
|
| 1563 |
|
|
.wbs3_dat_o (wbs3_dat_o[dw-1:0]),
|
| 1564 |
|
|
`endif
|
| 1565 |
|
|
`ifdef WBS4
|
| 1566 |
|
|
.wbs4_ack_o (wbs4_ack_o),
|
| 1567 |
|
|
.wbs4_err_o (wbs4_err_o),
|
| 1568 |
|
|
.wbs4_rty_o (wbs4_rty_o),
|
| 1569 |
|
|
.wbs4_dat_o (wbs4_dat_o[dw-1:0]),
|
| 1570 |
|
|
`endif
|
| 1571 |
|
|
`ifdef WBS5
|
| 1572 |
|
|
.wbs5_ack_o (wbs5_ack_o),
|
| 1573 |
|
|
.wbs5_err_o (wbs5_err_o),
|
| 1574 |
|
|
.wbs5_rty_o (wbs5_rty_o),
|
| 1575 |
|
|
.wbs5_dat_o (wbs5_dat_o[dw-1:0]),
|
| 1576 |
|
|
`endif
|
| 1577 |
|
|
`ifdef WBS6
|
| 1578 |
|
|
.wbs6_ack_o (wbs6_ack_o),
|
| 1579 |
|
|
.wbs6_err_o (wbs6_err_o),
|
| 1580 |
|
|
.wbs6_rty_o (wbs6_rty_o),
|
| 1581 |
|
|
.wbs6_dat_o (wbs6_dat_o[dw-1:0]),
|
| 1582 |
|
|
`endif
|
| 1583 |
|
|
`ifdef WBS7
|
| 1584 |
|
|
.wbs7_ack_o (wbs7_ack_o),
|
| 1585 |
|
|
.wbs7_err_o (wbs7_err_o),
|
| 1586 |
|
|
.wbs7_rty_o (wbs7_rty_o),
|
| 1587 |
|
|
.wbs7_dat_o (wbs7_dat_o[dw-1:0]),
|
| 1588 |
|
|
`endif
|
| 1589 |
|
|
.wbm_slave_sel (wbm1_slave_sel),
|
| 1590 |
|
|
.wb_clk (wb_clk),
|
| 1591 |
|
|
.wb_rst (wb_rst));
|
| 1592 |
|
|
`endif // `ifdef WBM1
|
| 1593 |
|
|
|
| 1594 |
|
|
`ifdef WBM2
|
| 1595 |
|
|
wb_b3_switch_master_out_mux master_out_mux2
|
| 1596 |
|
|
(
|
| 1597 |
|
|
.wbm_stb_o (wbm2_stb_o),
|
| 1598 |
|
|
// Outputs
|
| 1599 |
|
|
.wbm_ack_i (wbm2_ack_i),
|
| 1600 |
|
|
.wbm_err_i (wbm2_err_i),
|
| 1601 |
|
|
.wbm_rty_i (wbm2_rty_i),
|
| 1602 |
|
|
.wbm_dat_i (wbm2_dat_i[dw-1:0]),
|
| 1603 |
|
|
// Inputs
|
| 1604 |
|
|
.wbs0_ack_o (wbs0_ack_o),
|
| 1605 |
|
|
.wbs0_err_o (wbs0_err_o),
|
| 1606 |
|
|
.wbs0_rty_o (wbs0_rty_o),
|
| 1607 |
|
|
.wbs0_dat_o (wbs0_dat_o[dw-1:0]),
|
| 1608 |
|
|
`ifdef WBS1
|
| 1609 |
|
|
.wbs1_ack_o (wbs1_ack_o),
|
| 1610 |
|
|
.wbs1_err_o (wbs1_err_o),
|
| 1611 |
|
|
.wbs1_rty_o (wbs1_rty_o),
|
| 1612 |
|
|
.wbs1_dat_o (wbs1_dat_o[dw-1:0]),
|
| 1613 |
|
|
`endif
|
| 1614 |
|
|
`ifdef WBS2
|
| 1615 |
|
|
.wbs2_ack_o (wbs2_ack_o),
|
| 1616 |
|
|
.wbs2_err_o (wbs2_err_o),
|
| 1617 |
|
|
.wbs2_rty_o (wbs2_rty_o),
|
| 1618 |
|
|
.wbs2_dat_o (wbs2_dat_o[dw-1:0]),
|
| 1619 |
|
|
`endif
|
| 1620 |
|
|
`ifdef WBS3
|
| 1621 |
|
|
.wbs3_ack_o (wbs3_ack_o),
|
| 1622 |
|
|
.wbs3_err_o (wbs3_err_o),
|
| 1623 |
|
|
.wbs3_rty_o (wbs3_rty_o),
|
| 1624 |
|
|
.wbs3_dat_o (wbs3_dat_o[dw-1:0]),
|
| 1625 |
|
|
`endif
|
| 1626 |
|
|
`ifdef WBS4
|
| 1627 |
|
|
.wbs4_ack_o (wbs4_ack_o),
|
| 1628 |
|
|
.wbs4_err_o (wbs4_err_o),
|
| 1629 |
|
|
.wbs4_rty_o (wbs4_rty_o),
|
| 1630 |
|
|
.wbs4_dat_o (wbs4_dat_o[dw-1:0]),
|
| 1631 |
|
|
`endif
|
| 1632 |
|
|
`ifdef WBS5
|
| 1633 |
|
|
.wbs5_ack_o (wbs5_ack_o),
|
| 1634 |
|
|
.wbs5_err_o (wbs5_err_o),
|
| 1635 |
|
|
.wbs5_rty_o (wbs5_rty_o),
|
| 1636 |
|
|
.wbs5_dat_o (wbs5_dat_o[dw-1:0]),
|
| 1637 |
|
|
`endif
|
| 1638 |
|
|
`ifdef WBS6
|
| 1639 |
|
|
.wbs6_ack_o (wbs6_ack_o),
|
| 1640 |
|
|
.wbs6_err_o (wbs6_err_o),
|
| 1641 |
|
|
.wbs6_rty_o (wbs6_rty_o),
|
| 1642 |
|
|
.wbs6_dat_o (wbs6_dat_o[dw-1:0]),
|
| 1643 |
|
|
`endif
|
| 1644 |
|
|
`ifdef WBS7
|
| 1645 |
|
|
.wbs7_ack_o (wbs7_ack_o),
|
| 1646 |
|
|
.wbs7_err_o (wbs7_err_o),
|
| 1647 |
|
|
.wbs7_rty_o (wbs7_rty_o),
|
| 1648 |
|
|
.wbs7_dat_o (wbs7_dat_o[dw-1:0]),
|
| 1649 |
|
|
`endif
|
| 1650 |
|
|
.wbm_slave_sel (wbm2_slave_sel),
|
| 1651 |
|
|
.wb_clk (wb_clk),
|
| 1652 |
|
|
.wb_rst (wb_rst));
|
| 1653 |
|
|
`endif
|
| 1654 |
|
|
|
| 1655 |
|
|
`ifdef WBM3
|
| 1656 |
|
|
wb_b3_switch_master_out_mux master_out_mux3
|
| 1657 |
|
|
(
|
| 1658 |
|
|
.wbm_stb_o (wbm3_stb_o),
|
| 1659 |
|
|
// Outputs
|
| 1660 |
|
|
.wbm_ack_i (wbm3_ack_i),
|
| 1661 |
|
|
.wbm_err_i (wbm3_err_i),
|
| 1662 |
|
|
.wbm_rty_i (wbm3_rty_i),
|
| 1663 |
|
|
.wbm_dat_i (wbm3_dat_i[dw-1:0]),
|
| 1664 |
|
|
// Inputs
|
| 1665 |
|
|
.wbs0_ack_o (wbs0_ack_o),
|
| 1666 |
|
|
.wbs0_err_o (wbs0_err_o),
|
| 1667 |
|
|
.wbs0_rty_o (wbs0_rty_o),
|
| 1668 |
|
|
.wbs0_dat_o (wbs0_dat_o[dw-1:0]),
|
| 1669 |
|
|
`ifdef WBS1
|
| 1670 |
|
|
.wbs1_ack_o (wbs1_ack_o),
|
| 1671 |
|
|
.wbs1_err_o (wbs1_err_o),
|
| 1672 |
|
|
.wbs1_rty_o (wbs1_rty_o),
|
| 1673 |
|
|
.wbs1_dat_o (wbs1_dat_o[dw-1:0]),
|
| 1674 |
|
|
`endif
|
| 1675 |
|
|
`ifdef WBS2
|
| 1676 |
|
|
.wbs2_ack_o (wbs2_ack_o),
|
| 1677 |
|
|
.wbs2_err_o (wbs2_err_o),
|
| 1678 |
|
|
.wbs2_rty_o (wbs2_rty_o),
|
| 1679 |
|
|
.wbs2_dat_o (wbs2_dat_o[dw-1:0]),
|
| 1680 |
|
|
`endif
|
| 1681 |
|
|
`ifdef WBS3
|
| 1682 |
|
|
.wbs3_ack_o (wbs3_ack_o),
|
| 1683 |
|
|
.wbs3_err_o (wbs3_err_o),
|
| 1684 |
|
|
.wbs3_rty_o (wbs3_rty_o),
|
| 1685 |
|
|
.wbs3_dat_o (wbs3_dat_o[dw-1:0]),
|
| 1686 |
|
|
`endif
|
| 1687 |
|
|
`ifdef WBS4
|
| 1688 |
|
|
.wbs4_ack_o (wbs4_ack_o),
|
| 1689 |
|
|
.wbs4_err_o (wbs4_err_o),
|
| 1690 |
|
|
.wbs4_rty_o (wbs4_rty_o),
|
| 1691 |
|
|
.wbs4_dat_o (wbs4_dat_o[dw-1:0]),
|
| 1692 |
|
|
`endif
|
| 1693 |
|
|
`ifdef WBS5
|
| 1694 |
|
|
.wbs5_ack_o (wbs5_ack_o),
|
| 1695 |
|
|
.wbs5_err_o (wbs5_err_o),
|
| 1696 |
|
|
.wbs5_rty_o (wbs5_rty_o),
|
| 1697 |
|
|
.wbs5_dat_o (wbs5_dat_o[dw-1:0]),
|
| 1698 |
|
|
`endif
|
| 1699 |
|
|
`ifdef WBS6
|
| 1700 |
|
|
.wbs6_ack_o (wbs6_ack_o),
|
| 1701 |
|
|
.wbs6_err_o (wbs6_err_o),
|
| 1702 |
|
|
.wbs6_rty_o (wbs6_rty_o),
|
| 1703 |
|
|
.wbs6_dat_o (wbs6_dat_o[dw-1:0]),
|
| 1704 |
|
|
`endif
|
| 1705 |
|
|
`ifdef WBS7
|
| 1706 |
|
|
.wbs7_ack_o (wbs7_ack_o),
|
| 1707 |
|
|
.wbs7_err_o (wbs7_err_o),
|
| 1708 |
|
|
.wbs7_rty_o (wbs7_rty_o),
|
| 1709 |
|
|
.wbs7_dat_o (wbs7_dat_o[dw-1:0]),
|
| 1710 |
|
|
`endif
|
| 1711 |
|
|
.wbm_slave_sel (wbm3_slave_sel),
|
| 1712 |
|
|
.wb_clk (wb_clk),
|
| 1713 |
|
|
.wb_rst (wb_rst));
|
| 1714 |
|
|
`endif
|
| 1715 |
|
|
`ifdef WBM4
|
| 1716 |
|
|
wb_b3_switch_master_out_mux master_out_mux4
|
| 1717 |
|
|
(
|
| 1718 |
|
|
.wbm_stb_o (wbm4_stb_o),
|
| 1719 |
|
|
// Outputs
|
| 1720 |
|
|
.wbm_ack_i (wbm4_ack_i),
|
| 1721 |
|
|
.wbm_err_i (wbm4_err_i),
|
| 1722 |
|
|
.wbm_rty_i (wbm4_rty_i),
|
| 1723 |
|
|
.wbm_dat_i (wbm4_dat_i[dw-1:0]),
|
| 1724 |
|
|
// Inputs
|
| 1725 |
|
|
.wbs0_ack_o (wbs0_ack_o),
|
| 1726 |
|
|
.wbs0_err_o (wbs0_err_o),
|
| 1727 |
|
|
.wbs0_rty_o (wbs0_rty_o),
|
| 1728 |
|
|
.wbs0_dat_o (wbs0_dat_o[dw-1:0]),
|
| 1729 |
|
|
`ifdef WBS1
|
| 1730 |
|
|
.wbs1_ack_o (wbs1_ack_o),
|
| 1731 |
|
|
.wbs1_err_o (wbs1_err_o),
|
| 1732 |
|
|
.wbs1_rty_o (wbs1_rty_o),
|
| 1733 |
|
|
.wbs1_dat_o (wbs1_dat_o[dw-1:0]),
|
| 1734 |
|
|
`endif
|
| 1735 |
|
|
`ifdef WBS2
|
| 1736 |
|
|
.wbs2_ack_o (wbs2_ack_o),
|
| 1737 |
|
|
.wbs2_err_o (wbs2_err_o),
|
| 1738 |
|
|
.wbs2_rty_o (wbs2_rty_o),
|
| 1739 |
|
|
.wbs2_dat_o (wbs2_dat_o[dw-1:0]),
|
| 1740 |
|
|
`endif
|
| 1741 |
|
|
`ifdef WBS3
|
| 1742 |
|
|
.wbs3_ack_o (wbs3_ack_o),
|
| 1743 |
|
|
.wbs3_err_o (wbs3_err_o),
|
| 1744 |
|
|
.wbs3_rty_o (wbs3_rty_o),
|
| 1745 |
|
|
.wbs3_dat_o (wbs3_dat_o[dw-1:0]),
|
| 1746 |
|
|
`endif
|
| 1747 |
|
|
`ifdef WBS4
|
| 1748 |
|
|
.wbs4_ack_o (wbs4_ack_o),
|
| 1749 |
|
|
.wbs4_err_o (wbs4_err_o),
|
| 1750 |
|
|
.wbs4_rty_o (wbs4_rty_o),
|
| 1751 |
|
|
.wbs4_dat_o (wbs4_dat_o[dw-1:0]),
|
| 1752 |
|
|
`endif
|
| 1753 |
|
|
`ifdef WBS5
|
| 1754 |
|
|
.wbs5_ack_o (wbs5_ack_o),
|
| 1755 |
|
|
.wbs5_err_o (wbs5_err_o),
|
| 1756 |
|
|
.wbs5_rty_o (wbs5_rty_o),
|
| 1757 |
|
|
.wbs5_dat_o (wbs5_dat_o[dw-1:0]),
|
| 1758 |
|
|
`endif
|
| 1759 |
|
|
`ifdef WBS6
|
| 1760 |
|
|
.wbs6_ack_o (wbs6_ack_o),
|
| 1761 |
|
|
.wbs6_err_o (wbs6_err_o),
|
| 1762 |
|
|
.wbs6_rty_o (wbs6_rty_o),
|
| 1763 |
|
|
.wbs6_dat_o (wbs6_dat_o[dw-1:0]),
|
| 1764 |
|
|
`endif
|
| 1765 |
|
|
`ifdef WBS7
|
| 1766 |
|
|
.wbs7_ack_o (wbs7_ack_o),
|
| 1767 |
|
|
.wbs7_err_o (wbs7_err_o),
|
| 1768 |
|
|
.wbs7_rty_o (wbs7_rty_o),
|
| 1769 |
|
|
.wbs7_dat_o (wbs7_dat_o[dw-1:0]),
|
| 1770 |
|
|
`endif
|
| 1771 |
|
|
.wbm_slave_sel (wbm4_slave_sel),
|
| 1772 |
|
|
.wb_clk (wb_clk),
|
| 1773 |
|
|
.wb_rst (wb_rst));
|
| 1774 |
|
|
`endif
|
| 1775 |
|
|
`ifdef WBM5
|
| 1776 |
|
|
wb_b3_switch_master_out_mux master_out_mux5
|
| 1777 |
|
|
(
|
| 1778 |
|
|
.wbm_stb_o (wbm5_stb_o),
|
| 1779 |
|
|
// Outputs
|
| 1780 |
|
|
.wbm_ack_i (wbm5_ack_i),
|
| 1781 |
|
|
.wbm_err_i (wbm5_err_i),
|
| 1782 |
|
|
.wbm_rty_i (wbm5_rty_i),
|
| 1783 |
|
|
.wbm_dat_i (wbm5_dat_i[dw-1:0]),
|
| 1784 |
|
|
// Inputs
|
| 1785 |
|
|
.wbs0_ack_o (wbs0_ack_o),
|
| 1786 |
|
|
.wbs0_err_o (wbs0_err_o),
|
| 1787 |
|
|
.wbs0_rty_o (wbs0_rty_o),
|
| 1788 |
|
|
.wbs0_dat_o (wbs0_dat_o[dw-1:0]),
|
| 1789 |
|
|
`ifdef WBS1
|
| 1790 |
|
|
.wbs1_ack_o (wbs1_ack_o),
|
| 1791 |
|
|
.wbs1_err_o (wbs1_err_o),
|
| 1792 |
|
|
.wbs1_rty_o (wbs1_rty_o),
|
| 1793 |
|
|
.wbs1_dat_o (wbs1_dat_o[dw-1:0]),
|
| 1794 |
|
|
`endif
|
| 1795 |
|
|
`ifdef WBS2
|
| 1796 |
|
|
.wbs2_ack_o (wbs2_ack_o),
|
| 1797 |
|
|
.wbs2_err_o (wbs2_err_o),
|
| 1798 |
|
|
.wbs2_rty_o (wbs2_rty_o),
|
| 1799 |
|
|
.wbs2_dat_o (wbs2_dat_o[dw-1:0]),
|
| 1800 |
|
|
`endif
|
| 1801 |
|
|
`ifdef WBS3
|
| 1802 |
|
|
.wbs3_ack_o (wbs3_ack_o),
|
| 1803 |
|
|
.wbs3_err_o (wbs3_err_o),
|
| 1804 |
|
|
.wbs3_rty_o (wbs3_rty_o),
|
| 1805 |
|
|
.wbs3_dat_o (wbs3_dat_o[dw-1:0]),
|
| 1806 |
|
|
`endif
|
| 1807 |
|
|
`ifdef WBS4
|
| 1808 |
|
|
.wbs4_ack_o (wbs4_ack_o),
|
| 1809 |
|
|
.wbs4_err_o (wbs4_err_o),
|
| 1810 |
|
|
.wbs4_rty_o (wbs4_rty_o),
|
| 1811 |
|
|
.wbs4_dat_o (wbs4_dat_o[dw-1:0]),
|
| 1812 |
|
|
`endif
|
| 1813 |
|
|
`ifdef WBS5
|
| 1814 |
|
|
.wbs5_ack_o (wbs5_ack_o),
|
| 1815 |
|
|
.wbs5_err_o (wbs5_err_o),
|
| 1816 |
|
|
.wbs5_rty_o (wbs5_rty_o),
|
| 1817 |
|
|
.wbs5_dat_o (wbs5_dat_o[dw-1:0]),
|
| 1818 |
|
|
`endif
|
| 1819 |
|
|
`ifdef WBS6
|
| 1820 |
|
|
.wbs6_ack_o (wbs6_ack_o),
|
| 1821 |
|
|
.wbs6_err_o (wbs6_err_o),
|
| 1822 |
|
|
.wbs6_rty_o (wbs6_rty_o),
|
| 1823 |
|
|
.wbs6_dat_o (wbs6_dat_o[dw-1:0]),
|
| 1824 |
|
|
`endif
|
| 1825 |
|
|
`ifdef WBS7
|
| 1826 |
|
|
.wbs7_ack_o (wbs7_ack_o),
|
| 1827 |
|
|
.wbs7_err_o (wbs7_err_o),
|
| 1828 |
|
|
.wbs7_rty_o (wbs7_rty_o),
|
| 1829 |
|
|
.wbs7_dat_o (wbs7_dat_o[dw-1:0]),
|
| 1830 |
|
|
`endif
|
| 1831 |
|
|
.wbm_slave_sel (wbm5_slave_sel),
|
| 1832 |
|
|
.wb_clk (wb_clk),
|
| 1833 |
|
|
.wb_rst (wb_rst));
|
| 1834 |
|
|
`endif
|
| 1835 |
|
|
|
| 1836 |
|
|
endmodule // wb_b3_switch
|
| 1837 |
|
|
|
| 1838 |
|
|
// Master selection logic
|
| 1839 |
|
|
module wb_b3_switch_slave_sel
|
| 1840 |
|
|
(
|
| 1841 |
|
|
wbm0_adr_o, wbm0_cyc_o,
|
| 1842 |
|
|
`ifdef WBM1
|
| 1843 |
|
|
wbm1_adr_o, wbm1_cyc_o,
|
| 1844 |
|
|
`endif
|
| 1845 |
|
|
`ifdef WBM2
|
| 1846 |
|
|
wbm2_adr_o, wbm2_cyc_o,
|
| 1847 |
|
|
`endif
|
| 1848 |
|
|
`ifdef WBM3
|
| 1849 |
|
|
wbm3_adr_o, wbm3_cyc_o,
|
| 1850 |
|
|
`endif
|
| 1851 |
|
|
`ifdef WBM4
|
| 1852 |
|
|
wbm4_adr_o, wbm4_cyc_o,
|
| 1853 |
|
|
`endif
|
| 1854 |
|
|
`ifdef WBM5
|
| 1855 |
|
|
wbm5_adr_o, wbm5_cyc_o,
|
| 1856 |
|
|
`endif
|
| 1857 |
|
|
|
| 1858 |
|
|
wbs_master_sel, wbs_master_sel_new,
|
| 1859 |
|
|
|
| 1860 |
|
|
wb_clk, wb_rst);
|
| 1861 |
|
|
|
| 1862 |
|
|
parameter dw = 32;
|
| 1863 |
|
|
parameter aw = 32;
|
| 1864 |
|
|
|
| 1865 |
|
|
parameter num_masters = 4;
|
| 1866 |
|
|
parameter slave_sel_bit_width = 4;
|
| 1867 |
|
|
parameter slave_addr = 4'hf;
|
| 1868 |
|
|
|
| 1869 |
|
|
|
| 1870 |
|
|
input [aw-1:0] wbm0_adr_o;input wbm0_cyc_o;
|
| 1871 |
|
|
`ifdef WBM1
|
| 1872 |
|
|
input [aw-1:0] wbm1_adr_o;input wbm1_cyc_o;
|
| 1873 |
|
|
`endif
|
| 1874 |
|
|
`ifdef WBM2
|
| 1875 |
|
|
input [aw-1:0] wbm2_adr_o;input wbm2_cyc_o;
|
| 1876 |
|
|
`endif
|
| 1877 |
|
|
`ifdef WBM3
|
| 1878 |
|
|
input [aw-1:0] wbm3_adr_o;input wbm3_cyc_o;
|
| 1879 |
|
|
`endif
|
| 1880 |
|
|
`ifdef WBM4
|
| 1881 |
|
|
input [aw-1:0] wbm4_adr_o;input wbm4_cyc_o;
|
| 1882 |
|
|
`endif
|
| 1883 |
|
|
`ifdef WBM5
|
| 1884 |
|
|
input [aw-1:0] wbm5_adr_o;input wbm5_cyc_o;
|
| 1885 |
|
|
`endif
|
| 1886 |
|
|
|
| 1887 |
|
|
input wb_clk, wb_rst;
|
| 1888 |
|
|
|
| 1889 |
|
|
output reg [num_masters - 1:0] wbs_master_sel;
|
| 1890 |
|
|
output wbs_master_sel_new;
|
| 1891 |
|
|
|
| 1892 |
|
|
reg [num_masters - 1:0] wbs_master_sel_r;
|
| 1893 |
|
|
|
| 1894 |
|
|
reg [num_masters - 1:0] last_master;
|
| 1895 |
|
|
|
| 1896 |
|
|
wire wbm0_req;
|
| 1897 |
|
|
assign wbm0_req = (wbm0_adr_o[aw-1:(aw-(slave_sel_bit_width))] == slave_addr) &
|
| 1898 |
|
|
wbm0_cyc_o;
|
| 1899 |
|
|
`ifdef WBM1
|
| 1900 |
|
|
wire wbm1_req;
|
| 1901 |
|
|
assign wbm1_req = (wbm1_adr_o[aw-1:(aw-(slave_sel_bit_width))] == slave_addr) &
|
| 1902 |
|
|
wbm1_cyc_o;
|
| 1903 |
|
|
`endif
|
| 1904 |
|
|
|
| 1905 |
|
|
`ifdef WBM2
|
| 1906 |
|
|
wire wbm2_req;
|
| 1907 |
|
|
assign wbm2_req = (wbm2_adr_o[aw-1:(aw-(slave_sel_bit_width))] == slave_addr) &
|
| 1908 |
|
|
wbm2_cyc_o;
|
| 1909 |
|
|
`endif
|
| 1910 |
|
|
|
| 1911 |
|
|
`ifdef WBM3
|
| 1912 |
|
|
wire wbm3_req;
|
| 1913 |
|
|
assign wbm3_req = (wbm3_adr_o[aw-1:(aw-(slave_sel_bit_width))] == slave_addr) &
|
| 1914 |
|
|
wbm3_cyc_o;
|
| 1915 |
|
|
`endif
|
| 1916 |
|
|
`ifdef WBM4
|
| 1917 |
|
|
wire wbm4_req;
|
| 1918 |
|
|
assign wbm4_req = (wbm4_adr_o[aw-1:(aw-(slave_sel_bit_width))] == slave_addr) &
|
| 1919 |
|
|
wbm4_cyc_o;
|
| 1920 |
|
|
`endif
|
| 1921 |
|
|
`ifdef WBM5
|
| 1922 |
|
|
wire wbm5_req;
|
| 1923 |
|
|
assign wbm5_req = (wbm5_adr_o[aw-1:(aw-(slave_sel_bit_width))] == slave_addr) &
|
| 1924 |
|
|
wbm5_cyc_o;
|
| 1925 |
|
|
`endif
|
| 1926 |
|
|
|
| 1927 |
|
|
// Generate wires to check if there's other requests than our own, to enable us to stop
|
| 1928 |
|
|
// any particular master hogging the bus
|
| 1929 |
|
|
`ifdef WBM5
|
| 1930 |
|
|
wire wbm0_other_reqs;
|
| 1931 |
|
|
assign wbm0_other_reqs = (wbm1_req | wbm2_req | wbm3_req | wbm4_req | wbm5_req);
|
| 1932 |
|
|
wire wbm1_other_reqs;
|
| 1933 |
|
|
assign wbm1_other_reqs = (wbm0_req | wbm2_req | wbm3_req | wbm4_req | wbm5_req);
|
| 1934 |
|
|
wire wbm2_other_reqs;
|
| 1935 |
|
|
assign wbm2_other_reqs = (wbm1_req | wbm0_req | wbm3_req | wbm4_req | wbm5_req);
|
| 1936 |
|
|
wire wbm3_other_reqs;
|
| 1937 |
|
|
assign wbm3_other_reqs = (wbm1_req | wbm2_req | wbm0_req | wbm4_req | wbm5_req);
|
| 1938 |
|
|
wire wbm4_other_reqs;
|
| 1939 |
|
|
assign wbm4_other_reqs = (wbm1_req | wbm2_req | wbm0_req | wbm3_req | wbm5_req);
|
| 1940 |
|
|
wire wbm5_other_reqs;
|
| 1941 |
|
|
assign wbm5_other_reqs = (wbm1_req | wbm2_req | wbm0_req | wbm3_req | wbm4_req);
|
| 1942 |
|
|
`else
|
| 1943 |
|
|
`ifdef WBM4
|
| 1944 |
|
|
wire wbm0_other_reqs;
|
| 1945 |
|
|
assign wbm0_other_reqs = (wbm1_req | wbm2_req | wbm3_req | wbm4_req);
|
| 1946 |
|
|
wire wbm1_other_reqs;
|
| 1947 |
|
|
assign wbm1_other_reqs = (wbm0_req | wbm2_req | wbm3_req | wbm4_req);
|
| 1948 |
|
|
wire wbm2_other_reqs;
|
| 1949 |
|
|
assign wbm2_other_reqs = (wbm1_req | wbm0_req | wbm3_req | wbm4_req);
|
| 1950 |
|
|
wire wbm3_other_reqs;
|
| 1951 |
|
|
assign wbm3_other_reqs = (wbm1_req | wbm2_req | wbm0_req | wbm4_req);
|
| 1952 |
|
|
wire wbm4_other_reqs;
|
| 1953 |
|
|
assign wbm4_other_reqs = (wbm1_req | wbm2_req | wbm0_req | wbm3_req);
|
| 1954 |
|
|
`else
|
| 1955 |
|
|
`ifdef WBM3
|
| 1956 |
|
|
wire wbm0_other_reqs;
|
| 1957 |
|
|
assign wbm0_other_reqs = (wbm1_req | wbm2_req | wbm3_req);
|
| 1958 |
|
|
wire wbm1_other_reqs;
|
| 1959 |
|
|
assign wbm1_other_reqs = (wbm0_req | wbm2_req | wbm3_req);
|
| 1960 |
|
|
wire wbm2_other_reqs;
|
| 1961 |
|
|
assign wbm2_other_reqs = (wbm1_req | wbm0_req | wbm3_req);
|
| 1962 |
|
|
wire wbm3_other_reqs;
|
| 1963 |
|
|
assign wbm3_other_reqs = (wbm1_req | wbm2_req | wbm0_req);
|
| 1964 |
|
|
`else
|
| 1965 |
|
|
`ifdef WBM2
|
| 1966 |
|
|
wire wbm0_other_reqs;
|
| 1967 |
|
|
assign wbm0_other_reqs = (wbm1_req | wbm2_req);
|
| 1968 |
|
|
wire wbm1_other_reqs;
|
| 1969 |
|
|
assign wbm1_other_reqs = (wbm0_req | wbm2_req);
|
| 1970 |
|
|
wire wbm2_other_reqs;
|
| 1971 |
|
|
assign wbm2_other_reqs = (wbm1_req | wbm0_req);
|
| 1972 |
|
|
`else
|
| 1973 |
|
|
`ifdef WBM1
|
| 1974 |
|
|
wire wbm0_other_reqs;
|
| 1975 |
|
|
assign wbm0_other_reqs = (wbm1_req);
|
| 1976 |
|
|
wire wbm1_other_reqs;
|
| 1977 |
|
|
assign wbm1_other_reqs = (wbm0_req);
|
| 1978 |
|
|
`else
|
| 1979 |
|
|
wire wbm0_other_reqs;
|
| 1980 |
|
|
assign wbm0_other_reqs = 0;
|
| 1981 |
|
|
`endif
|
| 1982 |
|
|
`endif // !`ifdef WBM2
|
| 1983 |
|
|
`endif // !`ifdef WBM3
|
| 1984 |
|
|
`endif // !`ifdef WBM4
|
| 1985 |
|
|
`endif // !`ifdef WBM5
|
| 1986 |
|
|
|
| 1987 |
|
|
// Address match logic - number of bits from the MSbit we used for address
|
| 1988 |
|
|
// selection. Typically just the top nibble
|
| 1989 |
|
|
always @(posedge wb_clk)
|
| 1990 |
|
|
if (wb_rst)
|
| 1991 |
|
|
begin
|
| 1992 |
|
|
wbs_master_sel <= 0;
|
| 1993 |
|
|
last_master <= 0;
|
| 1994 |
|
|
end // if (wb_rst)
|
| 1995 |
|
|
else
|
| 1996 |
|
|
begin
|
| 1997 |
|
|
if ((!(|wbs_master_sel)) & (!(|wbs_master_sel_r)))
|
| 1998 |
|
|
// Make sure it's cleared for a couple cycles
|
| 1999 |
|
|
begin
|
| 2000 |
|
|
// check for a new master request
|
| 2001 |
|
|
if (wbm0_req & ((!last_master[0]) | (last_master[0] & !wbm0_other_reqs)))
|
| 2002 |
|
|
begin
|
| 2003 |
|
|
wbs_master_sel[0] <= 1;
|
| 2004 |
|
|
last_master <= 1;
|
| 2005 |
|
|
end
|
| 2006 |
|
|
`ifdef WBM1
|
| 2007 |
|
|
else if (wbm1_req & ((!last_master[1]) | (last_master[1] & !wbm1_other_reqs)))
|
| 2008 |
|
|
begin
|
| 2009 |
|
|
wbs_master_sel[1] <= 1;
|
| 2010 |
|
|
last_master <= 2;
|
| 2011 |
|
|
end
|
| 2012 |
|
|
`endif
|
| 2013 |
|
|
`ifdef WBM2
|
| 2014 |
|
|
else if (wbm2_req & ((!last_master[2]) | (last_master[2] & !wbm2_other_reqs)))
|
| 2015 |
|
|
begin
|
| 2016 |
|
|
wbs_master_sel[2] <= 1;
|
| 2017 |
|
|
last_master <= 4;
|
| 2018 |
|
|
end
|
| 2019 |
|
|
`endif
|
| 2020 |
|
|
`ifdef WBM3
|
| 2021 |
|
|
else if (wbm3_req & ((!last_master[3]) | (last_master[3] & !wbm3_other_reqs)))
|
| 2022 |
|
|
begin
|
| 2023 |
|
|
wbs_master_sel[3] <= 1;
|
| 2024 |
|
|
last_master <= 8;
|
| 2025 |
|
|
end
|
| 2026 |
|
|
`endif
|
| 2027 |
|
|
`ifdef WBM4
|
| 2028 |
|
|
else if (wbm4_req & ((!last_master[4]) | (last_master[4] & !wbm4_other_reqs)))
|
| 2029 |
|
|
begin
|
| 2030 |
|
|
wbs_master_sel[4] <= 1;
|
| 2031 |
|
|
last_master <= 16;
|
| 2032 |
|
|
end
|
| 2033 |
|
|
`endif
|
| 2034 |
|
|
`ifdef WBM5
|
| 2035 |
|
|
else if (wbm5_req & ((!last_master[5]) | (last_master[5] & !wbm5_other_reqs)))
|
| 2036 |
|
|
begin
|
| 2037 |
|
|
wbs_master_sel[5] <= 1;
|
| 2038 |
|
|
last_master <= 32;
|
| 2039 |
|
|
end
|
| 2040 |
|
|
`endif
|
| 2041 |
|
|
end // if (!(|wbs_master_sel))
|
| 2042 |
|
|
else
|
| 2043 |
|
|
begin
|
| 2044 |
|
|
// Poll the cycle of the selected master until it goes low,
|
| 2045 |
|
|
// at which point we select another master
|
| 2046 |
|
|
if (wbs_master_sel[0] & !wbm0_cyc_o)
|
| 2047 |
|
|
wbs_master_sel[0] <= 0;
|
| 2048 |
|
|
`ifdef WBM1
|
| 2049 |
|
|
if (wbs_master_sel[1] & !wbm1_cyc_o)
|
| 2050 |
|
|
wbs_master_sel[1] <= 0;
|
| 2051 |
|
|
`endif
|
| 2052 |
|
|
`ifdef WBM2
|
| 2053 |
|
|
if (wbs_master_sel[2] & !wbm2_cyc_o)
|
| 2054 |
|
|
wbs_master_sel[2] <= 0;
|
| 2055 |
|
|
`endif
|
| 2056 |
|
|
`ifdef WBM3
|
| 2057 |
|
|
if (wbs_master_sel[3] & !wbm3_cyc_o)
|
| 2058 |
|
|
wbs_master_sel[3] <= 0;
|
| 2059 |
|
|
`endif
|
| 2060 |
|
|
`ifdef WBM4
|
| 2061 |
|
|
if (wbs_master_sel[4] & !wbm4_cyc_o)
|
| 2062 |
|
|
wbs_master_sel[4] <= 0;
|
| 2063 |
|
|
`endif
|
| 2064 |
|
|
`ifdef WBM5
|
| 2065 |
|
|
if (wbs_master_sel[5] & !wbm5_cyc_o)
|
| 2066 |
|
|
wbs_master_sel[5] <= 0;
|
| 2067 |
|
|
`endif
|
| 2068 |
|
|
end // else: !if(!(|wbs_master_sel))
|
| 2069 |
|
|
end // else: !if(wb_rst)
|
| 2070 |
|
|
|
| 2071 |
|
|
always @(posedge wb_clk)
|
| 2072 |
|
|
wbs_master_sel_r <= wbs_master_sel;
|
| 2073 |
|
|
|
| 2074 |
|
|
`define WBS_MASTER_DESELECT_ALSO
|
| 2075 |
|
|
`ifdef WBS_MASTER_DESELECT_ALSO
|
| 2076 |
|
|
// Also pulse for deselection of master
|
| 2077 |
|
|
assign wbs_master_sel_new = ((|wbs_master_sel) & !(|wbs_master_sel_r)) |
|
| 2078 |
|
|
(!(|wbs_master_sel)) & (|wbs_master_sel_r);
|
| 2079 |
|
|
`else
|
| 2080 |
|
|
// Pulse for just new select of master by slave
|
| 2081 |
|
|
assign wbs_master_sel_new = (|wbs_master_sel) & !(|wbs_master_sel_r);
|
| 2082 |
|
|
`endif
|
| 2083 |
|
|
|
| 2084 |
|
|
endmodule // wb_b3_switch_slave_sel
|
| 2085 |
|
|
|
| 2086 |
|
|
|
| 2087 |
|
|
// Detect which slave has selected this master to control its bus
|
| 2088 |
|
|
// Need this to determine which slave's output to mux onto which master's inputs
|
| 2089 |
|
|
module wb_b3_switch_master_detect_slave_sel
|
| 2090 |
|
|
(
|
| 2091 |
|
|
output reg [`NUM_SLAVES-1:0] wbm_slave_sel,
|
| 2092 |
|
|
|
| 2093 |
|
|
input [`NUM_MASTERS-1:0] wbs0_master_sel,
|
| 2094 |
|
|
input wbs0_master_sel_new,
|
| 2095 |
|
|
`ifdef WBS1
|
| 2096 |
|
|
input [`NUM_MASTERS-1:0] wbs1_master_sel,
|
| 2097 |
|
|
input wbs1_master_sel_new,
|
| 2098 |
|
|
`endif
|
| 2099 |
|
|
`ifdef WBS2
|
| 2100 |
|
|
input [`NUM_MASTERS-1:0] wbs2_master_sel,
|
| 2101 |
|
|
input wbs2_master_sel_new,
|
| 2102 |
|
|
`endif
|
| 2103 |
|
|
`ifdef WBS3
|
| 2104 |
|
|
input [`NUM_MASTERS-1:0] wbs3_master_sel,
|
| 2105 |
|
|
input wbs3_master_sel_new,
|
| 2106 |
|
|
`endif
|
| 2107 |
|
|
`ifdef WBS4
|
| 2108 |
|
|
input [`NUM_MASTERS-1:0] wbs4_master_sel,
|
| 2109 |
|
|
input wbs4_master_sel_new,
|
| 2110 |
|
|
`endif
|
| 2111 |
|
|
`ifdef WBS5
|
| 2112 |
|
|
input [`NUM_MASTERS-1:0] wbs5_master_sel,
|
| 2113 |
|
|
input wbs5_master_sel_new,
|
| 2114 |
|
|
`endif
|
| 2115 |
|
|
`ifdef WBS6
|
| 2116 |
|
|
input [`NUM_MASTERS-1:0] wbs6_master_sel,
|
| 2117 |
|
|
input wbs6_master_sel_new,
|
| 2118 |
|
|
`endif
|
| 2119 |
|
|
`ifdef WBS7
|
| 2120 |
|
|
input [`NUM_MASTERS-1:0] wbs7_master_sel,
|
| 2121 |
|
|
input wbs7_master_sel_new,
|
| 2122 |
|
|
`endif
|
| 2123 |
|
|
input wb_clk, wb_rst
|
| 2124 |
|
|
);
|
| 2125 |
|
|
|
| 2126 |
|
|
parameter slave_bit = 0;
|
| 2127 |
|
|
|
| 2128 |
|
|
// Master's slave select detection logic (depends on which slave has
|
| 2129 |
|
|
// selected it)
|
| 2130 |
|
|
always @(posedge wb_clk)
|
| 2131 |
|
|
if (wb_rst)
|
| 2132 |
|
|
wbm_slave_sel <= 0;
|
| 2133 |
|
|
else
|
| 2134 |
|
|
if (wbs0_master_sel_new
|
| 2135 |
|
|
`ifdef WBS1
|
| 2136 |
|
|
| wbs1_master_sel_new
|
| 2137 |
|
|
`endif
|
| 2138 |
|
|
`ifdef WBS2
|
| 2139 |
|
|
| wbs2_master_sel_new
|
| 2140 |
|
|
`endif
|
| 2141 |
|
|
`ifdef WBS3
|
| 2142 |
|
|
| wbs3_master_sel_new
|
| 2143 |
|
|
`endif
|
| 2144 |
|
|
`ifdef WBS4
|
| 2145 |
|
|
| wbs4_master_sel_new
|
| 2146 |
|
|
`endif
|
| 2147 |
|
|
`ifdef WBS5
|
| 2148 |
|
|
| wbs5_master_sel_new
|
| 2149 |
|
|
`endif
|
| 2150 |
|
|
`ifdef WBS6
|
| 2151 |
|
|
| wbs6_master_sel_new
|
| 2152 |
|
|
`endif
|
| 2153 |
|
|
`ifdef WBS7
|
| 2154 |
|
|
| wbs7_master_sel_new
|
| 2155 |
|
|
`endif
|
| 2156 |
|
|
)
|
| 2157 |
|
|
// Figure out which slave is tied to master0
|
| 2158 |
|
|
wbm_slave_sel <=
|
| 2159 |
|
|
`ifdef WBS7
|
| 2160 |
|
|
{wbs7_master_sel[slave_bit], wbs6_master_sel[slave_bit],
|
| 2161 |
|
|
wbs5_master_sel[slave_bit], wbs4_master_sel[slave_bit],
|
| 2162 |
|
|
wbs3_master_sel[slave_bit], wbs2_master_sel[slave_bit],
|
| 2163 |
|
|
wbs1_master_sel[slave_bit], wbs0_master_sel[slave_bit]};
|
| 2164 |
|
|
`else
|
| 2165 |
|
|
`ifdef WBS6
|
| 2166 |
|
|
{wbs6_master_sel[slave_bit], wbs5_master_sel[slave_bit],
|
| 2167 |
|
|
wbs4_master_sel[slave_bit], wbs3_master_sel[slave_bit],
|
| 2168 |
|
|
wbs2_master_sel[slave_bit], wbs1_master_sel[slave_bit],
|
| 2169 |
|
|
wbs0_master_sel[slave_bit]};
|
| 2170 |
|
|
`else
|
| 2171 |
|
|
`ifdef WBS5
|
| 2172 |
|
|
{wbs5_master_sel[slave_bit], wbs4_master_sel[slave_bit],
|
| 2173 |
|
|
wbs3_master_sel[slave_bit], wbs2_master_sel[slave_bit],
|
| 2174 |
|
|
wbs1_master_sel[slave_bit], wbs0_master_sel[slave_bit]};
|
| 2175 |
|
|
`else
|
| 2176 |
|
|
`ifdef WBS4
|
| 2177 |
|
|
{wbs4_master_sel[slave_bit], wbs3_master_sel[slave_bit],
|
| 2178 |
|
|
wbs2_master_sel[slave_bit], wbs1_master_sel[slave_bit],
|
| 2179 |
|
|
wbs0_master_sel[slave_bit]};
|
| 2180 |
|
|
`else
|
| 2181 |
|
|
`ifdef WBS3
|
| 2182 |
|
|
{wbs3_master_sel[slave_bit], wbs2_master_sel[slave_bit],
|
| 2183 |
|
|
wbs1_master_sel[slave_bit], wbs0_master_sel[slave_bit]};
|
| 2184 |
|
|
`else
|
| 2185 |
|
|
`ifdef WBS2
|
| 2186 |
|
|
{wbs2_master_sel[slave_bit], wbs1_master_sel[slave_bit],
|
| 2187 |
|
|
wbs0_master_sel[slave_bit]};
|
| 2188 |
|
|
`else
|
| 2189 |
|
|
`ifdef WBS1
|
| 2190 |
|
|
{wbs1_master_sel[slave_bit], wbs0_master_sel[slave_bit]};
|
| 2191 |
|
|
`else
|
| 2192 |
|
|
wbs0_master_sel[slave_bit];
|
| 2193 |
|
|
`endif
|
| 2194 |
|
|
`endif
|
| 2195 |
|
|
`endif // !`ifdef WBS3
|
| 2196 |
|
|
`endif // !`ifdef WBS4
|
| 2197 |
|
|
`endif // !`ifdef WBS5
|
| 2198 |
|
|
`endif // !`ifdef WBS6
|
| 2199 |
|
|
`endif // !`ifdef WBS7
|
| 2200 |
|
|
|
| 2201 |
|
|
endmodule // wb_b3_switch_master_detect_slave_sel
|
| 2202 |
|
|
|
| 2203 |
|
|
// All signals FROM master coming in, Muxing them to the signals TO the slave
|
| 2204 |
|
|
module wb_b3_switch_slave_out_mux
|
| 2205 |
|
|
(
|
| 2206 |
|
|
// Master ports
|
| 2207 |
|
|
wbm0_adr_o, wbm0_bte_o, wbm0_cti_o, wbm0_cyc_o, wbm0_dat_o, wbm0_sel_o,
|
| 2208 |
|
|
wbm0_stb_o, wbm0_we_o,
|
| 2209 |
|
|
`ifdef WBM1
|
| 2210 |
|
|
wbm1_adr_o, wbm1_bte_o, wbm1_cti_o, wbm1_cyc_o, wbm1_dat_o, wbm1_sel_o,
|
| 2211 |
|
|
wbm1_stb_o, wbm1_we_o,
|
| 2212 |
|
|
`endif
|
| 2213 |
|
|
`ifdef WBM2
|
| 2214 |
|
|
wbm2_adr_o, wbm2_bte_o, wbm2_cti_o, wbm2_cyc_o, wbm2_dat_o, wbm2_sel_o,
|
| 2215 |
|
|
wbm2_stb_o, wbm2_we_o,
|
| 2216 |
|
|
`endif
|
| 2217 |
|
|
`ifdef WBM3
|
| 2218 |
|
|
wbm3_adr_o, wbm3_bte_o, wbm3_cti_o, wbm3_cyc_o, wbm3_dat_o, wbm3_sel_o,
|
| 2219 |
|
|
wbm3_stb_o, wbm3_we_o,
|
| 2220 |
|
|
`endif
|
| 2221 |
|
|
`ifdef WBM4
|
| 2222 |
|
|
wbm4_adr_o, wbm4_bte_o, wbm4_cti_o, wbm4_cyc_o, wbm4_dat_o, wbm4_sel_o,
|
| 2223 |
|
|
wbm4_stb_o, wbm4_we_o,
|
| 2224 |
|
|
`endif
|
| 2225 |
|
|
`ifdef WBM5
|
| 2226 |
|
|
wbm5_adr_o, wbm5_bte_o, wbm5_cti_o, wbm5_cyc_o, wbm5_dat_o, wbm5_sel_o,
|
| 2227 |
|
|
wbm5_stb_o, wbm5_we_o,
|
| 2228 |
|
|
`endif
|
| 2229 |
|
|
|
| 2230 |
|
|
// Slave ports
|
| 2231 |
|
|
wbs_adr_i, wbs_bte_i, wbs_cti_i, wbs_cyc_i, wbs_dat_i, wbs_sel_i,
|
| 2232 |
|
|
wbs_stb_i, wbs_we_i,
|
| 2233 |
|
|
|
| 2234 |
|
|
wbs_master_sel,
|
| 2235 |
|
|
|
| 2236 |
|
|
wb_clk, wb_rst
|
| 2237 |
|
|
);
|
| 2238 |
|
|
|
| 2239 |
|
|
|
| 2240 |
|
|
parameter dw = 32;
|
| 2241 |
|
|
parameter aw = 32;
|
| 2242 |
|
|
parameter num_masters = `NUM_MASTERS;
|
| 2243 |
|
|
|
| 2244 |
|
|
input [aw-1:0] wbm0_adr_o;input [1:0] wbm0_bte_o;input [2:0] wbm0_cti_o;input wbm0_cyc_o;input [dw-1:0] wbm0_dat_o;input [3:0] wbm0_sel_o;input wbm0_stb_o;input wbm0_we_o;
|
| 2245 |
|
|
`ifdef WBM1
|
| 2246 |
|
|
input [aw-1:0] wbm1_adr_o;input [1:0] wbm1_bte_o;input [2:0] wbm1_cti_o;input wbm1_cyc_o;input [dw-1:0] wbm1_dat_o;input [3:0] wbm1_sel_o;input wbm1_stb_o;input wbm1_we_o;
|
| 2247 |
|
|
`endif
|
| 2248 |
|
|
`ifdef WBM2
|
| 2249 |
|
|
input [aw-1:0] wbm2_adr_o;input [1:0] wbm2_bte_o;input [2:0] wbm2_cti_o;input wbm2_cyc_o;input [dw-1:0] wbm2_dat_o;input [3:0] wbm2_sel_o;input wbm2_stb_o;input wbm2_we_o;
|
| 2250 |
|
|
`endif
|
| 2251 |
|
|
`ifdef WBM3
|
| 2252 |
|
|
input [aw-1:0] wbm3_adr_o;input [1:0] wbm3_bte_o;input [2:0] wbm3_cti_o;input wbm3_cyc_o;input [dw-1:0] wbm3_dat_o;input [3:0] wbm3_sel_o;input wbm3_stb_o;input wbm3_we_o;
|
| 2253 |
|
|
`endif
|
| 2254 |
|
|
`ifdef WBM4
|
| 2255 |
|
|
input [aw-1:0] wbm4_adr_o;input [1:0] wbm4_bte_o;input [2:0] wbm4_cti_o;input wbm4_cyc_o;input [dw-1:0] wbm4_dat_o;input [3:0] wbm4_sel_o;input wbm4_stb_o;input wbm4_we_o;
|
| 2256 |
|
|
`endif
|
| 2257 |
|
|
`ifdef WBM5
|
| 2258 |
|
|
input [aw-1:0] wbm5_adr_o;input [1:0] wbm5_bte_o;input [2:0] wbm5_cti_o;input wbm5_cyc_o;input [dw-1:0] wbm5_dat_o;input [3:0] wbm5_sel_o;input wbm5_stb_o;input wbm5_we_o;
|
| 2259 |
|
|
`endif
|
| 2260 |
|
|
|
| 2261 |
|
|
output [aw-1:0] wbs_adr_i;output [1:0] wbs_bte_i;output [2:0] wbs_cti_i;output wbs_cyc_i;output [dw-1:0] wbs_dat_i;output [3:0] wbs_sel_i;output wbs_stb_i;output wbs_we_i;
|
| 2262 |
|
|
|
| 2263 |
|
|
input [num_masters-1:0] wbs_master_sel;
|
| 2264 |
|
|
|
| 2265 |
|
|
input wb_clk, wb_rst;
|
| 2266 |
|
|
|
| 2267 |
|
|
assign wbs_adr_i = (wbs_master_sel[0]) ? wbm0_adr_o :
|
| 2268 |
|
|
`ifdef WBM1
|
| 2269 |
|
|
(wbs_master_sel[1]) ? wbm1_adr_o :
|
| 2270 |
|
|
`endif
|
| 2271 |
|
|
`ifdef WBM2
|
| 2272 |
|
|
(wbs_master_sel[2]) ? wbm2_adr_o :
|
| 2273 |
|
|
`endif
|
| 2274 |
|
|
`ifdef WBM3
|
| 2275 |
|
|
(wbs_master_sel[3]) ? wbm3_adr_o :
|
| 2276 |
|
|
`endif
|
| 2277 |
|
|
`ifdef WBM4
|
| 2278 |
|
|
(wbs_master_sel[4]) ? wbm4_adr_o :
|
| 2279 |
|
|
`endif
|
| 2280 |
|
|
`ifdef WBM5
|
| 2281 |
|
|
(wbs_master_sel[5]) ? wbm5_adr_o :
|
| 2282 |
|
|
`endif
|
| 2283 |
|
|
0;
|
| 2284 |
|
|
assign wbs_bte_i = (wbs_master_sel[0]) ? wbm0_bte_o :
|
| 2285 |
|
|
`ifdef WBM1
|
| 2286 |
|
|
(wbs_master_sel[1]) ? wbm1_bte_o :
|
| 2287 |
|
|
`endif
|
| 2288 |
|
|
`ifdef WBM2
|
| 2289 |
|
|
(wbs_master_sel[2]) ? wbm2_bte_o :
|
| 2290 |
|
|
`endif
|
| 2291 |
|
|
`ifdef WBM3
|
| 2292 |
|
|
(wbs_master_sel[3]) ? wbm3_bte_o :
|
| 2293 |
|
|
`endif
|
| 2294 |
|
|
`ifdef WBM4
|
| 2295 |
|
|
(wbs_master_sel[4]) ? wbm4_bte_o :
|
| 2296 |
|
|
`endif
|
| 2297 |
|
|
`ifdef WBM5
|
| 2298 |
|
|
(wbs_master_sel[5]) ? wbm5_bte_o :
|
| 2299 |
|
|
`endif
|
| 2300 |
|
|
0;
|
| 2301 |
|
|
assign wbs_cti_i = (wbs_master_sel[0]) ? wbm0_cti_o :
|
| 2302 |
|
|
`ifdef WBM1
|
| 2303 |
|
|
(wbs_master_sel[1]) ? wbm1_cti_o :
|
| 2304 |
|
|
`endif
|
| 2305 |
|
|
`ifdef WBM2
|
| 2306 |
|
|
(wbs_master_sel[2]) ? wbm2_cti_o :
|
| 2307 |
|
|
`endif
|
| 2308 |
|
|
`ifdef WBM3
|
| 2309 |
|
|
(wbs_master_sel[3]) ? wbm3_cti_o :
|
| 2310 |
|
|
`endif
|
| 2311 |
|
|
`ifdef WBM4
|
| 2312 |
|
|
(wbs_master_sel[4]) ? wbm4_cti_o :
|
| 2313 |
|
|
`endif
|
| 2314 |
|
|
`ifdef WBM5
|
| 2315 |
|
|
(wbs_master_sel[5]) ? wbm5_cti_o :
|
| 2316 |
|
|
`endif
|
| 2317 |
|
|
0;
|
| 2318 |
|
|
|
| 2319 |
|
|
assign wbs_cyc_i = (wbs_master_sel[0]) ? wbm0_cyc_o :
|
| 2320 |
|
|
`ifdef WBM1
|
| 2321 |
|
|
(wbs_master_sel[1]) ? wbm1_cyc_o :
|
| 2322 |
|
|
`endif
|
| 2323 |
|
|
`ifdef WBM2
|
| 2324 |
|
|
(wbs_master_sel[2]) ? wbm2_cyc_o :
|
| 2325 |
|
|
`endif
|
| 2326 |
|
|
`ifdef WBM3
|
| 2327 |
|
|
(wbs_master_sel[3]) ? wbm3_cyc_o :
|
| 2328 |
|
|
`endif
|
| 2329 |
|
|
`ifdef WBM4
|
| 2330 |
|
|
(wbs_master_sel[4]) ? wbm4_cyc_o :
|
| 2331 |
|
|
`endif
|
| 2332 |
|
|
`ifdef WBM5
|
| 2333 |
|
|
(wbs_master_sel[5]) ? wbm5_cyc_o :
|
| 2334 |
|
|
`endif
|
| 2335 |
|
|
0;
|
| 2336 |
|
|
|
| 2337 |
|
|
assign wbs_dat_i = (wbs_master_sel[0]) ? wbm0_dat_o :
|
| 2338 |
|
|
`ifdef WBM1
|
| 2339 |
|
|
(wbs_master_sel[1]) ? wbm1_dat_o :
|
| 2340 |
|
|
`endif
|
| 2341 |
|
|
`ifdef WBM2
|
| 2342 |
|
|
(wbs_master_sel[2]) ? wbm2_dat_o :
|
| 2343 |
|
|
`endif
|
| 2344 |
|
|
`ifdef WBM3
|
| 2345 |
|
|
(wbs_master_sel[3]) ? wbm3_dat_o :
|
| 2346 |
|
|
`endif
|
| 2347 |
|
|
`ifdef WBM4
|
| 2348 |
|
|
(wbs_master_sel[4]) ? wbm4_dat_o :
|
| 2349 |
|
|
`endif
|
| 2350 |
|
|
`ifdef WBM5
|
| 2351 |
|
|
(wbs_master_sel[5]) ? wbm5_dat_o :
|
| 2352 |
|
|
`endif
|
| 2353 |
|
|
0;
|
| 2354 |
|
|
|
| 2355 |
|
|
assign wbs_sel_i = (wbs_master_sel[0]) ? wbm0_sel_o :
|
| 2356 |
|
|
`ifdef WBM1
|
| 2357 |
|
|
(wbs_master_sel[1]) ? wbm1_sel_o :
|
| 2358 |
|
|
`endif
|
| 2359 |
|
|
`ifdef WBM2
|
| 2360 |
|
|
(wbs_master_sel[2]) ? wbm2_sel_o :
|
| 2361 |
|
|
`endif
|
| 2362 |
|
|
`ifdef WBM3
|
| 2363 |
|
|
(wbs_master_sel[3]) ? wbm3_sel_o :
|
| 2364 |
|
|
`endif
|
| 2365 |
|
|
`ifdef WBM4
|
| 2366 |
|
|
(wbs_master_sel[4]) ? wbm4_sel_o :
|
| 2367 |
|
|
`endif
|
| 2368 |
|
|
`ifdef WBM5
|
| 2369 |
|
|
(wbs_master_sel[5]) ? wbm5_sel_o :
|
| 2370 |
|
|
`endif
|
| 2371 |
|
|
0;
|
| 2372 |
|
|
|
| 2373 |
|
|
assign wbs_stb_i = (wbs_master_sel[0]) ? wbm0_stb_o :
|
| 2374 |
|
|
`ifdef WBM1
|
| 2375 |
|
|
(wbs_master_sel[1]) ? wbm1_stb_o :
|
| 2376 |
|
|
`endif
|
| 2377 |
|
|
`ifdef WBM2
|
| 2378 |
|
|
(wbs_master_sel[2]) ? wbm2_stb_o :
|
| 2379 |
|
|
`endif
|
| 2380 |
|
|
`ifdef WBM3
|
| 2381 |
|
|
(wbs_master_sel[3]) ? wbm3_stb_o :
|
| 2382 |
|
|
`endif
|
| 2383 |
|
|
`ifdef WBM4
|
| 2384 |
|
|
(wbs_master_sel[4]) ? wbm4_stb_o :
|
| 2385 |
|
|
`endif
|
| 2386 |
|
|
`ifdef WBM5
|
| 2387 |
|
|
(wbs_master_sel[5]) ? wbm5_stb_o :
|
| 2388 |
|
|
`endif
|
| 2389 |
|
|
0;
|
| 2390 |
|
|
|
| 2391 |
|
|
assign wbs_we_i = (wbs_master_sel[0]) ? wbm0_we_o :
|
| 2392 |
|
|
`ifdef WBM1
|
| 2393 |
|
|
(wbs_master_sel[1]) ? wbm1_we_o :
|
| 2394 |
|
|
`endif
|
| 2395 |
|
|
`ifdef WBM2
|
| 2396 |
|
|
(wbs_master_sel[2]) ? wbm2_we_o :
|
| 2397 |
|
|
`endif
|
| 2398 |
|
|
`ifdef WBM3
|
| 2399 |
|
|
(wbs_master_sel[3]) ? wbm3_we_o :
|
| 2400 |
|
|
`endif
|
| 2401 |
|
|
`ifdef WBM4
|
| 2402 |
|
|
(wbs_master_sel[4]) ? wbm4_we_o :
|
| 2403 |
|
|
`endif
|
| 2404 |
|
|
`ifdef WBM5
|
| 2405 |
|
|
(wbs_master_sel[5]) ? wbm5_we_o :
|
| 2406 |
|
|
`endif
|
| 2407 |
|
|
0;
|
| 2408 |
|
|
endmodule // wb_b3_switch_slave_out_mux
|
| 2409 |
|
|
|
| 2410 |
|
|
|
| 2411 |
|
|
module wb_b3_switch_master_out_mux
|
| 2412 |
|
|
(
|
| 2413 |
|
|
// Master in, for watchdog
|
| 2414 |
|
|
wbm_stb_o,
|
| 2415 |
|
|
// Master outs
|
| 2416 |
|
|
wbm_ack_i, wbm_err_i, wbm_rty_i, wbm_dat_i,
|
| 2417 |
|
|
// Slave ports
|
| 2418 |
|
|
wbs0_ack_o, wbs0_err_o, wbs0_rty_o, wbs0_dat_o,
|
| 2419 |
|
|
`ifdef WBS1
|
| 2420 |
|
|
wbs1_ack_o, wbs1_err_o, wbs1_rty_o, wbs1_dat_o,
|
| 2421 |
|
|
`endif
|
| 2422 |
|
|
`ifdef WBS2
|
| 2423 |
|
|
wbs2_ack_o, wbs2_err_o, wbs2_rty_o, wbs2_dat_o,
|
| 2424 |
|
|
`endif
|
| 2425 |
|
|
`ifdef WBS3
|
| 2426 |
|
|
wbs3_ack_o, wbs3_err_o, wbs3_rty_o, wbs3_dat_o,
|
| 2427 |
|
|
`endif
|
| 2428 |
|
|
`ifdef WBS4
|
| 2429 |
|
|
wbs4_ack_o, wbs4_err_o, wbs4_rty_o, wbs4_dat_o,
|
| 2430 |
|
|
`endif
|
| 2431 |
|
|
`ifdef WBS5
|
| 2432 |
|
|
wbs5_ack_o, wbs5_err_o, wbs5_rty_o, wbs5_dat_o,
|
| 2433 |
|
|
`endif
|
| 2434 |
|
|
`ifdef WBS6
|
| 2435 |
|
|
wbs6_ack_o, wbs6_err_o, wbs6_rty_o, wbs6_dat_o,
|
| 2436 |
|
|
`endif
|
| 2437 |
|
|
`ifdef WBS7
|
| 2438 |
|
|
wbs7_ack_o, wbs7_err_o, wbs7_rty_o, wbs7_dat_o,
|
| 2439 |
|
|
`endif
|
| 2440 |
|
|
|
| 2441 |
|
|
wbm_slave_sel,
|
| 2442 |
|
|
|
| 2443 |
|
|
wb_clk, wb_rst);
|
| 2444 |
|
|
|
| 2445 |
|
|
// Data and address width parameters
|
| 2446 |
|
|
parameter dw = 32;
|
| 2447 |
|
|
parameter aw = 32;
|
| 2448 |
|
|
input wbm_stb_o;
|
| 2449 |
|
|
|
| 2450 |
|
|
output wbm_ack_i;output wbm_err_i;output wbm_rty_i;output [dw-1:0] wbm_dat_i;
|
| 2451 |
|
|
|
| 2452 |
|
|
input wbs0_ack_o;input wbs0_err_o;input wbs0_rty_o;input [dw-1:0] wbs0_dat_o;
|
| 2453 |
|
|
|
| 2454 |
|
|
`ifdef WBS1
|
| 2455 |
|
|
input wbs1_ack_o;input wbs1_err_o;input wbs1_rty_o;input [dw-1:0] wbs1_dat_o;
|
| 2456 |
|
|
`endif
|
| 2457 |
|
|
`ifdef WBS2
|
| 2458 |
|
|
input wbs2_ack_o;input wbs2_err_o;input wbs2_rty_o;input [dw-1:0] wbs2_dat_o;
|
| 2459 |
|
|
`endif
|
| 2460 |
|
|
`ifdef WBS3
|
| 2461 |
|
|
input wbs3_ack_o;input wbs3_err_o;input wbs3_rty_o;input [dw-1:0] wbs3_dat_o;
|
| 2462 |
|
|
`endif
|
| 2463 |
|
|
`ifdef WBS4
|
| 2464 |
|
|
input wbs4_ack_o;input wbs4_err_o;input wbs4_rty_o;input [dw-1:0] wbs4_dat_o;
|
| 2465 |
|
|
`endif
|
| 2466 |
|
|
`ifdef WBS5
|
| 2467 |
|
|
input wbs5_ack_o;input wbs5_err_o;input wbs5_rty_o;input [dw-1:0] wbs5_dat_o;
|
| 2468 |
|
|
`endif
|
| 2469 |
|
|
`ifdef WBS6
|
| 2470 |
|
|
input wbs6_ack_o;input wbs6_err_o;input wbs6_rty_o;input [dw-1:0] wbs6_dat_o;
|
| 2471 |
|
|
`endif
|
| 2472 |
|
|
`ifdef WBS7
|
| 2473 |
|
|
input wbs7_ack_o;input wbs7_err_o;input wbs7_rty_o;input [dw-1:0] wbs7_dat_o;
|
| 2474 |
|
|
`endif
|
| 2475 |
|
|
|
| 2476 |
|
|
input [`NUM_SLAVES-1:0] wbm_slave_sel;
|
| 2477 |
|
|
|
| 2478 |
|
|
input wb_clk, wb_rst;
|
| 2479 |
|
|
|
| 2480 |
|
|
`ifdef WATCHDOG_TIMER
|
| 2481 |
|
|
parameter watchdog_timer_width = 8;
|
| 2482 |
|
|
reg [watchdog_timer_width-1:0] watchdog_timer;
|
| 2483 |
|
|
reg watchdog_err;
|
| 2484 |
|
|
reg wbm_stb_r, wbm_stb_r2; // Register strobe
|
| 2485 |
|
|
wire wbm_stb_edge; // Detect its edge
|
| 2486 |
|
|
reg wbm_stb_edge_r;
|
| 2487 |
|
|
reg wbm_ack_i_r;
|
| 2488 |
|
|
|
| 2489 |
|
|
|
| 2490 |
|
|
always @(posedge wb_clk)
|
| 2491 |
|
|
wbm_stb_r <= wbm_stb_o;
|
| 2492 |
|
|
|
| 2493 |
|
|
always @(posedge wb_clk)
|
| 2494 |
|
|
wbm_stb_r2 <= wbm_stb_r;
|
| 2495 |
|
|
|
| 2496 |
|
|
always @(posedge wb_clk)
|
| 2497 |
|
|
wbm_stb_edge_r <= wbm_stb_edge;
|
| 2498 |
|
|
|
| 2499 |
|
|
always @(posedge wb_clk)
|
| 2500 |
|
|
wbm_ack_i_r <= wbm_ack_i;
|
| 2501 |
|
|
|
| 2502 |
|
|
|
| 2503 |
|
|
assign wbm_stb_edge = (wbm_stb_r & !wbm_stb_r2);
|
| 2504 |
|
|
|
| 2505 |
|
|
// Counter logic
|
| 2506 |
|
|
always @(posedge wb_clk)
|
| 2507 |
|
|
if (wb_rst) watchdog_timer <= 0;
|
| 2508 |
|
|
else if (wbm_ack_i_r) // When we see an ack, turn off timer
|
| 2509 |
|
|
watchdog_timer <= 0;
|
| 2510 |
|
|
else if (wbm_stb_edge_r) // New access means start timer again
|
| 2511 |
|
|
watchdog_timer <= 1;
|
| 2512 |
|
|
else if (|watchdog_timer) // Continue counting if counter > 0
|
| 2513 |
|
|
watchdog_timer <= watchdog_timer + 1;
|
| 2514 |
|
|
|
| 2515 |
|
|
always @(posedge wb_clk)
|
| 2516 |
|
|
watchdog_err <= (&watchdog_timer);
|
| 2517 |
|
|
|
| 2518 |
|
|
always @(posedge watchdog_err)
|
| 2519 |
|
|
begin
|
| 2520 |
|
|
$display("%t: %m - Watchdog counter error",$time);
|
| 2521 |
|
|
if (|wbm_slave_sel)
|
| 2522 |
|
|
$display("%t: %m - slave %d selected - it didn't respond in time",
|
| 2523 |
|
|
$time, wbm_slave_sel);
|
| 2524 |
|
|
else
|
| 2525 |
|
|
$display("%t: %m - NO slave was selected by switch - either bad address or arbiter hadn't granted a access to a locked slave", $time);
|
| 2526 |
|
|
end
|
| 2527 |
|
|
|
| 2528 |
|
|
`else
|
| 2529 |
|
|
wire watchdog_err;
|
| 2530 |
|
|
assign watchdog_err = 0;
|
| 2531 |
|
|
`endif
|
| 2532 |
|
|
|
| 2533 |
|
|
|
| 2534 |
|
|
|
| 2535 |
|
|
assign wbm_ack_i = (wbm_slave_sel[0]) ? wbs0_ack_o :
|
| 2536 |
|
|
`ifdef WBS1
|
| 2537 |
|
|
(wbm_slave_sel[1]) ? wbs1_ack_o :
|
| 2538 |
|
|
`endif
|
| 2539 |
|
|
`ifdef WBS2
|
| 2540 |
|
|
(wbm_slave_sel[2]) ? wbs2_ack_o :
|
| 2541 |
|
|
`endif
|
| 2542 |
|
|
`ifdef WBS3
|
| 2543 |
|
|
(wbm_slave_sel[3]) ? wbs3_ack_o :
|
| 2544 |
|
|
`endif
|
| 2545 |
|
|
`ifdef WBS4
|
| 2546 |
|
|
(wbm_slave_sel[4]) ? wbs4_ack_o :
|
| 2547 |
|
|
`endif
|
| 2548 |
|
|
`ifdef WBS5
|
| 2549 |
|
|
(wbm_slave_sel[5]) ? wbs5_ack_o :
|
| 2550 |
|
|
`endif
|
| 2551 |
|
|
`ifdef WBS6
|
| 2552 |
|
|
(wbm_slave_sel[6]) ? wbs6_ack_o :
|
| 2553 |
|
|
`endif
|
| 2554 |
|
|
`ifdef WBS7
|
| 2555 |
|
|
(wbm_slave_sel[7]) ? wbs7_ack_o :
|
| 2556 |
|
|
`endif
|
| 2557 |
|
|
watchdog_err;
|
| 2558 |
|
|
|
| 2559 |
|
|
assign wbm_err_i = (wbm_slave_sel[0]) ? wbs0_err_o :
|
| 2560 |
|
|
`ifdef WBS1
|
| 2561 |
|
|
(wbm_slave_sel[1]) ? wbs1_err_o :
|
| 2562 |
|
|
`endif
|
| 2563 |
|
|
`ifdef WBS2
|
| 2564 |
|
|
(wbm_slave_sel[2]) ? wbs2_err_o :
|
| 2565 |
|
|
`endif
|
| 2566 |
|
|
`ifdef WBS3
|
| 2567 |
|
|
(wbm_slave_sel[3]) ? wbs3_err_o :
|
| 2568 |
|
|
`endif
|
| 2569 |
|
|
`ifdef WBS4
|
| 2570 |
|
|
(wbm_slave_sel[4]) ? wbs4_err_o :
|
| 2571 |
|
|
`endif
|
| 2572 |
|
|
`ifdef WBS5
|
| 2573 |
|
|
(wbm_slave_sel[5]) ? wbs5_err_o :
|
| 2574 |
|
|
`endif
|
| 2575 |
|
|
`ifdef WBS6
|
| 2576 |
|
|
(wbm_slave_sel[6]) ? wbs6_err_o :
|
| 2577 |
|
|
`endif
|
| 2578 |
|
|
`ifdef WBS7
|
| 2579 |
|
|
(wbm_slave_sel[7]) ? wbs7_err_o :
|
| 2580 |
|
|
`endif
|
| 2581 |
|
|
watchdog_err;
|
| 2582 |
|
|
|
| 2583 |
|
|
assign wbm_rty_i = (wbm_slave_sel[0]) ? wbs0_rty_o :
|
| 2584 |
|
|
`ifdef WBS1
|
| 2585 |
|
|
(wbm_slave_sel[1]) ? wbs1_rty_o :
|
| 2586 |
|
|
`endif
|
| 2587 |
|
|
`ifdef WBS2
|
| 2588 |
|
|
(wbm_slave_sel[2]) ? wbs2_rty_o :
|
| 2589 |
|
|
`endif
|
| 2590 |
|
|
`ifdef WBS3
|
| 2591 |
|
|
(wbm_slave_sel[3]) ? wbs3_rty_o :
|
| 2592 |
|
|
`endif
|
| 2593 |
|
|
`ifdef WBS4
|
| 2594 |
|
|
(wbm_slave_sel[4]) ? wbs4_rty_o :
|
| 2595 |
|
|
`endif
|
| 2596 |
|
|
`ifdef WBS5
|
| 2597 |
|
|
(wbm_slave_sel[5]) ? wbs5_rty_o :
|
| 2598 |
|
|
`endif
|
| 2599 |
|
|
`ifdef WBS6
|
| 2600 |
|
|
(wbm_slave_sel[6]) ? wbs6_rty_o :
|
| 2601 |
|
|
`endif
|
| 2602 |
|
|
`ifdef WBS7
|
| 2603 |
|
|
(wbm_slave_sel[7]) ? wbs7_rty_o :
|
| 2604 |
|
|
`endif
|
| 2605 |
|
|
0;
|
| 2606 |
|
|
|
| 2607 |
|
|
assign wbm_dat_i = (wbm_slave_sel[0]) ? wbs0_dat_o :
|
| 2608 |
|
|
`ifdef WBS1
|
| 2609 |
|
|
(wbm_slave_sel[1]) ? wbs1_dat_o :
|
| 2610 |
|
|
`endif
|
| 2611 |
|
|
`ifdef WBS2
|
| 2612 |
|
|
(wbm_slave_sel[2]) ? wbs2_dat_o :
|
| 2613 |
|
|
`endif
|
| 2614 |
|
|
`ifdef WBS3
|
| 2615 |
|
|
(wbm_slave_sel[3]) ? wbs3_dat_o :
|
| 2616 |
|
|
`endif
|
| 2617 |
|
|
`ifdef WBS4
|
| 2618 |
|
|
(wbm_slave_sel[4]) ? wbs4_dat_o :
|
| 2619 |
|
|
`endif
|
| 2620 |
|
|
`ifdef WBS5
|
| 2621 |
|
|
(wbm_slave_sel[5]) ? wbs5_dat_o :
|
| 2622 |
|
|
`endif
|
| 2623 |
|
|
`ifdef WBS6
|
| 2624 |
|
|
(wbm_slave_sel[6]) ? wbs6_dat_o :
|
| 2625 |
|
|
`endif
|
| 2626 |
|
|
`ifdef WBS7
|
| 2627 |
|
|
(wbm_slave_sel[7]) ? wbs7_dat_o :
|
| 2628 |
|
|
`endif
|
| 2629 |
|
|
0;
|
| 2630 |
|
|
|
| 2631 |
|
|
endmodule // wb_b3_switch_master_out_mux
|
| 2632 |
|
|
|
| 2633 |
|
|
|
