OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-board-benchsrc.inc] - Blame information for rev 542

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 542 julius
 
2
#
3
# Testbench source
4
#
5
BOARD_BENCH_VERILOG_SRC=$(shell ls $(BOARD_BENCH_VERILOG_DIR)/*.v | grep -v $(DESIGN_NAME)_testbench )
6
BOARD_BENCH_VERILOG_SRC_FILES=$(notdir $(BOARD_BENCH_VERILOG_SRC))
7
 
8
# Now only take the source from the common path that we don't already have in
9
# our board's
10
COMMON_BENCH_VERILOG_DIR_LS=$(shell ls $(COMMON_BENCH_VERILOG_DIR)/*.v)
11
COMMON_BENCH_VERILOG_SRC_FILES=$(notdir $(COMMON_BENCH_VERILOG_DIR_LS))
12
COMMON_BENCH_VERILOG_SRC_FILTERED=$(filter-out $(BOARD_BENCH_VERILOG_SRC_FILES) $(DESIGN_NAME)_testbench.v,$(COMMON_BENCH_VERILOG_SRC_FILES))
13
COMMON_BENCH_VERILOG_SRC=$(addprefix $(COMMON_BENCH_VERILOG_DIR)/, $(COMMON_BENCH_VERILOG_SRC_FILTERED))
14
 
15
print-board-bench-src:
16
        $(Q)echo "\tBoard bench verilog source"; \
17
        echo $(BOARD_BENCH_VERILOG_SRC)
18
 
19
print-common-bench-src:
20
        $(Q)echo "\Common bench verilog source"; \
21
        echo $(COMMON_BENCH_VERILOG_SRC)
22
 
23
# Testbench source subdirectory detection (exclude include, we always use
24
# board bench include directory!)
25
BOARD_BENCH_VERILOG_SUBDIRS=$(shell cd $(BOARD_BENCH_VERILOG_DIR) && ls -d */ | grep -v include)
26
COMMON_BENCH_VERILOG_SUBDIRS=$(shell cd $(COMMON_BENCH_VERILOG_DIR) && ls -d */ | grep -v include)
27
 
28
# Get rid of ones we have a copy of locally
29
COMMON_BENCH_VERILOG_SUBDIRS_EXCLUDE_BOARDS=$(filter-out $(BOARD_BENCH_VERILOG_SUBDIRS),$(COMMON_BENCH_VERILOG_SUBDIRS))
30
 
31
# Construct list of paths we will want to include
32
BENCH_VERILOG_SUBDIRS=$(addprefix $(COMMON_BENCH_VERILOG_DIR)/,$(COMMON_BENCH_VERILOG_SUBDIRS_EXCLUDE_BOARDS))
33
BENCH_VERILOG_SUBDIRS += $(addprefix $(BOARD_BENCH_VERILOG_DIR)/,$(BOARD_BENCH_VERILOG_SUBDIRS))
34
 
35
# Finally, add include path from local bench path
36
BENCH_VERILOG_SUBDIRS += $(BOARD_BENCH_VERILOG_DIR)/include
37
 
38
ifeq ($(VPI), 1)
39
# Manually add the VPI bench verilog path
40
COMMON_BENCH_VERILOG_SUBDIRS += $(VPI_SRC_VERILOG_DIR)
41
endif
42
 
43
print-board-bench-subdirs:
44
        $(Q)echo "\tBoard bench subdirectories"; \
45
        echo $(BOARD_BENCH_VERILOG_SUBDIRS)
46
 
47
print-common-bench-subdirs:
48
        $(Q)echo "\tCommon bench subdirectories"; \
49
        echo $(COMMON_BENCH_VERILOG_SUBDIRS)
50
 
51
print-bench-subdirs:
52
        $(Q)echo "\tBench subdirectories"; \
53
        echo $(BENCH_VERILOG_SUBDIRS)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.