OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-board-definesparse.inc] - Blame information for rev 566

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 542 julius
# Main defines file is from board include path
2
PROJECT_VERILOG_DEFINES ?=$(BOARD_RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
3
 
4
# Detect technology to use for the simulation
5
DESIGN_DEFINES ?=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
6
 
7
# Rule to look at what defines are being extracted from main file
8
print-defines:
9
        @echo echo; echo "\t### Design defines ###"; echo;
10
        @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
11
        @echo $(DESIGN_DEFINES)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.