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[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-board-modelsim.inc] - Blame information for rev 560

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1 542 julius
# Modelsim script generation, compile and run rules for board simulations
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#
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# Modelsim-specific settings
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#
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VOPT_ARGS+=$(QUIET) -suppress 2241
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# If VCD dump is desired, tell Modelsim not to optimise
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# away everything.
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ifeq ($(VCD), 1)
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#VOPT_ARGS=-voptargs="+acc=rnp"
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VOPT_ARGS+=+acc=rnpqv
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endif
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# VSIM commands
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# Suppressed warnings - 3009: Failed to open $readmemh() file
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# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
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# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
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VSIM_ARGS+=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
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# VPI debugging interface set up
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VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
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VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
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# Modelsim VPI compile variables
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MODELTECH_VPILIB=msim_jp_vpi.sl
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# Modelsim VPI settings
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ifeq ($(VPI), 1)
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VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
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VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
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endif
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# Rule to make the VPI library for modelsim
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$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB): $(VPI_SRCS)
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        $(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
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#
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# Script generation rules
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#
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# Backend script generation - make these rules sensitive to source and includes
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modelsim_backend.scr: $(BOARD_BACKEND_VERILOG_SRC)
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        $(Q)echo "+incdir+"$(TECHNOLOGY_BACKEND_VERILOG_DIR) > $@;
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        $(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
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        $(Q)for vsrc in $(BACKEND_TECHNOLOGY_VERILOG_SRC); do echo $$vsrc >> $@; done
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        $(Q)echo "-y " $(TECHNOLOGY_LIBRARY_VERILOG_DIR) >> $@;
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        $(Q)echo "+libext+.v" >> $@;
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        $(Q)echo >> $@;
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# DUT compile script
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modelsim_dut.scr: $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
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        $(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) > $@;
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        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
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        $(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) >> $@;
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        $(Q)echo "+libext+.v" >> $@;
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        $(Q)for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(BOARD_RTL_VERILOG_DIR)/$$module >> $@; fi; done
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        $(Q)for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(COMMON_RTL_VERILOG_DIR)/$$module >> $@; fi; done
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        $(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
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        $(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
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                then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
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                echo "+libext+.vm" >> $@; \
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        fi
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ifeq ($(FPGA_VENDOR), xilinx)
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        $(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@;
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        $(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@;
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endif
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        $(Q)echo >> $@
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modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
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        $(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@;
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        $(Q)echo "+incdir+"$(COMMON_BENCH_VERILOG_INCLUDE_DIR) >> $@;
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        $(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "+incdir+"$$path >> $@; done
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        $(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "-y "$$path >> $@; done
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        $(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) >> $@;
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        $(Q)echo "+libext+.v" >> $@;
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        $(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
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        $(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
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ifeq ($(FPGA_VENDOR), xilinx)
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        $(Q)echo "+incdir+"$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src" >> $@;
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endif
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        $(Q)echo >> $@
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#
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# Build rules
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#
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# Modelsim backend library compilation rules
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BACKEND_LIB=lib_backend
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$(BACKEND_LIB): modelsim_backend.scr
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        $(Q)if [ ! -e $@ ]; then vlib $@; fi
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        $(Q)echo; echo "\t### Compiling backend library ###"; echo
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        $(Q)vlog -nologo $(QUIET) -work $@ -f $<
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# Compile DUT into "work" library
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work: modelsim_dut.scr
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        $(Q)if [ ! -e $@ ]; then vlib $@; fi
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        $(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
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        $(Q)vlog $(QUIET) -f $< $(DUT_TOP_FILE)
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        $(Q)if [ "$(RTL_VHDL_SRC)" != "" ]; then \
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                echo; echo "\t### Compiling VHDL design library ###"; \
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                echo; \
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                vcom -93 $(QUIET) $(RTL_VHDL_SRC); \
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        fi
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#
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# Run rule, one for each vendor
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#
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.PHONY : $(MODELSIM)
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ifeq ($(FPGA_VENDOR), actel)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
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        $(Q)echo; echo "\t### Compiling testbench ###"; echo
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        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
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        -L $(BACKEND_LIB) -o tb
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        $(Q)echo; echo "\t### Launching simulation ###"; echo
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        $(Q)vsim $(VSIM_ARGS) tb
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endif
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ifeq ($(FPGA_VENDOR), xilinx)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
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        $(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
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ifeq ($(DO_XILINX_COMPXLIB), 1)
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        $(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
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endif
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        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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        $(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
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        $(Q)echo; echo "\t### Launching simulation ###"; echo
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        $(Q)vsim $(VSIM_ARGS) tb
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endif
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ifeq ($(FPGA_VENDOR), altera)
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$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work
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        $(Q)echo; echo "\t### Compiling testbench ###"; echo
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        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
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        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \
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        -L $(BACKEND_LIB) -o tb
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        $(Q)echo; echo "\t### Launching simulation ###"; echo
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        $(Q)vsim $(VSIM_ARGS) tb
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endif

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