URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-sim-definesgen.inc] - Blame information for rev 565
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
542 |
julius |
# A make rule that creates the test defines verilog file.
|
2 |
|
|
|
3 |
|
|
|
4 |
|
|
# Dynamically generated verilog file defining configuration for various things
|
5 |
|
|
# Rule actually generating this is found in definesgen.inc file.
|
6 |
|
|
TEST_DEFINES_VLG=test-defines.v
|
7 |
|
|
|
8 |
|
|
|
9 |
|
|
# Test defines.v file made .PHONY to force its generation every time
|
10 |
|
|
.PHONY: $(TEST_DEFINES_VLG)
|
11 |
|
|
$(TEST_DEFINES_VLG):
|
12 |
|
|
$(Q)echo "\`define "$(SIM_TYPE)"_SIM" > $@
|
13 |
|
|
$(Q)echo "\`define SIMULATOR_"`echo $(SIMULATOR) | tr "[:lower:]" "[:upper:]"` >> $@
|
14 |
|
|
$(Q)echo "\`define TEST_NAME_STRING \""$(TEST)"\"" >> $@
|
15 |
|
|
$(Q)if [ ! -z $$VCD ]; \
|
16 |
|
|
then echo "\`define VCD" >> $@; \
|
17 |
|
|
fi
|
18 |
|
|
$(Q)if [ ! -z $$VCD_DELAY ]; \
|
19 |
|
|
then echo "\`define VCD_DELAY "$$VCD_DELAY >> $@; \
|
20 |
|
|
fi
|
21 |
|
|
$(Q)if [ ! -z $$VCD_DEPTH ]; \
|
22 |
|
|
then echo "\`define VCD_DEPTH "$$VCD_DEPTH >> $@; \
|
23 |
|
|
fi
|
24 |
|
|
$(Q)if [ ! -z $$VCD_DELAY_INSNS ]; \
|
25 |
|
|
then echo "\`define VCD_DELAY_INSNS "$$VCD_DELAY_INSNS >> $@; \
|
26 |
|
|
fi
|
27 |
|
|
$(Q)if [ ! -z $$END_TIME ]; \
|
28 |
|
|
then echo "\`define END_TIME "$$END_TIME >> $@; \
|
29 |
|
|
fi
|
30 |
|
|
$(Q)if [ ! -z $$END_INSNS ]; \
|
31 |
|
|
then echo "\`define END_INSNS "$$END_INSNS >> $@; \
|
32 |
|
|
fi
|
33 |
|
|
$(Q)if [ ! -z $$PRELOAD_RAM ]; \
|
34 |
|
|
then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \
|
35 |
|
|
fi
|
36 |
|
|
$(Q)if [ -z $$DISABLE_PROCESSOR_LOGS ]; \
|
37 |
|
|
then echo "\`define PROCESSOR_MONITOR_ENABLE_LOGS" >> $@; \
|
38 |
|
|
fi
|
39 |
|
|
$(Q)if [ ! -z $$VPI ]; \
|
40 |
|
|
then echo "\`define VPI_DEBUG" >> $@; \
|
41 |
|
|
fi
|
42 |
|
|
$(Q)if [ ! -z $$SIM_QUIET ]; \
|
43 |
|
|
then echo "\`define SIM_QUIET" >> $@; \
|
44 |
|
|
fi
|
45 |
|
|
$(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
|
46 |
|
|
|
47 |
|
|
|
48 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.