OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-swrules.inc] - Blame information for rev 542

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 542 julius
 
2
#
3
# Software compilation rules used mostly in simulation.
4
#
5
 
6
# Name of the image the RAM model will attempt to load via Verilog $readmemh
7
# system function.
8
 
9
# Set PRELOAD_RAM=1 to preload the system memory
10
ifeq ($(PRELOAD_RAM), 1)
11
SIM_SW_IMAGE ?=sram.vmem
12
endif
13
 
14
ifeq ($(SIM_SW_IMAGE),)
15
SIM_SW_IMAGE ?=flash.in
16
endif
17
 
18
.PHONY : sw
19
sw: $(SIM_SW_IMAGE)
20
 
21
 
22
flash.in: $(SW_TEST_DIR)/$(TEST).flashin
23
        $(Q)if [ -L $@ ]; then unlink $@; fi
24
        $(Q)ln -s $< $@
25
 
26
sram.vmem: $(SW_TEST_DIR)/$(TEST).vmem
27
        $(Q)if [ -L $@ ]; then unlink $@; fi
28
        $(Q)ln -s $< $@
29
 
30
.PHONY: $(SW_TEST_DIR)/$(TEST).flashin
31
$(SW_TEST_DIR)/$(TEST).flashin:
32
        $(Q) echo; echo "\t### Compiling software ###"; echo;
33
        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).flashin
34
 
35
.PHONY: $(SW_TEST_DIR)/$(TEST).vmem
36
$(SW_TEST_DIR)/$(TEST).vmem:
37
        $(Q) echo; echo "\t### Compiling software ###"; echo;
38
        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem
39
 
40
# Create test software disassembly
41
 
42
sw-dis: $(SW_TEST_DIR)/$(TEST).dis
43
        $(Q)cp -v $< .
44
 
45
$(SW_TEST_DIR)/$(TEST).dis:
46
        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis
47
 
48
 
49
#
50
# Clean rules
51
#
52
 
53
clean-sim-test-sw:
54
        $(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.