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[/] [openrisc/] [trunk/] [orpsocv2/] [scripts/] [make/] [Makefile-swrules.inc] - Blame information for rev 560

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Line No. Rev Author Line
1 542 julius
 
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#
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# Software compilation rules used mostly in simulation.
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#
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# Name of the image the RAM model will attempt to load via Verilog $readmemh
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# system function.
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# Set PRELOAD_RAM=1 to preload the system memory
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ifeq ($(PRELOAD_RAM), 1)
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SIM_SW_IMAGE ?=sram.vmem
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endif
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ifeq ($(SIM_SW_IMAGE),)
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SIM_SW_IMAGE ?=flash.in
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endif
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.PHONY : sw
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sw: $(SIM_SW_IMAGE)
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flash.in: $(SW_TEST_DIR)/$(TEST).flashin
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        $(Q)if [ -L $@ ]; then unlink $@; fi
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        $(Q)ln -s $< $@
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sram.vmem: $(SW_TEST_DIR)/$(TEST).vmem
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        $(Q)if [ -L $@ ]; then unlink $@; fi
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        $(Q)ln -s $< $@
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.PHONY: $(SW_TEST_DIR)/$(TEST).flashin
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$(SW_TEST_DIR)/$(TEST).flashin:
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        $(Q) echo; echo "\t### Compiling software ###"; echo;
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        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).flashin
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.PHONY: $(SW_TEST_DIR)/$(TEST).vmem
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$(SW_TEST_DIR)/$(TEST).vmem:
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        $(Q) echo; echo "\t### Compiling software ###"; echo;
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        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem
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# Create test software disassembly
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sw-dis: $(SW_TEST_DIR)/$(TEST).dis
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        $(Q)cp -v $< .
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$(SW_TEST_DIR)/$(TEST).dis:
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        $(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis
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#
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# Clean rules
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#
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clean-sim-test-sw:
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        $(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi

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