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1 6 julius
######################################################################
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####                                                              ####
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####  ORPSoCv2 Testbenches Makefile                               ####
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####                                                              ####
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####  Description                                                 ####
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####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
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####  configuring and running different tests on the current      ####
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####  ORPSoC(v2) design.                                          ####
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####                                                              ####
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####  To do:                                                      ####
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####    * Test if each software test file gets made properly      ####
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####      before it's run in whatever model we're using           ####
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####    * Expand software test-suite (uClibc, ecos tests, LTP?)   ####
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####                                                              ####
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####  Author(s):                                                  ####
16 348 julius
####      - Julius Baxter, julius.baxter@orsoc.se                 ####
17 6 julius
####                                                              ####
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####                                                              ####
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######################################################################
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####                                                              ####
21 348 julius
#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG            ####
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####                                                              ####
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#### This source file may be used and distributed without         ####
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#### restriction provided that this copyright statement is not    ####
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#### removed from the file and that any derivative work contains  ####
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#### the original copyright notice and the associated disclaimer. ####
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####                                                              ####
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#### This source file is free software; you can redistribute it   ####
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#### and/or modify it under the terms of the GNU Lesser General   ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any   ####
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#### later version.                                               ####
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####                                                              ####
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#### This source is distributed in the hope that it will be       ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
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#### PURPOSE.  See the GNU Lesser General Public License for more ####
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#### details.                                                     ####
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####                                                              ####
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#### You should have received a copy of the GNU Lesser General    ####
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#### Public License along with this source; if not, download it   ####
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#### from http://www.opencores.org/lgpl.shtml                     ####
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####                                                              ####
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######################################################################
45
 
46
# Usage:
47
#
48
#       make rtl-tests
49
#
50
#       Run the software tests in the RTL model of the ORPSoC being
51 55 julius
#       simulated with an event-driven simulator like Icarus. It's also
52
#       possible to use Modelsim's vsim and Cadence's Verilog simulators.
53 6 julius
#
54
#       make vlt-tests
55
#
56
#       Run all the software tests in the RTL model which has been
57
#       converted into a cycle-accurate SystemC model with Verilator.
58
#
59
#       make sim-tests
60
#
61
#       Run all the software tests in the architectural simulator
62
#
63 40 julius
#
64
# Debugging modes:
65
#
66
#       make rtl-debug
67
#
68
#       Enable a GDB stub integrated into the simulation via VPI. This will
69
#       start a simulation, then the GDB server, and allow the user to connect
70
#       using the OpenRISC GDB port. It should provide the same functionality
71
#       as GDB to a physical target, although a little slower.
72
#       It is provided here as an example of how to compile and run an OpenRISC
73
#       model at RTL level with support for debugging from GDB.
74
#       UART output from printf() is enabled by default. The model loads with
75
#       the dhrystone test running as default, but can be changed by defining
76
#       VPI_TEST_SW at the command line. Logging of the processor's execution
77
#       is also disabled by default to speed up simulation.
78
#
79 6 julius
 
80
# Simulation results:
81
#
82
# The results and output of the event-driven simulations are in the
83
# results path, in parallel to the simulation run and bin paths.
84
 
85
# Specific tests:
86
#
87
# To run an individual test, specify it in the variable TESTS when
88
# calling make, eg:
89
#
90
#        make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
91
 
92
# UART printf:
93
#
94
# It is possible to enable printf to the console via the UART when
95
# running the event-driven simulators. To do this define UART_PRINTF=1
96
# when calling make. The SystemC cycle-acccurate model uses this by
97
# default.
98
# Also note when switching between runs with and without UART printf
99
# enabled, run a clean-sw so the library files are recompiled when
100
# the tests are run - this is not done automatically.
101
 
102
# VCDs:
103
#
104
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
105
# to inspect the internals of the system graphically) files can be
106
# generated by defining a variable VCD, eg.
107
#
108
#       make rtl-tests VCD=1
109
#
110
# and a dump file will be created in the simulation results directory,
111
# and named according to the test run which generated it. This is
112
# possible for both event-driven and cycle-accurate simulations.
113
# However the cycle-accurate
114
 
115
# NO_SIM_LOGGING:
116
#
117
# It is possible to speed up the event-driven simulation slightly by
118
# disabling log output of the processor's state to files by defining
119
# NO_SIM_LOGGING, eg:
120
#
121
#       make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
122
#
123
 
124
# Cleaning:
125
# A simple "make clean" cleans everything - software and all temporary
126
# simulation files and directories. To clean just the software run:
127
#
128
#       make clean-sw
129
#
130
# and to clean just the temporary simulation files (including VCDs,
131
# results logs - everything under, and including, sim/results/, run
132
#
133
#       make clean-sim
134
#
135
 
136
# Note:
137
#
138
# The way each of the test loops is written is probably a bit overly complex
139
# but this is to save maintaining, and calling, multiple files.
140
#
141
 
142
# Model configuration:
143
#
144
# Currently, the ORPSoCv2, by default, contains an internal SRAM (configurable
145
# size - check the defparam in rtl/verilog/orpsoc_top.v), standard OR1200 (check
146
# the config in rtl/verilog/or1200_defines.v) and UART.
147
# Switches can be passed to enable certain parts of the design if testing with
148
# these is desired.
149
#
150
# SDRAM and controller
151
#
152
# To enable the use of SDRAM, define USE_SDRAM when calling the sim -this
153
# only has an effect in the event-driven simulators as the external SDRAM model
154
# is not availble in SystemC format. eg:
155
#
156
#       make rtl-tests USE_SDRAM=1
157
#
158
# This not only enables SDRAM but also enables the booting from external SPI
159
# interfaced flash memory. This causes significant increase in the time taken
160
# for simulation as the program to test is first loaded out of SPI flash memory
161
# and into SDRAM before it is executed. Although this more closely mimics the
162
# behaviour of the hardware, for simulation purposes it is purely time-consuming
163
# however it may be useful to track down any problems with this boot-loading
164 43 julius
# process. Therefore, becuase it enables SDRAM memory, it also enables the flash
165 6 julius
# memory model and SPI controller inside ORPSoC.
166
#
167
# Ethernet
168
#
169
# Ethernet is disabled by default. This is due to the fact that it is not
170
# supported in the verilator/systemC model. Also, there is currently no software
171
# which tests it in any meaningful way.
172
#
173
 
174
#
175
# Event-driven simulation compilation
176
#
177
# The way the event-driven simulations are compiled is simply using the
178
# configuration script file in this directory, currently called icarus.scr -
179
# however it is first processesed to replace the variables, beginning with $'s,
180
# with the appropriate paths. Instead of naming each file to be compiled, the
181
# paths to be searched for each module are instead defined ( -y paths), and
182
# only the toplevel testbench and library source files are explicitly named.
183
# This simplifies the script, and also requires that the name of each verilog
184
# source file is the same as the module it contains (a good convention
185
# regardless.) In addition to the script/command file, defines are passed to
186
# the compiler via the command line in the EVENT_SIM_FLAGS variable.
187
# Additionally, a source file, test_define.v, is created with  some defines
188
# that cannot be passed to the compiled reliably (there are differences between
189
# the way, for instance, icarus and ncverilog parse strings +define+'d on the
190
# command line). This file is then included at the appropriate places.
191
# It is probably not ideal that the entire design be re-compiled for each test,
192
# but currently the design is small enough so that this doesn't cause a
193
# significant overhead, unlike the cycle-accurate model compile time.
194
#
195
 
196
#
197
# SystemC cycle-accurate model compilation
198
#
199
# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
200 44 julius
# behind this is verilator, which processes the RTL source and generates a c++
201
# description of the system. This c++ description is then compiled, with a
202 6 julius
# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
203 44 julius
# model, and other useful modules - in this case a reset generation, UART
204 6 julius
# decoder, and monitor module are included at the top level. These additional
205 44 julius
# modules and models are written in SystemC. Finally, everything is linked with
206
# the cycle-accurate ORPSoC model to create the simulation executable. This
207
# executable is the cycle-representation of the system.
208
#
209 49 julius
# Run the resulting executable with the -h switch for usage.
210 44 julius
#
211
# The compilation is all done with the GNU c++ compiler, g++.
212
#
213
# The compilation process is a little more complicated than the event-driven
214 6 julius
# simulator. It proceeds basically by generating the makefiles for compiling
215
# the design with verilator, running these makes which produces a library
216
# containing the cycle-accurate ORPSoC design, compiling the additional
217
# top-level, and testbench, systemC models into a library, and then linking it
218
# all together into the simulation executable.
219 44 julius
#
220 6 julius
# The major advantage of the cycle-accurate model is that it is quicker, in
221
# terms of simulated cycles/second, when compared with event-driven simulators.
222
# It is, of course, less accurate in that it cannot model propegation delays.
223
# However this is usually not an issue for simulating a design which is known
224
# to synthesize and run OK. It is very useful for running complex software,
225
# such as the linux kernel and real-time OS applications, which generally
226 44 julius
# result in long simulation times.
227
#
228 6 julius
# Currently the cycle-accurate model being used doesn't contain much more than
229
# the processor and a UART, however it's exepected in future this will be
230
# expanded on and more complex software test suites will be implemented to put
231
# the system through its paces.
232
#
233 44 julius
#
234 49 julius
#
235 6 julius
 
236 44 julius
# Name of the directory we're currently in
237 6 julius
CUR_DIR=$(shell pwd)
238
 
239
# The root path of the whole project
240 67 julius
PROJECT_ROOT ?=$(CUR_DIR)/../..
241 6 julius
 
242
# Tests is only defined if it wasn't already defined when make was called
243
# This is the default list of every test that is currently possible
244 351 julius
 
245
TESTS ?= or1200-simple or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200asm-basic or1200asm-except or1200asm-linkregtest or1200asm-tick or1200asm-ticksyscall uart-simple
246 348 julius
#basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
247 6 julius
 
248
# Paths to other important parts of this test suite
249 67 julius
SIM_DIR ?=$(PROJECT_ROOT)/sim
250 6 julius
SIM_RUN_DIR=$(SIM_DIR)/run
251
SIM_BIN_DIR=$(SIM_DIR)/bin
252
SIM_RESULTS_DIR=$(SIM_DIR)/results
253
SIM_VLT_DIR=$(SIM_DIR)/vlt
254
BENCH_DIR=$(PROJECT_ROOT)/bench
255 67 julius
BACKEND_DIR ?=$(PROJECT_ROOT)/backend
256 6 julius
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
257 67 julius
BENCH_TOP_VERILOG_DIR ?= $(BENCH_DIR)/verilog
258 6 julius
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
259
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
260
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
261
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
262
SW_DIR=$(PROJECT_ROOT)/sw
263
 
264
ICARUS=iverilog
265
ICARUS_VVP=vvp
266 58 julius
VSIM_COMP=vlog
267
VSIM=vsim
268
NCVERILOG=ncverilog
269 77 rherveille
SILOS=silos
270 6 julius
ICARUS_COMMAND_FILE=icarus.scr
271
VLT_COMMAND_FILE=verilator.scr
272 348 julius
SIM_SUCCESS_MESSAGE=8000000d
273 55 julius
MGC_COMMAND_FILE=modelsim.scr
274 6 julius
 
275
ARCH_SIM_EXE=or32-elf-sim
276
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
277
 
278 57 julius
# Set V=1 when calling make to enable verbose output
279
# mainly for debugging purposes.
280
ifeq ($(V), 1)
281
Q=
282
else
283
Q=@
284
endif
285
 
286 6 julius
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
287
# command line becuase it's used by many different modules and it's easier
288
# to do it this way than make them all include a file.
289
ifdef USE_SDRAM
290 68 julius
EVENT_SIM_FLAGS +=USE_SDRAM=$(USE_SDRAM)
291 6 julius
endif
292
 
293 58 julius
# Enable ethernet if defined on the command line
294
ifdef USE_ETHERNET
295 68 julius
EVENT_SIM_FLAGS +=USE_ETHERNET=$(USE_ETHERNET) USE_ETHERNET_IO=$(USE_ETHERNET)
296 58 julius
# Extra tests we do if ethernet is enabled
297
TESTS += eth-basic eth-int
298
endif
299
 
300 68 julius
DASH_D_EVENT_SIM_FLAGS=$(shell for flag in $(EVENT_SIM_FLAGS); do echo "-D "$$flag; done)
301
PLUS_DEFINE_EVENT_SIM_FLAGS=$(shell for flag in $(EVENT_SIM_FLAGS); do echo "+define+"$$flag; done)
302
 
303 58 julius
#Default simulator is Icarus Verilog
304
# Set SIMULATOR=vsim to use Modelsim
305
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog
306
SIMULATOR ?= $(ICARUS)
307
 
308
# Set the command file to use, simulator dependent
309
ifeq ($(SIMULATOR), $(ICARUS))
310 55 julius
# Icarus Verilog Simulator
311
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
312
endif
313 51 julius
 
314 58 julius
ifeq ($(SIMULATOR), $(VSIM))
315
# Modelsim has own command file (it's a little more stupid than Icarus & NC)
316
SIM_COMMANDFILE=$(MGC_COMMAND_FILE)
317
endif
318
 
319
ifeq ($(SIMULATOR), $(NCVERILOG))
320
# NCVerilog uses same command file as Icarus
321
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
322
endif
323
 
324 77 rherveille
ifeq ($(SIMULATOR), $(SILOS))
325
# SILOS uses same command file as Icarus (this should be default)
326
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
327
endif
328
 
329
 
330 55 julius
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
331 51 julius
 
332 55 julius
# When Modelsim is selected as simulator, we compile
333
# the ORPSoC system into one library called orpsoc and
334
# then simply re-compile the testbench and or1200_monitor
335
# whenever we run the simulation, so just that part is
336
# recompiled for every test, instead of the whole thing.
337
MGC_ORPSOC_LIB=orpsoc
338
MGC_ORPSOC_LIB_DIR=$(SIM_RUN_DIR)/$(MGC_ORPSOC_LIB)
339
 
340
# If VCD dump is desired, tell Modelsim not to optimise
341
# away everything.
342
ifeq ($(VCD), 1)
343
VOPT_ARGS=-voptargs="+acc=rnp"
344
endif
345
 
346 67 julius
# RTL testbench toplevel name
347
RTL_TESTBENCH_TOP ?= orpsoc_testbench
348
 
349 55 julius
# Simulation compile and run commands, depending on your
350 58 julius
# simulator.
351
 
352
# Icarus Verilog
353
ifeq ($(SIMULATOR), $(ICARUS))
354
# Icarus Verilog Simulator compile and run commands
355 348 julius
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/rtlsim.elf; $(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -o rtlsim.elf $(DASH_D_EVENT_SIM_FLAGS)
356 58 julius
# Icarus Verilog run command
357 348 julius
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log rtlsim.elf
358 58 julius
endif
359
 
360
# Modelsim
361
ifeq ($(SIMULATOR), $(VSIM))
362 55 julius
# Line to compile the orpsoc design into a modelsim library.
363 68 julius
SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work $(MGC_ORPSOC_LIB) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(PLUS_DEFINE_EVENT_SIM_FLAGS); fi
364 55 julius
# Final modelsim compile, done each time, pulling in or1200
365
# monitor and the new test_defines.v file:
366 68 julius
VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) -y $(BENCH_VERILOG_DIR) +libext+.v +incdir+$(BENCH_TOP_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(PLUS_DEFINE_EVENT_SIM_FLAGS) $(BENCH_TOP_VERILOG_DIR)/$(RTL_TESTBENCH_TOP).v
367 55 julius
# Simulation run command:
368 67 julius
SIM_COMMANDRUN=$(VSIM_COMPILE_TB); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" $(RTL_TESTBENCH_TOP)
369 55 julius
endif
370
 
371 58 julius
# NCVerilog
372
ifeq ($(SIMULATOR), $(NCVERILOG))
373
SIM_COMMANDCOMPILE=echo
374
SIM_COMMANDRUN=$(NCVERILOG) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -Q -l $(SIM_RESULTS_DIR)/$$TEST-$(NCVERILOG)-out.log $(EVENT_SIM_FLAGS)
375 6 julius
endif
376
 
377 77 rherveille
# Silos
378
ifeq ($(SIMULATOR), $(SILOS))
379
SIM_COMMANDCOMPILE=echo
380 78 rherveille
SIM_COMMANDRUN=$(SILOS) -b -w +width_mistmatches -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -l $(SIM_RESULTS_DIR)/$$TEST-$(SILOS)-out.log $(EVENT_SIM_FLAGS)
381 77 rherveille
endif
382
 
383
 
384 58 julius
# Names of memory files used in simulation
385 6 julius
SIM_FLASH_MEM_FILE="flash.in"
386
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
387
SIM_SRAM_MEM_FILE="sram.vmem"
388
 
389
TESTS_PASSED=0
390
TESTS_PERFORMED=0;
391
 
392
################################################################################
393 58 julius
# Event-driven simulator build rules
394 6 julius
################################################################################
395
 
396 51 julius
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
397
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
398 6 julius
 
399 57 julius
.PHONY: prepare-rtl
400
prepare-rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
401 6 julius
 
402 55 julius
$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)
403 57 julius
        $(Q)sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \
404 55 julius
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
405
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
406
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
407
                -e \\!^//.*\$$!d -e \\!^\$$!d ; \
408
        echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
409
        if [ ! -z $$VCD ]; \
410
                then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
411 58 julius
                if [ $(SIMULATOR) = $(NCVERILOG) ]; \
412
                        then echo "+access+r" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
413
                fi; \
414 55 julius
        fi; \
415
        if [ ! -z $$UART_PRINTF ]; \
416
                then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
417 58 julius
        fi; \
418
        if [ $(SIMULATOR) = $(NCVERILOG) ]; \
419
                then echo "+nocopyright" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
420
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
421 55 julius
        fi
422 51 julius
 
423 6 julius
ifdef UART_PRINTF
424 44 julius
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
425 6 julius
endif
426
 
427 57 julius
.PHONY: prepare-sw
428
prepare-sw:
429
        $(Q)$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
430
        $(Q)$(MAKE) -C $(SW_DIR)/utils all
431 6 julius
 
432
# A rule with UART_PRINTF hard defined ... used by verilator make sw
433 57 julius
prepare-sw-uart-printf:
434
        $(Q)$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
435
        $(Q)$(MAKE) -C $(SW_DIR)/utils all
436 6 julius
 
437 57 julius
prepare-dirs:
438
        $(Q)if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
439 6 julius
 
440 55 julius
#
441
# Rough guide to how event driven simulation test loop works:
442
#
443
# 1. Compile software support programs.
444
# 2. Generate RTL compilation script file
445
# 3. For each test listed in $(TESTS), loop and
446
#       a) Compile software
447
#       b) Create appropriate image to be loaded into sim
448
#       c) Create a verilog file to be included by top level
449
#       d) Compile the RTL design
450
#       e) Run the RTL design in the chosen simulator
451
#       f) Check the output (files in ../results)
452
#
453
# Default setup is:
454
#       * Event-driven simulation with Icarus Verilog
455
#       * Internal SRAM memory, preloaded with application
456
#       * Ethernet disabled
457
#       * VCD generation disabled
458
#       * printf() via UART disabled
459
#       * Logging enabled
460
#
461
# Options:
462
#       SIMULATOR=vsim
463
#               Use Mentor Graphics Modelsim simulator
464 58 julius
#       SIMULATOR=ncverilog
465
#               Use Cadence's NC-Verilog
466 55 julius
#       USE_SDRAM=1
467
#               Enable use of SDRAM - changes boot sequence and takes
468
#               a lot longer due to application being loaded out of
469
#               external FLASH memory and into SDRAM before execution
470
#               from the SDRAM.
471
#       VCD=1
472
#               Enable VCD generation. These files are output to
473
#               ../results
474
#       USE_ETHERNET=1
475
#               Turns on ethernet core inclusion. There are currently
476
#               some tests, but not included by default. Check the sw
477
#               directory
478
#       UART_PRINTF=1
479
#               Make the software use the UART core to print out
480
#               printf() calls.
481
#       NO_SIM_LOGGING=1
482
#               Turn off generation of logging files in the ../results
483
#               directory.
484
#
485 57 julius
rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare-sw prepare-rtl prepare-dirs
486 6 julius
        @echo
487
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
488
        @echo
489 57 julius
        $(Q)for TEST in $(TESTS); do \
490 6 julius
                echo "################################################################################"; \
491
                echo; \
492
                echo "\t#### Current test: $$TEST ####"; echo; \
493
                echo "\t#### Compiling software ####"; echo; \
494
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
495 348 julius
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST.vmem $(TEST_SW_MAKE_OPTS); \
496 6 julius
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
497
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
498
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
499
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
500 55 julius
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
501
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
502 6 julius
                if [ ! -z $$VCD ]; \
503 55 julius
                        then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
504 6 julius
                fi; \
505
                if [ ! -z $$UART_PRINTF ]; \
506 55 julius
                        then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
507 6 julius
                fi; \
508 44 julius
                if echo $$TEST | grep -q -i ^eth; then \
509
                        echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
510
                        echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
511
                fi; \
512 43 julius
                if [ -z $$NO_SIM_LOGGING ]; then \
513 6 julius
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
514
                fi; \
515
                echo ; \
516
                echo "\t#### Compiling RTL ####"; \
517 55 julius
                $(SIM_COMMANDCOMPILE); \
518 6 julius
                echo; \
519
                echo "\t#### Beginning simulation ####"; \
520 55 julius
                time -p $(SIM_COMMANDRUN) ; \
521 78 rherveille
                if [ "$$SIMULATOR" != "$$SILOS" ]; then if [ $$? -gt 0 ]; then exit $$?; fi; fi; \
522 348 julius
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep $(SIM_SUCCESS_MESSAGE) -c`; \
523 6 julius
                echo; echo "\t####"; \
524
                if [ $$TEST_RESULT -gt 0 ]; then \
525
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
526
                else    echo "\t#### Test $$TEST FAILED ####";\
527
                fi; \
528
                echo "\t####"; echo; \
529
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
530
        done; \
531
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
532
 
533
################################################################################
534 40 julius
# RTL simulation in Icarus with GDB stub via VPI for debugging
535
################################################################################
536
# This compiles a version of the system which starts up the dhrystone nocache
537
# test, and launches the simulator with a VPI module that provides a GDB stub
538
# allowing the OpenRISC compatible GDB to connect and debug the system.
539
# The launched test can be changed by defining VPI_TEST_SW on the make line
540
VPI_DIR=$(BENCH_VERILOG_DIR)/vpi
541
VPI_C_DIR=$(VPI_DIR)/c
542
VPI_VERILOG_DIR=$(VPI_DIR)/verilog
543
VPI_LIB_NAME=jp_vpi
544
ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)
545
VPI_TEST_SW ?= dhry-nocache-O2
546
 
547 57 julius
prepare-vpi:
548 40 julius
## Build the VPI library
549
        $(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)
550
 
551 49 julius
clean-vpi:
552 40 julius
        $(MAKE) -C $(VPI_C_DIR) clean
553
 
554 57 julius
rtl-debug: prepare-sw-uart-printf prepare-rtl prepare-vpi prepare-dirs
555 40 julius
## Prepare the software for the test
556
        @echo "\t#### Compiling software ####"; echo; \
557
        CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \
558
        $(MAKE) -C $$CURRENT_TEST_SW_DIR $(VPI_TEST_SW) $(TEST_SW_MAKE_OPTS); \
559
        rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
560
        rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
561
        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
562
        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)
563
## Generate the icarus script we'll compile with
564 57 julius
        $(Q)sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
565 40 julius
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
566
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
567
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
568
                -e \\!^//.*\$$!d -e \\!^\$$!d
569
## Add a couple of extra defines to the icarus compile script
570 57 julius
        $(Q)echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
571 40 julius
## The define that enables the VPI debug module
572 57 julius
        $(Q)echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
573
        $(Q)if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi
574 40 julius
## Unless NO_UART_PRINTF=1 we use printf via the UART
575 57 julius
        $(Q)if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi
576
        $(Q)echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
577
        $(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
578
        $(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
579 40 julius
        @echo
580
        @echo "\t#### Compiling RTL ####"
581 348 julius
        $(Q)rm -f $(SIM_RUN_DIR)/rtlsim.elf
582
        $(Q)$(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -o rtlsim.elf $(EVENT_SIM_FLAGS)
583 40 julius
        @echo
584
        @echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
585 348 julius
        $(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log rtlsim.elf
586 40 julius
 
587
################################################################################
588 6 julius
# Verilator model build rules
589
################################################################################
590
 
591
 
592
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
593
 
594
 
595
# List of System C models - use this list to link the sources into the Verilator
596
# build directory
597 51 julius
SYSC_MODELS=OrpsocAccess MemoryLoad
598 6 julius
 
599 49 julius
ifdef VLT_DEBUG
600
VLT_DEBUG_COMPILE_FLAGS = -g
601
# Enabling the following generates a TON of debugging
602
# when running verilator. Not so helpful.
603
#VLT_DEBUG_OPTIONS = --debug --dump-tree
604
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
605 6 julius
endif
606
 
607 49 julius
# If set on the command line we build the cycle accurate model which will generate verilator-specific profiling information. This is useful for checking the efficiency of the model - not really useful for checking code or the function of the model.
608
ifdef VLT_ORPSOC_PROFILING
609 63 julius
VLT_CPPFLAGS +=-pg
610 49 julius
VLT_DEBUG_OPTIONS +=-profile-cfuncs
611
else
612 63 julius
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
613 53 julius
#VLT_CPPFLAGS=-Wall
614 49 julius
endif
615
 
616 63 julius
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model executable in GDB to check suspect behavior. This also removes optimisation.
617
ifdef VLT_IN_GDB
618
VLT_CPPFLAGS +=-g -O0
619
else
620
# The default optimisation flag applied to all of the cycle accurate model files
621
VLT_CPPFLAGS +=-O3
622
endif
623
 
624 49 julius
ifdef VLT_DO_PROFILING
625 63 julius
VLT_CPPFLAGS +=-ftest-coverage -fprofile-arcs -fprofile-generate
626 49 julius
endif
627
 
628
# VCD Enabled by default when building, enable it at runtime
629
#ifdef VCD
630
VLT_FLAGS +=-trace
631
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
632
#endif
633
 
634 6 julius
# Only need the trace target if we are tracing
635 49 julius
#ifneq (,$(findstring -trace, $(VLT_FLAGS)))
636 70 julius
VLT_TRACEOBJ = verilated_vcd_c
637 49 julius
#endif
638 6 julius
 
639
# This is the list of extra models we'll issue make commands for
640
# Included is the SystemPerl trace model
641
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
642
 
643 63 julius
prepare-vlt: prepare-rtl vlt-model-links $(SIM_VLT_DIR)/Vorpsoc_top
644 54 julius
        @echo;echo "\tCycle-accurate model compiled successfully"
645
        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo
646
        $(SIM_VLT_DIR)/Vorpsoc_top -h
647
        @echo;echo
648 6 julius
 
649
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
650
# Final linking of the simulation executable. Order of libraries here is important!
651
        @echo; echo "\tGenerating simulation executable"; echo
652 49 julius
        cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
653 6 julius
 
654 51 julius
# Now compile the top level systemC "testbench" module from the systemC source path
655
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
656 6 julius
        @echo; echo "\tCompiling top level SystemC testbench"; echo
657 49 julius
        cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
658 6 julius
 
659 57 julius
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt-modules-compile $(SIM_VLT_DIR)/verilated.o
660 6 julius
# Now archive all of the libraries from verilator witht he other modules we might have
661
        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
662 57 julius
        $(Q)cd $(SIM_VLT_DIR) && \
663 6 julius
        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
664
        ar rcs libVorpsoc_top.a verilated.o; \
665
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
666
                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
667
        done
668
 
669
$(SIM_VLT_DIR)/verilated.o:
670
        @echo; echo "\tCompiling verilated.o"; echo
671 57 julius
        $(Q)cd $(SIM_VLT_DIR) && \
672 49 julius
        export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
673
        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
674
        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
675 6 julius
        $(MAKE) -f Vorpsoc_top.mk verilated.o
676
 
677 57 julius
.PHONY: vlt-modules-compile
678
vlt-modules-compile:
679 6 julius
# Compile the module files
680
        @echo; echo "\tCompiling SystemC models"
681 57 julius
        $(Q)cd $(SIM_VLT_DIR) && \
682 6 julius
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
683
                echo;echo "\t$$SYSCMODEL"; echo; \
684 49 julius
                export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
685 51 julius
                export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
686 49 julius
                export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
687
                 $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
688
        done
689 6 julius
 
690
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
691
        @echo; echo "\tCompiling main design"; echo
692 57 julius
        $(Q)cd $(SIM_VLT_DIR) && \
693 49 julius
        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
694
        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
695 6 julius
        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
696
 
697
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
698
# Now call verilator to generate the .mk files
699
        @echo; echo "\tGenerating makefiles with Verilator"; echo
700
        cd $(SIM_VLT_DIR) && \
701 49 julius
        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top $(VLT_DEBUG_OPTIONS) -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
702 6 julius
 
703
# SystemC modules library
704
$(SIM_VLT_DIR)/libmodules.a:
705
        @echo; echo "\tCompiling SystemC modules"; echo
706 57 julius
        $(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
707 49 julius
        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
708 6 julius
 
709
 
710 51 julius
ALL_VLOG=$(shell find $(RTL_VERILOG_DIR) -name "*.v")
711
 
712 6 julius
# Verilator command script
713 51 julius
# Generate the compile script to give Verilator - make it sensitive to the RTL
714
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated: $(ALL_VLOG)
715 6 julius
        @echo; echo "\tGenerating verilator compile script"; echo
716 57 julius
        $(Q)sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
717 6 julius
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
718
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
719
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
720
                -e \\!^//.*\$$!d -e \\!^\$$!d;
721
 
722 63 julius
.PHONY: vlt-model-links
723
vlt-model-links:
724 6 julius
# Link all the required system C model files into the verilator work dir
725
        @echo; echo "\tLinking SystemC model source to verilator build path"; echo
726
        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
727 57 julius
        $(Q)cd $(SIM_VLT_DIR) && \
728 6 julius
        for SYSCMODEL in $(SYSC_MODELS); do \
729
                if [ ! -e $$SYSCMODEL.cpp ]; then \
730
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
731
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
732
                fi; \
733
        done
734
 
735
 
736
################################################################################
737
# Verilator test loop
738
################################################################################
739
 
740
# Verilator defaults to internal memories
741 66 julius
vlt-tests: prepare-sw prepare-rtl prepare-dirs prepare-vlt
742 6 julius
        @echo
743
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
744
        @echo
745 57 julius
        $(Q)for TEST in $(TESTS); do \
746 6 julius
                echo "################################################################################"; \
747
                echo; \
748
                echo "\t#### Current test: $$TEST ####"; echo; \
749
                echo "\t#### Compiling software ####"; echo; \
750
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
751 348 julius
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST.vmem $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
752 6 julius
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
753
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
754
                echo "\t#### Beginning simulation ####"; \
755
                time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
756
                if [ $$? -gt 0 ]; then exit $$?; fi; \
757
                TEST_RESULT=1; \
758
                echo; echo "\t####"; \
759
                if [ $$TEST_RESULT -gt 0 ]; then \
760
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
761
                else    echo "\t#### Test $$TEST FAILED ####";\
762
                fi; \
763
                echo "\t####"; echo; \
764
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
765
        done; \
766
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
767
 
768 49 julius
###############################################################################
769
# Verilator profiled module make
770
###############################################################################
771 57 julius
# To run this, first run a "make prepare-vlt VLT_DO_PROFILING=1" then do a
772
# "make clean" and then a "make prepare-vlt_profiled"
773 49 julius
# This new make target copies athe results of the profiling back to the right
774
# paths before we create everything again
775
###############################################################################
776 63 julius
.PHONY: prepare-vlt-profiled
777
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda clean vlt-restore-profileoutput prepare-rtl vlt-model-links $(SIM_VLT_DIR)/Vorpsoc_top
778 6 julius
 
779 63 julius
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/Vorpsoc_top-for-profiling prepare-sw-uart-printf
780
        $(MAKE) -C $(SW_DIR)/dhry dhry-nocache-O2 NUM_RUNS=200
781
        $(SIM_VLT_DIR)/Vorpsoc_top -f $(SW_DIR)/dhry/dhry-nocache-O2.or32 -v -l sim.log --crash-monitor
782
 
783
.PHONY: $(SIM_VLT_DIR)/Vorpsoc_top-for-profiling
784
$(SIM_VLT_DIR)/Vorpsoc_top-for-profiling:
785
        $(MAKE) prepare-vlt VLT_DO_PROFILING=1
786
 
787
.PHONY: vlt-restore-profileoutput
788 57 julius
vlt-restore-profileoutput:
789 49 julius
        @echo;echo "\tRestoring profiling outputs"; echo
790 57 julius
        $(Q)mkdir -p ../vlt
791
        $(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
792
        $(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
793 6 julius
 
794
################################################################################
795
# Architectural simulator test loop
796
################################################################################
797
 
798
# Verilator defaults to internal memories
799 66 julius
sim-tests: prepare-sw
800 6 julius
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
801
        @echo
802
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
803
        @echo
804 57 julius
        $(Q)for TEST in $(TESTS); do \
805 6 julius
                echo "################################################################################"; \
806
                echo; \
807
                echo "\t#### Current test: $$TEST ####"; echo; \
808
                echo "\t#### Compiling software ####"; echo; \
809
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
810 348 julius
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST.vmem $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
811 6 julius
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
812
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
813
                echo;echo "\t#### Launching architectural simulator ####"; \
814
                time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
815
                if [ $$? -gt 0 ]; then exit $$?; fi; \
816
                if [ `tail -n 10 $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log | grep -c $(SIM_SUCCESS_MESSAGE)` -gt 0 ]; then \
817
                        TEST_RESULT=1; \
818
                fi; \
819
                echo; echo "\t####"; \
820
                if [ $$TEST_RESULT -gt 0 ]; then \
821
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
822
                else    echo "\t#### Test $$TEST FAILED ####";\
823
                fi; \
824
                echo "\t####"; echo; \
825
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
826
                unlink $(SIM_RUN_DIR)/$$TEST.or32; \
827
        done; \
828
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
829
 
830
 
831
 
832
################################################################################
833
# Cleaning rules
834
################################################################################
835
 
836 69 julius
dist-clean: clean
837
        $(MAKE) -C $(SW_DIR)/utils clean
838
 
839 49 julius
clean: clean-sw clean-sim clean-sysc clean-rtl clean-vpi
840 6 julius
 
841
clean-sw:
842 69 julius
        @for SWDIR in `ls $(SW_DIR) | grep -v utils`; do \
843 44 julius
                echo $$SWDIR; \
844
                $(MAKE) -C $(SW_DIR)/$$SWDIR clean; \
845 6 julius
        done
846
 
847
clean-sim:
848 49 julius
#backup any profiling output files
849 51 julius
        @if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo;echo "\tBacking up verilator profiling output to /tmp"; echo; \
850 49 julius
        cp $(SIM_VLT_DIR)/*.gc* /tmp; \
851
        cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi
852 55 julius
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR) $(MGC_ORPSOC_LIB_DIR) $(SIM_RUN_DIR)/work $(SIM_RUN_DIR)/transcript
853 36 julius
 
854
clean-sysc:
855
# Clean away dependency files generated by verilator
856 42 julius
        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
857 36 julius
 
858
clean-rtl:
859
# Clean away temporary verilog source files
860 44 julius
        rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
861
 

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