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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Blame information for rev 393

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1 6 julius
######################################################################
2
####                                                              ####
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####  ORPSoCv2 Testbenches Makefile                               ####
4
####                                                              ####
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####  Description                                                 ####
6
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
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####  configuring and running different tests on the current      ####
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####  ORPSoC(v2) design.                                          ####
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####                                                              ####
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####  To do:                                                      ####
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####                                                              ####
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####  Author(s):                                                  ####
13 360 julius
####      - Julius Baxter, julius@opencores.org                   ####
14 6 julius
####                                                              ####
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####                                                              ####
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######################################################################
17
####                                                              ####
18 348 julius
#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG            ####
19 6 julius
####                                                              ####
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#### This source file may be used and distributed without         ####
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#### restriction provided that this copyright statement is not    ####
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#### removed from the file and that any derivative work contains  ####
23
#### the original copyright notice and the associated disclaimer. ####
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####                                                              ####
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#### This source file is free software; you can redistribute it   ####
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#### and/or modify it under the terms of the GNU Lesser General   ####
27
#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any   ####
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#### later version.                                               ####
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####                                                              ####
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#### This source is distributed in the hope that it will be       ####
32
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
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#### PURPOSE.  See the GNU Lesser General Public License for more ####
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#### details.                                                     ####
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####                                                              ####
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#### You should have received a copy of the GNU Lesser General    ####
38
#### Public License along with this source; if not, download it   ####
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#### from http://www.opencores.org/lgpl.shtml                     ####
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####                                                              ####
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######################################################################
42
 
43 360 julius
# Name of the directory we're currently in
44
CUR_DIR=$(shell pwd)
45 6 julius
 
46 360 julius
# The root path of the whole project
47
PROJECT_ROOT ?=$(CUR_DIR)/../..
48 6 julius
 
49 362 julius
DESIGN_NAME=orpsoc
50
RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
51
# Top level files for DUT and testbench
52
DUT_TOP=$(RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
53
BENCH_TOP=$(BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
54
 
55 360 julius
# Need this for individual test variables to not break
56
TEST ?= or1200-simple
57 6 julius
 
58 393 julius
TESTS ?= or1200-simple or1200-basic or1200-cbasic or1200-dctest or1200-float or1200-mmu  or1200-except or1200-mac or1200-linkregtest or1200-tick or1200-ticksyscall uart-simple
59 6 julius
 
60 360 julius
# Gets turned into verilog `define
61
SIM_TYPE=RTL
62 6 julius
 
63 360 julius
# Paths to other important parts of this test suite
64
RTL_DIR = $(PROJECT_ROOT)/rtl
65
RTL_VERILOG_DIR = $(RTL_DIR)/verilog
66
RTL_VERILOG_INCLUDE_DIR = $(RTL_VERILOG_DIR)/include
67
#RTL_VHDL_DIR = $(RTL_DIR)/vhdl
68 6 julius
 
69 360 julius
PROJECT_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
70
# Detect technology to use for the simulation
71
DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
72 6 julius
 
73 360 julius
# Rule to look at what defines are being extracted from main file
74
print-defines:
75
        @echo echo; echo "\t### Design defines ###"; echo
76
        @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
77
        @echo $(DESIGN_DEFINES)
78 6 julius
 
79 360 julius
# Simulation directories
80
SIM_DIR ?=$(PROJECT_ROOT)/sim
81 362 julius
SIM_VLT_DIR ?=$(SIM_DIR)/vlt
82 360 julius
RTL_SIM_DIR=$(SIM_DIR)
83
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
84
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
85
RTL_SIM_SRC_DIR=$(RTL_SIM_DIR)/src
86
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
87 6 julius
 
88 360 julius
# Testbench paths
89 6 julius
BENCH_DIR=$(PROJECT_ROOT)/bench
90
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
91 360 julius
#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl
92 362 julius
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
93
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
94
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
95 360 julius
 
96 362 julius
 
97 360 julius
# System software dir
98 6 julius
SW_DIR=$(PROJECT_ROOT)/sw
99 360 julius
# BootROM code, which generates a verilog array select values
100
BOOTROM_FILE=bootrom.v
101
BOOTROM_SW_DIR=$(SW_DIR)/bootrom
102
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
103
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
104
$(BOOTROM_VERILOG): $(BOOTROM_SRC)
105
        $(Q)echo; echo "\t### Generating bootup ROM ###"; echo
106
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
107 6 julius
 
108 360 julius
# Suffix of file to check after each test for the string
109
TEST_OUT_FILE_SUFFIX=-general.log
110
TEST_OK_STRING=8000000d
111 6 julius
 
112 360 julius
# Dynamically generated verilog file defining configuration for various things
113
TEST_DEFINES_VLG=test-defines.v
114 57 julius
# Set V=1 when calling make to enable verbose output
115
# mainly for debugging purposes.
116
ifeq ($(V), 1)
117
Q=
118 360 julius
QUIET=
119 57 julius
else
120 360 julius
Q ?=@
121
QUIET=-quiet
122 57 julius
endif
123
 
124 360 julius
# Modelsim variables
125
MGC_VSIM=vsim
126
MGC_VLOG_COMP=vlog
127
MGC_VHDL_COMP=vcom
128
MODELSIM=modelsim
129 6 julius
 
130 360 julius
# Icarus variables
131
ICARUS_COMPILE=iverilog
132
ICARUS_RUN=vvp
133
ICARUS_SCRIPT=icarus.scr
134
ICARUS_SIM_EXE=vlogsim.elf
135
ICARUS=icarus
136 58 julius
 
137 360 julius
#Default simulator is Icarus Verilog
138
# Set SIMULATOR=modelsim to use Modelsim
139
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog - TODO
140
# Set SIMULATOR=icarus to use Icarus Verilog (Default)
141 68 julius
 
142 58 julius
SIMULATOR ?= $(ICARUS)
143
 
144 360 julius
# VPI debugging interface variables
145
VPI_SRC_C_DIR=$(BENCH_VERILOG_DIR)/vpi/c
146
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
147 58 julius
 
148 360 julius
# Modelsim VPI compile variables
149
MODELTECH_VPILIB=msim_jp_vpi.sl
150
# Icarus VPI compile target
151
ICARUS_VPILIB=jp_vpi
152 58 julius
 
153 360 julius
#
154
# Modelsim-specific settings
155
#
156
VOPT_ARGS=$(QUIET) -suppress 2241
157 55 julius
# If VCD dump is desired, tell Modelsim not to optimise
158
# away everything.
159
ifeq ($(VCD), 1)
160 360 julius
#VOPT_ARGS=-voptargs="+acc=rnp"
161
VOPT_ARGS=+acc=rnpqv
162 55 julius
endif
163 360 julius
# VSIM commands
164
# Suppressed warnings - 3009: Failed to open $readmemh() file
165
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
166
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
167
VSIM_ARGS=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
168
# Modelsim VPI settings
169
ifeq ($(VPI), 1)
170
VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
171
VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
172 58 julius
endif
173 360 julius
# Rule to make the VPI library for modelsim
174
$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB): $(VPI_SRCS)
175
        $(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
176 58 julius
 
177 360 julius
#
178
# Icarus Verilog-specific settings
179
#
180 77 rherveille
 
181 360 julius
# Rule to make the VPI library for Icarus
182
$(VPI_SRC_C_DIR)/$(ICARUS_VPILIB): $(VPI_SRCS)
183
        $(MAKE) -C $(VPI_SRC_C_DIR) $(ICARUS_VPILIB)
184 77 rherveille
 
185 360 julius
#
186
# Verilog DUT source variables
187
#
188
# A list of paths under rtl/verilog we wish to exclude for module searching
189
VERILOG_MODULES_EXCLUDE=  include components
190
VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
191
RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v $(VERILOG_MODULES_EXCLUDE_LIST_E) )
192
# Specific files to exclude, currently none.
193
#VERILOG_EXCLUDE=
194
#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); do echo "-e $$exclude"; done)
195
# List of verilog source files, minus excluded files
196
#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v $(VERILOG_EXCLUDE_LIST_E); fi; done)
197
# List of verilog source files, ignoring excludes
198
RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then ls $(RTL_VERILOG_DIR)/$$module/*.v; fi; done)
199 6 julius
 
200 360 julius
# List of verilog includes
201
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
202 6 julius
 
203 360 julius
print-verilog-src:
204
        @echo echo; echo "\t### Verilog source ###"; echo
205
        @echo $(RTL_VERILOG_SRC)
206 51 julius
 
207 360 julius
# Rules to make RTL we might need
208
# Expects modules, if they need making, to have their top verilog file to
209
# correspond to their module name, and the directory should have a make file
210
# and rule which works for this command.
211
# Add name of module to this list, currently only does verilog ones.
212
# Rule 'rtl' is called just before generating DUT modelsim compilation script
213
RTL_TO_CHECK=
214
rtl:
215
        $(Q)for module in $(RTL_TO_CHECK); do \
216
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module $$module.v; \
217
        done
218 6 julius
 
219 55 julius
#
220 360 julius
# VHDL DUT source variables
221 55 julius
#
222 360 julius
# VHDL modules
223
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
224
# VHDL sources
225
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do if [ -d $(RTL_VHDL_DIR)/$$module ]; then ls $(RTL_VHDL_DIR)/$$module/*.vhd; fi; done)
226
#print-vhdl-src:
227
#       @echo echo; echo "\t### VHDL modules and source ###"; echo
228
#       @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
229
#       @echo "source: "$(RTL_VHDL_SRC)
230 6 julius
 
231 40 julius
 
232 360 julius
# Testbench verilog source
233 362 julius
BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v $(DESIGN_NAME)_testbench )
234 40 julius
 
235 362 julius
print-bench-src:
236
        $(Q)echo "\tBench verilog source"; \
237
        echo $(BENCH_VERILOG_SRC)
238
 
239 360 julius
# Testbench source subdirectory detection
240
BENCH_VERILOG_SRC_SUBDIRS=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then echo $(BENCH_VERILOG_DIR)/$$file; fi; done)
241 40 julius
 
242 360 julius
# Compile script generation rules:
243 40 julius
 
244 360 julius
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
245
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
246
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
247
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
248
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
249
        $(Q)echo "+libext+.v" >> $@;
250
        $(Q)for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; fi; done
251
        $(Q)echo >> $@
252 6 julius
 
253 360 julius
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
254
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
255
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "+incdir+"$$path >> $@; done
256
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "-y "$$path >> $@; done
257
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
258
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
259
        $(Q)echo "+libext+.v" >> $@;
260
        $(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
261
        $(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
262
        $(Q)echo >> $@
263 6 julius
 
264 360 julius
# Compile DUT into "work" library
265
work: modelsim_dut.scr #$(RTL_VHDL_SRC)
266
        $(Q)if [ ! -e $@ ]; then vlib $@; fi
267
#       $(Q)echo; echo "\t### Compiling VHDL design library ###"; echo
268
#       $(Q)vcom -93 $(QUIET) $(RTL_VHDL_SRC)
269
        $(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
270
        $(Q)vlog $(QUIET) -f $< $(DUT_TOP)
271 6 julius
 
272 360 julius
# Single compile rule
273
.PHONY : $(MODELSIM)
274
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
275
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
276 362 julius
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
277 360 julius
        $(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
278
        $(Q)echo; echo "\t### Launching simulation ###"; echo
279
        $(Q)vsim $(VSIM_ARGS) tb
280 6 julius
 
281 360 julius
#
282
# Icarus Verilog simulator build and run rules
283
#
284
.PHONY: $(ICARUS_SCRIPT)
285
$(ICARUS_SCRIPT):  $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
286
        $(Q)echo "# Icarus Verilog simulation script" > $@
287
        $(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
288
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
289
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
290
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
291
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
292
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "+incdir+"$$path >> $@; done
293
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do echo "-y "$$path >> $@; done
294
        $(Q)for module in $(RTL_VERILOG_MODULES); do echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; done
295
        $(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
296 362 julius
        $(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
297
        $(Q)echo $(BENCH_TOP) >> $@;
298 360 julius
        $(Q) echo >> $@
299 6 julius
 
300 360 julius
# Icarus design compilation rule
301
$(ICARUS_SIM_EXE): $(ICARUS_SCRIPT) $(TEST_DEFINES_VLG)
302
        $(Q)echo; echo "\t### Compiling ###"; echo
303
        $(Q) $(ICARUS_COMPILE) -s$(RTL_TESTBENCH_TOP) -c $< -o $@
304 49 julius
 
305 360 julius
# Icarus simulation run rule
306
$(ICARUS): $(ICARUS_SIM_EXE) $(ICARUS_VPI_LIB)
307
        $(Q)echo; echo "\t### Launching simulation ###"; echo
308
        $(Q) $(ICARUS_RUN) $(ICARUS_VPI_ARGS) -l ../out/$(ICARUS_RUN).log $<
309 63 julius
 
310 49 julius
 
311
 
312 360 julius
.PHONY: rtl-test
313
rtl-test: clean-sim-test-sw sw clean-test-defines $(TEST_DEFINES_VLG) \
314
        $(SIMULATOR)
315 6 julius
 
316 360 julius
# Run an RTL test followed by checking of generated results
317
rtl-test-with-check: rtl-test
318
        $(Q)$(MAKE) check-test-log; \
319
        if [ $$? -ne 0 ]; then \
320
                echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \
321
        else \
322
                echo; echo "\t### "$(TEST)" test OK ###"; echo; \
323
        fi
324 6 julius
 
325 360 julius
# Do check, don't print anything out
326
rtl-test-with-check-no-print: rtl-test check-test-log
327 6 julius
 
328 360 julius
# Main RTL test loop
329
rtl-tests:
330
        $(Q)for test in $(TESTS); do \
331
                export TEST=$$test; \
332
                $(MAKE) rtl-test-with-check-no-print; \
333
                if [ $$? -ne 0 ]; then break; fi; \
334
                echo; echo "\t### $$test test OK ###"; echo; \
335 6 julius
        done
336
 
337
 
338 360 julius
.PHONY: check-test-log
339
check-test-log:
340
        $(Q)echo "#!/bin/bash" > $@
341
        $(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@
342
        $(Q)echo "check-test-log" >> $@
343
        $(Q)chmod +x $@
344
        $(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo;
345
        $(Q)./$@
346 6 julius
 
347
 
348 360 julius
# Test defines.v file, called recursively, .PHONY to force its generation
349
.PHONY: $(TEST_DEFINES_VLG)
350
$(TEST_DEFINES_VLG):
351
        $(Q)echo "\`define "$(SIM_TYPE)"_SIM" > $@
352
        $(Q)echo "\`define SIMULATOR_"`echo $(SIMULATOR) | tr  "[:lower:]" "[:upper:]"` > $@
353
        $(Q)echo "\`define TEST_NAME_STRING \""$(TEST)"\"" >> $@
354
        $(Q)if [ ! -z $$VCD ]; \
355
                then echo "\`define VCD" >> $@; \
356
        fi
357
        $(Q)if [ ! -z $$VCD_DELAY ]; \
358
                then echo "\`define VCD_DELAY "$$VCD_DELAY >> $@; \
359
        fi
360
        $(Q)if [ ! -z $$VCD_DEPTH ]; \
361
                then echo "\`define VCD_DEPTH "$$VCD_DEPTH >> $@; \
362
        fi
363
        $(Q)if [ ! -z $$VCD_DELAY_INSNS ]; \
364
                then echo "\`define VCD_DELAY_INSNS "$$VCD_DELAY_INSNS >> $@; \
365
        fi
366
        $(Q)if [ ! -z $$END_TIME ]; \
367
                then echo "\`define END_TIME "$$END_TIME >> $@; \
368
        fi
369
        $(Q)if [ ! -z $$END_INSNS ]; \
370
                then echo "\`define END_INSNS "$$END_INSNS >> $@; \
371
        fi
372
        $(Q)if [ ! -z $$PRELOAD_RAM ]; \
373
                then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \
374
        fi
375
        $(Q)if [ -z $$NO_SIM_LOGGING ]; \
376
                then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $@; \
377
        fi
378
        $(Q)if [ ! -z $$VPI ]; \
379
                then echo "\`define VPI_DEBUG" >> $@; \
380
        fi
381
        $(Q)if [ ! -z $$SIM_QUIET ]; \
382
                then echo "\`define SIM_QUIET" >> $@; \
383
        fi
384 6 julius
 
385
 
386 360 julius
#       $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
387
# More possible test defines go here
388 6 julius
 
389 51 julius
 
390 360 julius
# Software make rules (called recursively)
391 393 julius
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
392 6 julius
 
393 360 julius
# Set PRELOAD_RAM=1 to preload the system memory, avoiding lengthy SPI FLASH
394
# bootloader process.
395
#ifeq ($(PRELOAD_RAM), 1)
396
SIM_SW_IMAGE ?=sram.vmem
397
#else
398
#SIM_SW_IMAGE ?=flash.in
399
#endif
400 6 julius
 
401 360 julius
.PHONY : sw
402
sw: $(SIM_SW_IMAGE)
403 6 julius
 
404 360 julius
flash.in: $(TEST_SW_DIR)/$(TEST).flashin
405
        $(Q)if [ -L $@ ]; then unlink $@; fi
406
        $(Q)ln -s $< $@
407 6 julius
 
408 360 julius
sram.vmem: $(TEST_SW_DIR)/$(TEST).vmem
409
        $(Q)if [ -L $@ ]; then unlink $@; fi
410
        $(Q)ln -s $< $@
411 6 julius
 
412 360 julius
.PHONY: $(TEST_SW_DIR)/$(TEST).flashin
413
$(TEST_SW_DIR)/$(TEST).flashin:
414
        $(Q) echo; echo "\t### Compiling software ###"; echo;
415
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).flashin
416 6 julius
 
417 360 julius
.PHONY: $(TEST_SW_DIR)/$(TEST).vmem
418
$(TEST_SW_DIR)/$(TEST).vmem:
419
        $(Q) echo; echo "\t### Compiling software ###"; echo;
420
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
421 63 julius
 
422 360 julius
#
423
# Cleaning rules
424
#
425 362 julius
clean: clean-sim clean-sim-test-sw clean-bootrom clean-vlt clean-out clean-sw
426 63 julius
 
427 360 julius
clean-sim:
428
        $(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo;
429
        $(Q)rm -rf *.* lib_* work transcript check-test-log
430
        $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi
431 6 julius
 
432 360 julius
clean-bootrom:
433
        $(MAKE) -C $(BOOTROM_SW_DIR) clean
434 6 julius
 
435 360 julius
clean-out:
436
        $(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
437 6 julius
 
438 363 julius
# Clean away verilator build path and objects in SystemC path
439 362 julius
clean-vlt:
440
        $(Q)rm -rf $(SIM_VLT_DIR)
441 363 julius
        $(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
442 362 julius
 
443 360 julius
clean-test-defines:
444
        $(Q)rm -f $(TEST_DEFINES_VLG)
445 6 julius
 
446 360 julius
clean-sim-test-sw:
447
        $(Q)if [ -e $(SIM_SW_IMAGE) ]; then unlink $(SIM_SW_IMAGE); fi
448 6 julius
 
449
clean-sw:
450 360 julius
        $(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
451 393 julius
        $(Q) $(MAKE) -C $(SW_DIR)/lib clean-all
452 6 julius
 
453 36 julius
clean-rtl:
454 360 julius
        $(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
455
        for module in $(RTL_TO_CHECK); do \
456
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
457
        done
458 44 julius
 
459 360 julius
# Removes any checked out RTL
460
distclean: clean
461
        $(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
462
        $(Q)for module in $(RTL_TO_CHECK); do \
463
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module distclean; \
464
        done
465 362 julius
 
466
################################################################################
467
# Verilator model build rules
468
################################################################################
469
 
470
VLT_EXE=Vorpsoc_top
471
VLT_SCRIPT=verilator.scr
472
 
473
# Script for Verilator
474
$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) $(BOOTROM_VERILOG)
475
        $(Q)echo "\tGenerating Verilator script"
476
        $(Q)echo "# Verilator sources script" > $@
477
        $(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
478
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
479
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
480
        $(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
481
        $(Q)for module in $(RTL_VERILOG_MODULES); do echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; done
482
        $(Q)echo $(DUT_TOP) >> $@;
483
        $(Q) echo >> $@
484
 
485
 
486
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
487
 
488
 
489
# List of System C models - use this list to link the sources into the Verilator
490
# build directory
491
SYSC_MODELS=OrpsocAccess MemoryLoad
492
 
493 363 julius
ifdef VLT_LINT
494
VLT_FLAGS +=--lint-only
495
endif
496
 
497 362 julius
ifdef VLT_DEBUG
498
VLT_DEBUG_COMPILE_FLAGS = -g
499
# Enabling the following generates a TON of debugging
500
# when running verilator. Not so helpful.
501 363 julius
#VLT_FLAGS = --debug --dump-tree
502 362 julius
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
503
endif
504
 
505 363 julius
# This will build a verilator model that will generate profiling information
506
# suitable for gprof
507
# Run it through gprof after exection with: gprof Vorpsoc_top > gprof.out
508
# then run this through the Verilator tool with:
509
# verilator_profcfunc gprof.out > vprof.out
510
ifdef VLT_EXECUTION_PROFILE_BUILD
511
VLT_CPPFLAGS +=-g -pg
512
# Maybe add these to VLT_CPPFLAGS: -ftest-coverage -fprofile-arcs
513
VLT_FLAGS +=-profile-cfuncs
514
endif
515
 
516
# If set on the command line we build the cycle accurate model which will
517
# generate verilator-specific profiling information. This is useful for
518
# checking the efficiency of the model - not really useful for checking code
519
# or the function of the model.
520
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
521
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt -funroll-loops -fpeel-loops -ftracer
522 362 julius
else
523
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
524
endif
525
 
526 363 julius
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
527
# executable in GDB.
528 362 julius
ifdef VLT_IN_GDB
529
VLT_CPPFLAGS +=-g -O0
530
else
531
# The default optimisation flag applied to all of the cycle accurate model files
532
VLT_CPPFLAGS +=-O3
533
endif
534
 
535
# VCD Enabled by default when building, enable it at runtime
536
VLT_FLAGS +=-trace
537
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
538
 
539 363 julius
# Verilator tuning
540
# Inlining:
541
VLT_FLAGS +=--inline-mult 1
542
# Optimisation option for Verilator scripts
543
VLT_FLAGS +=-O3
544
# X-assign - at reset, all signals are set to random values, helps find rst bugs
545
VLT_FLAGS +=-x-assign unique
546
 
547 362 julius
VLT_TRACEOBJ = verilated_vcd_c
548
 
549 363 julius
 
550 362 julius
# This is the list of extra models we'll issue make commands for
551
# Included is the SystemPerl trace model
552
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
553
 
554
# List of sources for rule sensitivity
555
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
556
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
557
 
558
VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do echo $(SIM_VLT_DIR)/$$mod.o; done)
559
 
560
VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; done)
561
 
562
# Make Verilator build path if it doesn't exist
563
$(SIM_VLT_DIR):
564
        mkdir -p $@
565
 
566
# Dummy files the RTL requires: timescale.v
567
DUMMY_FILES_FOR_VLT=$(SIM_VLT_DIR)/timescale.v
568
$(DUMMY_FILES_FOR_VLT):
569
        $(Q)for file in $@; do if [ ! -e $$file ]; then touch $$file; fi; done
570
 
571
build-vlt: rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) $(SIM_VLT_DIR)/$(VLT_EXE)
572
 
573
# Main Cycle-accurate build rule
574
prepare-vlt: build-vlt
575
        @echo;echo "\tCycle-accurate model compiled successfully"
576
        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo
577
        $(SIM_VLT_DIR)/$(VLT_EXE) -h
578
        @echo;echo
579
 
580
$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a $(SIM_VLT_DIR)/OrpsocMain.o
581
# Final linking of the simulation executable. Order of libraries here is important!
582
        $(Q)echo; echo "\tGenerating simulation executable"; echo
583
        $(Q)cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
584
 
585
# Now compile the top level systemC "testbench" module from the systemC source path
586
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
587
        @echo; echo "\tCompiling top level SystemC testbench"; echo
588
        cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
589
 
590
$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a $(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
591
# Now archive all of the libraries from verilator witht he other modules we might have
592
        @echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
593
        $(Q)cd $(SIM_VLT_DIR) && \
594
        cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
595
        ar rcs lib$(VLT_EXE).a verilated.o; \
596
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
597
                ar rcs lib$(VLT_EXE).a $$SYSCMODEL.o; \
598
        done
599
 
600
$(SIM_VLT_DIR)/verilated.o: $(SYSC_MODEL_SOURCES)
601
        @echo; echo "\tCompiling verilated.o"; echo
602
        $(Q)cd $(SIM_VLT_DIR) && \
603
        export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
604
        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
605
        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
606
        $(MAKE) -f $(VLT_EXE).mk verilated.o
607
 
608
print-sysmod-objs:
609
        $(Q)echo $(VLT_MODULES_OBJS):
610
 
611
$(VLT_MODULES_OBJS):
612
# Compile the module files
613
        @echo; echo "\tCompiling SystemC models"
614
        $(Q)cd $(SIM_VLT_DIR) && \
615
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
616
                echo;echo "\t$$SYSCMODEL"; echo; \
617
                export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
618
                export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
619
                export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
620
                 $(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
621
        done
622
 
623
$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk $(SYSC_MODEL_SOURCES)
624
        @echo; echo "\tCompiling main design"; echo
625
        $(Q)cd $(SIM_VLT_DIR) && \
626
        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
627
        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
628
        $(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
629
 
630
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) $(BENCH_SYSC_SRC_DIR)/libmodules.a
631
# Now call verilator to generate the .mk files
632
        $(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
633
        $(Q)cd $(SIM_VLT_DIR) && \
634 363 julius
        verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
635 362 julius
 
636
# SystemC modules library
637
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
638
        @echo; echo "\tCompiling SystemC modules"; echo
639
        $(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
640
        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
641
 
642
print-vlt-model-link-paths:
643
        $(Q)echo $(VLT_MODEL_LINKS)
644
 
645
$(VLT_MODEL_LINKS):
646
# Link all the required system C model files into the verilator work dir
647
        for SYSCMODEL in $(SYSC_MODELS); do \
648
                if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
649
                echo "\tLinking SystemC model $$SYSCMODEL  Verilator model build path"; \
650
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
651
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h $(SIM_VLT_DIR)/$$SYSCMODEL.h; \
652
                fi; \
653
        done
654
 
655
 
656
################################################################################
657
# Verilator model test rules
658
################################################################################
659
 
660
vlt-test: build-vlt clean-sim-test-sw sw
661
        $(SIM_VLT_DIR)/$(VLT_EXE) $(TEST)
662
 
663
vlt-tests:
664
        $(Q)for test in $(TESTS); do \
665
                export TEST=$$test; \
666
                $(MAKE) vlt-test; \
667
                if [ $$? -ne 0 ]; then break; fi; \
668
                echo; echo "\t### $$test test OK ###"; echo; \
669
        done
670
 
671
 
672
 
673
###############################################################################
674
# Verilator profiled model build rules
675
###############################################################################
676
# To run this, first run a "make prepare-vlt VLT_DO_PROFILING=1" then do a
677
# "make clean" and then a "make prepare-vlt_profiled"
678
# This new make target copies athe results of the profiling back to the right
679
# paths before we create everything again
680
###############################################################################
681
.PHONY: prepare-vlt-profiled
682 363 julius
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda \
683
        clean-vlt-after-profile-run \
684
        rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
685
        $(SIM_VLT_DIR)/$(VLT_EXE)
686 362 julius
 
687
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
688 363 julius
        $(MAKE) -C $(SW_DIR)/dhry dhry.elf NUM_RUNS=5000
689
#       $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf -v -l sim.log --crash-monitor
690
        $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/dhry/dhry.elf
691 362 julius
 
692 363 julius
# Clean all compiled things
693
clean-vlt-after-profile-run:
694
        $(Q)echo "\tCleaning away compiled cycle-accurate files"
695
        $(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)
696
        $(Q)rm -f $(BENCH_SYSC_SRC_DIR)/*.[oa]
697
 
698
#.PHONY: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
699 362 julius
$(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling:
700 363 julius
        $(MAKE) build-vlt VLT_DO_PERFORMANCE_PROFILE_BUILD=1
701 362 julius
 
702
.PHONY: vlt-restore-profileoutput
703
vlt-restore-profileoutput:
704
        @echo;echo "\tRestoring profiling outputs"; echo
705
        $(Q)mkdir -p ../vlt
706
        $(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
707
        $(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
708 363 julius
 
709
 
710
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
711
        $(Q)echo; echo "\tLinting design with Verilator"; echo
712
        $(Q)cd $(SIM_VLT_DIR) && \
713
        verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)

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