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1 6 julius
######################################################################
2
####                                                              ####
3
####  ORPSoCv2 Testbenches Makefile                               ####
4
####                                                              ####
5
####  Description                                                 ####
6
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
7
####  configuring and running different tests on the current      ####
8
####  ORPSoC(v2) design.                                          ####
9
####                                                              ####
10
####  To do:                                                      ####
11
####    * Arrange verilator make rules so that the whole thing    ####
12
####      isn't recompiled when a single SystemC module is        ####
13
####      updated.                                                ####
14
####    * Test if each software test file gets made properly      ####
15
####      before it's run in whatever model we're using           ####
16
####    * Expand software test-suite (uClibc, ecos tests, LTP?)   ####
17
####                                                              ####
18
####  Author(s):                                                  ####
19
####      - jb, jb@orsoc.se                                       ####
20
####                                                              ####
21
####                                                              ####
22
######################################################################
23
####                                                              ####
24
#### Copyright (C) 2009 Authors and OPENCORES.ORG                 ####
25
####                                                              ####
26
#### This source file may be used and distributed without         ####
27
#### restriction provided that this copyright statement is not    ####
28
#### removed from the file and that any derivative work contains  ####
29
#### the original copyright notice and the associated disclaimer. ####
30
####                                                              ####
31
#### This source file is free software; you can redistribute it   ####
32
#### and/or modify it under the terms of the GNU Lesser General   ####
33
#### Public License as published by the Free Software Foundation; ####
34
#### either version 2.1 of the License, or (at your option) any   ####
35
#### later version.                                               ####
36
####                                                              ####
37
#### This source is distributed in the hope that it will be       ####
38
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
39
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
40
#### PURPOSE.  See the GNU Lesser General Public License for more ####
41
#### details.                                                     ####
42
####                                                              ####
43
#### You should have received a copy of the GNU Lesser General    ####
44
#### Public License along with this source; if not, download it   ####
45
#### from http://www.opencores.org/lgpl.shtml                     ####
46
####                                                              ####
47
######################################################################
48
 
49
# Usage:
50
#
51
#       make rtl-tests
52
#
53
#       Run the software tests in the RTL model of the ORPSoC being
54
#       simulated with an event-driven simulator like Icarus. Also
55
#       possible to use Cadence's Verilog simulators with the
56
#       "rtl-nc-tests" target.
57
#
58
#       make vlt-tests
59
#
60
#       Run all the software tests in the RTL model which has been
61
#       converted into a cycle-accurate SystemC model with Verilator.
62
#
63
#       make sim-tests
64
#
65
#       Run all the software tests in the architectural simulator
66
#
67 40 julius
#
68
# Debugging modes:
69
#
70
#       make rtl-debug
71
#
72
#       Enable a GDB stub integrated into the simulation via VPI. This will
73
#       start a simulation, then the GDB server, and allow the user to connect
74
#       using the OpenRISC GDB port. It should provide the same functionality
75
#       as GDB to a physical target, although a little slower.
76
#       It is provided here as an example of how to compile and run an OpenRISC
77
#       model at RTL level with support for debugging from GDB.
78
#       UART output from printf() is enabled by default. The model loads with
79
#       the dhrystone test running as default, but can be changed by defining
80
#       VPI_TEST_SW at the command line. Logging of the processor's execution
81
#       is also disabled by default to speed up simulation.
82
#
83 6 julius
 
84
# Simulation results:
85
#
86
# The results and output of the event-driven simulations are in the
87
# results path, in parallel to the simulation run and bin paths.
88
 
89
# Specific tests:
90
#
91
# To run an individual test, specify it in the variable TESTS when
92
# calling make, eg:
93
#
94
#        make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
95
 
96
# UART printf:
97
#
98
# It is possible to enable printf to the console via the UART when
99
# running the event-driven simulators. To do this define UART_PRINTF=1
100
# when calling make. The SystemC cycle-acccurate model uses this by
101
# default.
102
# Also note when switching between runs with and without UART printf
103
# enabled, run a clean-sw so the library files are recompiled when
104
# the tests are run - this is not done automatically.
105
 
106
# VCDs:
107
#
108
# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
109
# to inspect the internals of the system graphically) files can be
110
# generated by defining a variable VCD, eg.
111
#
112
#       make rtl-tests VCD=1
113
#
114
# and a dump file will be created in the simulation results directory,
115
# and named according to the test run which generated it. This is
116
# possible for both event-driven and cycle-accurate simulations.
117
# However the cycle-accurate
118
 
119
# NO_SIM_LOGGING:
120
#
121
# It is possible to speed up the event-driven simulation slightly by
122
# disabling log output of the processor's state to files by defining
123
# NO_SIM_LOGGING, eg:
124
#
125
#       make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
126
#
127
 
128
# Cleaning:
129
# A simple "make clean" cleans everything - software and all temporary
130
# simulation files and directories. To clean just the software run:
131
#
132
#       make clean-sw
133
#
134
# and to clean just the temporary simulation files (including VCDs,
135
# results logs - everything under, and including, sim/results/, run
136
#
137
#       make clean-sim
138
#
139
 
140
# Note:
141
#
142
# The way each of the test loops is written is probably a bit overly complex
143
# but this is to save maintaining, and calling, multiple files.
144
#
145
 
146
# Model configuration:
147
#
148
# Currently, the ORPSoCv2, by default, contains an internal SRAM (configurable
149
# size - check the defparam in rtl/verilog/orpsoc_top.v), standard OR1200 (check
150
# the config in rtl/verilog/or1200_defines.v) and UART.
151
# Switches can be passed to enable certain parts of the design if testing with
152
# these is desired.
153
#
154
# SDRAM and controller
155
#
156
# To enable the use of SDRAM, define USE_SDRAM when calling the sim -this
157
# only has an effect in the event-driven simulators as the external SDRAM model
158
# is not availble in SystemC format. eg:
159
#
160
#       make rtl-tests USE_SDRAM=1
161
#
162
# This not only enables SDRAM but also enables the booting from external SPI
163
# interfaced flash memory. This causes significant increase in the time taken
164
# for simulation as the program to test is first loaded out of SPI flash memory
165
# and into SDRAM before it is executed. Although this more closely mimics the
166
# behaviour of the hardware, for simulation purposes it is purely time-consuming
167
# however it may be useful to track down any problems with this boot-loading
168
# process. Therefore, becuase it enables SDRAM memory, ir also enables the flash
169
# memory model and SPI controller inside ORPSoC.
170
#
171
# Ethernet
172
#
173
# Ethernet is disabled by default. This is due to the fact that it is not
174
# supported in the verilator/systemC model. Also, there is currently no software
175
# which tests it in any meaningful way.
176
#
177
 
178
#
179
# Event-driven simulation compilation
180
#
181
# The way the event-driven simulations are compiled is simply using the
182
# configuration script file in this directory, currently called icarus.scr -
183
# however it is first processesed to replace the variables, beginning with $'s,
184
# with the appropriate paths. Instead of naming each file to be compiled, the
185
# paths to be searched for each module are instead defined ( -y paths), and
186
# only the toplevel testbench and library source files are explicitly named.
187
# This simplifies the script, and also requires that the name of each verilog
188
# source file is the same as the module it contains (a good convention
189
# regardless.) In addition to the script/command file, defines are passed to
190
# the compiler via the command line in the EVENT_SIM_FLAGS variable.
191
# Additionally, a source file, test_define.v, is created with  some defines
192
# that cannot be passed to the compiled reliably (there are differences between
193
# the way, for instance, icarus and ncverilog parse strings +define+'d on the
194
# command line). This file is then included at the appropriate places.
195
# It is probably not ideal that the entire design be re-compiled for each test,
196
# but currently the design is small enough so that this doesn't cause a
197
# significant overhead, unlike the cycle-accurate model compile time.
198
#
199
 
200
#
201
# SystemC cycle-accurate model compilation
202
#
203
# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
204
# behind this is verilator, which processes the RTL sources and generates a c++
205
# description of the system. This c++ description is then compiled with a
206
# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
207
# model, as well as any other modules - in this case a reset generation, UART
208
# decoder, and monitor module are included at the top level. These additional
209
# modules and models are written in SystemC and compiled all together with the
210
# cycle-accurate ORPSoC model to create the simulation executable. Finally this
211
# executable is run and should be a cycle-representation of the system. VCDs
212
# can be generated if enabled. The compiled mentioned above is all done with
213
# the GNU c++ compiler, g++.
214
# The compilation process is a little more tricky than a typical even-driven
215
# simulator. It proceeds basically by generating the makefiles for compiling
216
# the design with verilator, running these makes which produces a library
217
# containing the cycle-accurate ORPSoC design, compiling the additional
218
# top-level, and testbench, systemC models into a library, and then linking it
219
# all together into the simulation executable.
220
# The major advantage of the cycle-accurate model is that it is quicker, in
221
# terms of simulated cycles/second, when compared with event-driven simulators.
222
# It is, of course, less accurate in that it cannot model propegation delays.
223
# However this is usually not an issue for simulating a design which is known
224
# to synthesize and run OK. It is very useful for running complex software,
225
# such as the linux kernel and real-time OS applications, which generally
226
# require long simulation times.
227
# Currently the cycle-accurate model being used doesn't contain much more than
228
# the processor and a UART, however it's exepected in future this will be
229
# expanded on and more complex software test suites will be implemented to put
230
# the system through its paces.
231
#
232
 
233
 
234
# Name of
235
# the directory we're currently in
236
CUR_DIR=$(shell pwd)
237
 
238
# The root path of the whole project
239
PROJECT_ROOT=$(CUR_DIR)/../..
240
 
241
# Tests is only defined if it wasn't already defined when make was called
242
# This is the default list of every test that is currently possible
243
TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
244
 
245
# Paths to other important parts of this test suite
246
SIM_DIR=$(PROJECT_ROOT)/sim
247
SIM_RUN_DIR=$(SIM_DIR)/run
248
SIM_BIN_DIR=$(SIM_DIR)/bin
249
SIM_RESULTS_DIR=$(SIM_DIR)/results
250
SIM_VLT_DIR=$(SIM_DIR)/vlt
251
BENCH_DIR=$(PROJECT_ROOT)/bench
252
BACKEND_DIR=$(PROJECT_ROOT)/backend
253
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
254
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
255
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
256
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
257
RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
258
SW_DIR=$(PROJECT_ROOT)/sw
259
 
260
ICARUS=iverilog
261
ICARUS_VVP=vvp
262
ICARUS_COMMAND_FILE=icarus.scr
263
VLT_COMMAND_FILE=verilator.scr
264
SIM_SUCCESS_MESSAGE=deaddead
265
 
266
ARCH_SIM_EXE=or32-elf-sim
267
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
268
 
269
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
270
# command line becuase it's used by many different modules and it's easier
271
# to do it this way than make them all include a file.
272
ifdef USE_SDRAM
273
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)"
274
endif
275
 
276
# Enable ethernet if defined on the command line
277
ifdef USE_ETHERNET
278
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET)"
279
endif
280
 
281
SIM_FLASH_MEM_FILE="flash.in"
282
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
283
SIM_SRAM_MEM_FILE="sram.vmem"
284
 
285
TESTS_PASSED=0
286
TESTS_PERFORMED=0;
287
 
288
################################################################################
289
# Event-driven simulator build rules (Icarus, NCSim)
290
################################################################################
291
 
292
.PHONY: prepare_rtl
293
prepare_rtl:
294
        @cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
295
        @cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v
296
 
297
 
298
ifdef UART_PRINTF
299
TEST_SW_MAKE_OPTS=UART_PRINTF=1
300
endif
301
 
302
.PHONY: prepare_sw
303
prepare_sw:
304
        @$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
305
        @$(MAKE) -C $(SW_DIR)/utils all
306
 
307
# A rule with UART_PRINTF hard defined ... used by verilator make sw
308
prepare_sw_uart_printf:
309
        @$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
310
        @$(MAKE) -C $(SW_DIR)/utils all
311
 
312 40 julius
prepare_dirs:
313
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
314 6 julius
 
315
# Rough guide to how these tests work:
316
# First, the couple of custom, required, software tools under sw/utils are
317
# compiled, and then the software library files.
318
# Next the few verilog files that need preperation are taken care of.
319
# The test begins by starting a loop in bash using on the strings defined in
320
# TESTS. Each one corresponds to a certain module of software for the OpenRISC
321
# that is included in this test suite. Under the sw/ path is a set of paths,
322
# and all except the support/ and utils/ paths contain code which is run to
323
# test the OR1k used in this test suite. For each of these software modules,
324
# it is possible that different tests are done using the same module. These
325
# tests can vary by either using different levels of optimisation during
326
# compilation, and/or by having the OR1k's caches enabled or disabled.
327
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is
328
# usually just ../results, log files, and optionally VCD files, are created for
329
# inspection later and are named according to the test. Inspect the file
330
# bench/verilog/or1200_monitor.v to find out in detail what each log consists
331
# of.
332
# For each test, a few things occur. First the software that will run inside
333
# the simulated OR1k system is compiled, converted to a format which can be
334
# read
335
# into the flash memory model via $readmemh() and linked to the sim/run
336
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a
337
# compilation script for icarus is generated, containing a list of all the
338
# RTL files and include directories. Next, an include file for the verilog
339
# testbench is generated, containing a string of the name of the current
340
# test, path to the results directory (for VCD generation) and any other
341
# things which might vary from test to test. This is not done by +define
342
# lines in the icarus script because of string handling incosistencies
343
# between different simulators and shells.
344
# Once all the files are generated, icarus is called to compile the rtl
345
# design, and then run it. Each of the tested software modules have code which
346
# will trigger the simulation to be stopped by use of the l.nop instruction
347
# with an immediate value of 1. When the simulation finishes, the simulation
348
# executable exits and the log of the simulation is inspected for the expected
349
# output. Currently, the string "deaddead" indicates that the software
350
# completed successfully. This is counted as the ORPSoC "passing" the test. In
351
# fact, whether the system did the right thing or not requires more
352
# inspection, but roughly this is a good indicator that nothing major went
353
# wrong.
354
# Once the current test is finished, the next begins with the compilation of its
355
# software and linking of the resulting hex file to the run path, etc.
356
# Main RAM setup - (RTL simulation with Icarus/NCSim only!):
357
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation
358
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1
359
# Verilator defaults to internal memories
360 40 julius
rtl-tests: prepare_sw_uart_printf prepare_rtl prepare_dirs
361 6 julius
        @echo
362
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
363
        @echo
364
        @for TEST in $(TESTS); do \
365
                echo "################################################################################"; \
366
                echo; \
367
                echo "\t#### Current test: $$TEST ####"; echo; \
368
                echo "\t#### Compiling software ####"; echo; \
369
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
370
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
371
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
372
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
373
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
374
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
375
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
376
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
377
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
378
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
379
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
380
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
381
                if [ ! -z $$VCD ]; \
382
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
383
                fi; \
384
                if [ ! -z $$UART_PRINTF ]; \
385
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
386
                fi; \
387
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
388
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
389 40 julius
                if [ ! -z $$SIM_LOGGING ]; then \
390 6 julius
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
391
                fi; \
392
                echo ; \
393
                echo "\t#### Compiling RTL ####"; \
394
                rm -f $(SIM_RUN_DIR)/a.out; \
395
                $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS); \
396
                echo; \
397
                echo "\t#### Beginning simulation ####"; \
398
                time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \
399
                if [ $$? -gt 0 ]; then exit $$?; fi; \
400
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
401
                echo; echo "\t####"; \
402
                if [ $$TEST_RESULT -gt 0 ]; then \
403
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
404
                else    echo "\t#### Test $$TEST FAILED ####";\
405
                fi; \
406
                echo "\t####"; echo; \
407
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
408
        done; \
409
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
410
 
411
 
412
 
413
# Use NCSIM instead of icarus
414 40 julius
rtl-nc-tests: prepare_sw prepare_rtl prepare_dirs
415 6 julius
        @echo
416
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
417
        @echo
418
        @for TEST in $(TESTS); do \
419
                echo "################################################################################"; \
420
                echo; \
421
                echo "\t#### Current test: $$TEST ####"; echo; \
422
                echo "\t#### Compiling software ####"; echo; \
423
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
424
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST; \
425
                rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
426
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
427
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_twobyte_sizefirst.hex $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
428
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST_fourbyte.hex $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
429
                sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
430
                        -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
431
                        -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
432
                        -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
433
                        -e \\!^//.*\$$!d -e \\!^\$$!d ; \
434
                echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
435
                if [ ! -z $$VCD ]; \
436
                        then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
437
                        echo "+access+r" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
438
                fi; \
439
                if [ ! -z $$UART_PRINTF ]; \
440
                        then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
441
                fi; \
442
                if [ ! -z $$USE_SDRAM ]; then \
443
                        echo "\`define USE_SDRAM" >> $(SIM_RUN_DIR)/test_define.v; \
444
                fi; \
445
                echo "+nocopyright" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
446
                echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \
447
                echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
448
                echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
449
                if [ -z $$NO_SIM_LOGGING ]; then \
450
                        echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
451
                fi; \
452
                echo ; \
453
                echo "\t#### Beginning simulation ####"; \
454
                time -p ncverilog -f $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated -Q -l $(SIM_RESULTS_DIR)/$$TEST-ius-out.log $(EVENT_SIM_FLAGS); \
455
                if [ $$? -gt 0 ]; then exit $$?; fi; \
456
                TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
457
                echo; echo "\t####"; \
458
                if [ $$TEST_RESULT -gt 0 ]; then \
459
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
460
                else    echo "\t#### Test $$TEST FAILED ####";\
461
                fi; \
462
                echo "\t####"; echo; \
463
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
464
        done; \
465
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
466
 
467
################################################################################
468 40 julius
# RTL simulation in Icarus with GDB stub via VPI for debugging
469
################################################################################
470
# This compiles a version of the system which starts up the dhrystone nocache
471
# test, and launches the simulator with a VPI module that provides a GDB stub
472
# allowing the OpenRISC compatible GDB to connect and debug the system.
473
# The launched test can be changed by defining VPI_TEST_SW on the make line
474
VPI_DIR=$(BENCH_VERILOG_DIR)/vpi
475
VPI_C_DIR=$(VPI_DIR)/c
476
VPI_VERILOG_DIR=$(VPI_DIR)/verilog
477
VPI_LIB_NAME=jp_vpi
478
ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)
479
VPI_TEST_SW ?= dhry-nocache-O2
480
 
481
prepare_vpi:
482
## Build the VPI library
483
        $(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)
484
 
485
clean_vpi:
486
        $(MAKE) -C $(VPI_C_DIR) clean
487
 
488
rtl-debug: prepare_sw_uart_printf prepare_rtl prepare_vpi prepare_dirs
489
## Prepare the software for the test
490
        @echo "\t#### Compiling software ####"; echo; \
491
        CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \
492
        $(MAKE) -C $$CURRENT_TEST_SW_DIR $(VPI_TEST_SW) $(TEST_SW_MAKE_OPTS); \
493
        rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
494
        rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
495
        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
496
        ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)
497
## Generate the icarus script we'll compile with
498
        @sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
499
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
500
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
501
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
502
                -e \\!^//.*\$$!d -e \\!^\$$!d
503
## Add a couple of extra defines to the icarus compile script
504
        @echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
505
## The define that enables the VPI debug module
506
        @echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
507
        @if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi
508
## Unless NO_UART_PRINTF=1 we use printf via the UART
509
        @if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi
510
        @echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
511
        @echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
512
        @if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
513
        @echo
514
        @echo "\t#### Compiling RTL ####"
515
        @rm -f $(SIM_RUN_DIR)/a.out
516
        @$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
517
        @echo
518
        @echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
519
        @$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
520
 
521
################################################################################
522 6 julius
# Verilator model build rules
523
################################################################################
524
 
525
 
526
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
527
 
528
 
529
# List of System C models - use this list to link the sources into the Verilator
530
# build directory
531
SYSC_MODELS=OrpsocAccess TraceSC
532
 
533
ifdef VCD
534
VLT_FLAGS +=-trace
535
endif
536
 
537
# Only need the trace target if we are tracing
538
ifneq (,$(findstring -trace, $(VLT_FLAGS)))
539
VLT_TRACEOBJ = SpTraceVcdC
540
endif
541
 
542
# This is the list of extra models we'll issue make commands for
543
# Included is the SystemPerl trace model
544
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
545
 
546
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
547
 
548
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
549
# Final linking of the simulation executable. Order of libraries here is important!
550
        @echo; echo "\tGenerating simulation executable"; echo
551
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
552
 
553
$(SIM_VLT_DIR)/OrpsocMain.o:
554
# Now compile the top level systemC "testbench" module
555
        @echo; echo "\tCompiling top level SystemC testbench"; echo
556
        cd $(SIM_VLT_DIR) && g++ -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
557
 
558
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
559
# Now archive all of the libraries from verilator witht he other modules we might have
560
        @echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
561
        @cd $(SIM_VLT_DIR) && \
562
        cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
563
        ar rcs libVorpsoc_top.a verilated.o; \
564
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
565
                ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
566
        done
567
 
568
$(SIM_VLT_DIR)/verilated.o:
569
        @echo; echo "\tCompiling verilated.o"; echo
570
        @cd $(SIM_VLT_DIR) && \
571
        $(MAKE) -f Vorpsoc_top.mk verilated.o
572
 
573
.PHONY: vlt_modules_compile
574
vlt_modules_compile:
575
# Compile the module files
576
        @echo; echo "\tCompiling SystemC models"
577
        @cd $(SIM_VLT_DIR) && \
578
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
579
                echo;echo "\t$$SYSCMODEL"; echo; \
580
                $(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
581
        done
582
 
583
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
584
        @echo; echo "\tCompiling main design"; echo
585
        @cd $(SIM_VLT_DIR) && \
586
        $(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
587
 
588
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
589
# Now call verilator to generate the .mk files
590
        @echo; echo "\tGenerating makefiles with Verilator"; echo
591
        cd $(SIM_VLT_DIR) && \
592
        verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
593
 
594
# SystemC modules library
595
$(SIM_VLT_DIR)/libmodules.a:
596
        @echo; echo "\tCompiling SystemC modules"; echo
597
        @$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make
598
 
599
 
600
# Verilator command script
601
# Generate the compile script to give Verilator
602
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated:
603
        @echo; echo "\tGenerating verilator compile script"; echo
604
        @sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
605
                -e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)!              \
606
                -e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)!                  \
607
                -e s!\$$BACKEND_DIR!$(BACKEND_DIR)!                  \
608
                -e \\!^//.*\$$!d -e \\!^\$$!d;
609
 
610
.PHONY: vlt_model_links
611
vlt_model_links:
612
# Link all the required system C model files into the verilator work dir
613
        @echo; echo "\tLinking SystemC model source to verilator build path"; echo
614
        @if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
615
        @cd $(SIM_VLT_DIR) && \
616
        for SYSCMODEL in $(SYSC_MODELS); do \
617
                if [ ! -e $$SYSCMODEL.cpp ]; then \
618
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
619
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
620
                fi; \
621
        done
622
 
623
 
624
################################################################################
625
# Verilator test loop
626
################################################################################
627
 
628
# Verilator defaults to internal memories
629 40 julius
vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_dirs prepare_vlt
630 6 julius
        @echo
631
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
632
        @echo
633
        @for TEST in $(TESTS); do \
634
                echo "################################################################################"; \
635
                echo; \
636
                echo "\t#### Current test: $$TEST ####"; echo; \
637
                echo "\t#### Compiling software ####"; echo; \
638
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
639
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
640
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
641
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
642
                echo "\t#### Beginning simulation ####"; \
643
                time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
644
                if [ $$? -gt 0 ]; then exit $$?; fi; \
645
                TEST_RESULT=1; \
646
                echo; echo "\t####"; \
647
                if [ $$TEST_RESULT -gt 0 ]; then \
648
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
649
                else    echo "\t#### Test $$TEST FAILED ####";\
650
                fi; \
651
                echo "\t####"; echo; \
652
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
653
        done; \
654
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
655
 
656
 
657
 
658
################################################################################
659
# Architectural simulator test loop
660
################################################################################
661
 
662
# Verilator defaults to internal memories
663
sim-tests: prepare_sw_uart_printf
664
        @if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
665
        @echo
666
        @echo "Beginning loop that will complete the following tests: $(TESTS)"
667
        @echo
668
        @for TEST in $(TESTS); do \
669
                echo "################################################################################"; \
670
                echo; \
671
                echo "\t#### Current test: $$TEST ####"; echo; \
672
                echo "\t#### Compiling software ####"; echo; \
673
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
674
                $(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
675
                rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
676
                ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
677
                echo;echo "\t#### Launching architectural simulator ####"; \
678
                time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
679
                if [ $$? -gt 0 ]; then exit $$?; fi; \
680
                if [ `tail -n 10 $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log | grep -c $(SIM_SUCCESS_MESSAGE)` -gt 0 ]; then \
681
                        TEST_RESULT=1; \
682
                fi; \
683
                echo; echo "\t####"; \
684
                if [ $$TEST_RESULT -gt 0 ]; then \
685
                        echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
686
                else    echo "\t#### Test $$TEST FAILED ####";\
687
                fi; \
688
                echo "\t####"; echo; \
689
                TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
690
                unlink $(SIM_RUN_DIR)/$$TEST.or32; \
691
        done; \
692
        echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
693
 
694
 
695
 
696
################################################################################
697
# Cleaning rules
698
################################################################################
699
 
700 40 julius
clean: clean-sw clean-sim clean-sysc clean-rtl clean_vpi
701 6 julius
 
702
clean-sw:
703
        @for TEST in $(TESTS); do \
704
                echo "Current test: $$TEST"; \
705
                CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
706
                echo "Current test sw directory: " $$CURRENT_TEST_SW_DIR; \
707
                $(MAKE) -C $$CURRENT_TEST_SW_DIR clean; \
708
        done
709
        $(MAKE) -C $(SW_DIR)/support clean
710
        $(MAKE) -C $(SW_DIR)/utils clean
711
 
712
clean-sim:
713
        rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR)
714 36 julius
 
715
clean-sysc:
716
# Clean away dependency files generated by verilator
717
        rm -rf $(BENCH_SYSC_SRC_DIR)/*.d
718
 
719
clean-rtl:
720
# Clean away temporary verilog source files
721
        rm -f $(RTL_VERILOG_DIR)/intercon.v
722
        rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v

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