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######################################################################
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#### ####
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#### ORPSoCv2 Testbenches Makefile ####
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#### ####
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#### Description ####
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#### ORPSoCv2 Testbenches Makefile, containing rules for ####
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#### configuring and running different tests on the current ####
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#### ORPSoC(v2) design. ####
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#### ####
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#### To do: ####
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#### * Test if each software test file gets made properly ####
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#### before it's run in whatever model we're using ####
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#### * Expand software test-suite (uClibc, ecos tests, LTP?) ####
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#### ####
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#### Author(s): ####
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#### - jb, jb@orsoc.se ####
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#### ####
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#### ####
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######################################################################
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#### ####
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#### Copyright (C) 2009 Authors and OPENCORES.ORG ####
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#### ####
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#### This source file may be used and distributed without ####
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#### restriction provided that this copyright statement is not ####
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#### removed from the file and that any derivative work contains ####
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#### the original copyright notice and the associated disclaimer. ####
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#### ####
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#### This source file is free software; you can redistribute it ####
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#### and/or modify it under the terms of the GNU Lesser General ####
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#### Public License as published by the Free Software Foundation; ####
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#### either version 2.1 of the License, or (at your option) any ####
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#### later version. ####
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#### ####
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#### This source is distributed in the hope that it will be ####
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#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
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#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
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#### PURPOSE. See the GNU Lesser General Public License for more ####
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#### details. ####
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#### ####
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#### You should have received a copy of the GNU Lesser General ####
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#### Public License along with this source; if not, download it ####
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#### from http://www.opencores.org/lgpl.shtml ####
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#### ####
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######################################################################
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# Usage:
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#
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# make rtl-tests
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#
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# Run the software tests in the RTL model of the ORPSoC being
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# simulated with an event-driven simulator like Icarus. It's also
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# possible to use Modelsim's vsim and Cadence's Verilog simulators.
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#
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# make vlt-tests
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#
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# Run all the software tests in the RTL model which has been
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# converted into a cycle-accurate SystemC model with Verilator.
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#
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# make sim-tests
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#
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# Run all the software tests in the architectural simulator
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#
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#
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# Debugging modes:
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#
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# make rtl-debug
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#
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# Enable a GDB stub integrated into the simulation via VPI. This will
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# start a simulation, then the GDB server, and allow the user to connect
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# using the OpenRISC GDB port. It should provide the same functionality
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# as GDB to a physical target, although a little slower.
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# It is provided here as an example of how to compile and run an OpenRISC
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# model at RTL level with support for debugging from GDB.
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# UART output from printf() is enabled by default. The model loads with
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# the dhrystone test running as default, but can be changed by defining
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# VPI_TEST_SW at the command line. Logging of the processor's execution
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# is also disabled by default to speed up simulation.
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#
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# Simulation results:
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#
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# The results and output of the event-driven simulations are in the
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# results path, in parallel to the simulation run and bin paths.
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# Specific tests:
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#
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# To run an individual test, specify it in the variable TESTS when
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# calling make, eg:
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#
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# make rtl-tests TESTS="mmu-nocache mul-idcd-O2"
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# UART printf:
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#
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# It is possible to enable printf to the console via the UART when
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# running the event-driven simulators. To do this define UART_PRINTF=1
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# when calling make. The SystemC cycle-acccurate model uses this by
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# default.
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# Also note when switching between runs with and without UART printf
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# enabled, run a clean-sw so the library files are recompiled when
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# the tests are run - this is not done automatically.
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# VCDs:
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#
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# VCD (value change dumps, usable in a waveform viewer, such as gtkwave
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# to inspect the internals of the system graphically) files can be
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# generated by defining a variable VCD, eg.
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#
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# make rtl-tests VCD=1
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#
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# and a dump file will be created in the simulation results directory,
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# and named according to the test run which generated it. This is
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# possible for both event-driven and cycle-accurate simulations.
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# However the cycle-accurate
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# NO_SIM_LOGGING:
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#
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# It is possible to speed up the event-driven simulation slightly by
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# disabling log output of the processor's state to files by defining
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# NO_SIM_LOGGING, eg:
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#
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# make rtl-tests TESTS=except-icdc NO_SIM_LOGGING=1
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#
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# Cleaning:
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# A simple "make clean" cleans everything - software and all temporary
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# simulation files and directories. To clean just the software run:
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#
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# make clean-sw
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#
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# and to clean just the temporary simulation files (including VCDs,
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# results logs - everything under, and including, sim/results/, run
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#
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# make clean-sim
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#
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# Note:
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#
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# The way each of the test loops is written is probably a bit overly complex
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# but this is to save maintaining, and calling, multiple files.
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#
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# Model configuration:
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#
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# Currently, the ORPSoCv2, by default, contains an internal SRAM (configurable
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# size - check the defparam in rtl/verilog/orpsoc_top.v), standard OR1200 (check
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# the config in rtl/verilog/or1200_defines.v) and UART.
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# Switches can be passed to enable certain parts of the design if testing with
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# these is desired.
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#
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# SDRAM and controller
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#
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# To enable the use of SDRAM, define USE_SDRAM when calling the sim -this
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# only has an effect in the event-driven simulators as the external SDRAM model
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# is not availble in SystemC format. eg:
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#
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# make rtl-tests USE_SDRAM=1
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#
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# This not only enables SDRAM but also enables the booting from external SPI
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# interfaced flash memory. This causes significant increase in the time taken
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# for simulation as the program to test is first loaded out of SPI flash memory
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# and into SDRAM before it is executed. Although this more closely mimics the
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# behaviour of the hardware, for simulation purposes it is purely time-consuming
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# however it may be useful to track down any problems with this boot-loading
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# process. Therefore, becuase it enables SDRAM memory, it also enables the flash
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# memory model and SPI controller inside ORPSoC.
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#
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# Ethernet
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#
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# Ethernet is disabled by default. This is due to the fact that it is not
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# supported in the verilator/systemC model. Also, there is currently no software
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# which tests it in any meaningful way.
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#
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#
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# Event-driven simulation compilation
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#
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# The way the event-driven simulations are compiled is simply using the
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# configuration script file in this directory, currently called icarus.scr -
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# however it is first processesed to replace the variables, beginning with $'s,
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# with the appropriate paths. Instead of naming each file to be compiled, the
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# paths to be searched for each module are instead defined ( -y paths), and
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# only the toplevel testbench and library source files are explicitly named.
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# This simplifies the script, and also requires that the name of each verilog
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# source file is the same as the module it contains (a good convention
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# regardless.) In addition to the script/command file, defines are passed to
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# the compiler via the command line in the EVENT_SIM_FLAGS variable.
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# Additionally, a source file, test_define.v, is created with some defines
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# that cannot be passed to the compiled reliably (there are differences between
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# the way, for instance, icarus and ncverilog parse strings +define+'d on the
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# command line). This file is then included at the appropriate places.
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# It is probably not ideal that the entire design be re-compiled for each test,
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# but currently the design is small enough so that this doesn't cause a
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# significant overhead, unlike the cycle-accurate model compile time.
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#
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#
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# SystemC cycle-accurate model compilation
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#
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# A new addition to ORPSoC v2 is the cycle-accurate model. The primary enabler
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# behind this is verilator, which processes the RTL source and generates a c++
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# description of the system. This c++ description is then compiled, with a
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# SystemC wrapper. Finally a top-level SystemC testbench instantiates the
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# model, and other useful modules - in this case a reset generation, UART
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# decoder, and monitor module are included at the top level. These additional
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# modules and models are written in SystemC. Finally, everything is linked with
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# the cycle-accurate ORPSoC model to create the simulation executable. This
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# executable is the cycle-representation of the system.
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#
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# Run the resulting executable with the -h switch for usage.
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#
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# The compilation is all done with the GNU c++ compiler, g++.
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#
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# The compilation process is a little more complicated than the event-driven
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# simulator. It proceeds basically by generating the makefiles for compiling
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# the design with verilator, running these makes which produces a library
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# containing the cycle-accurate ORPSoC design, compiling the additional
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# top-level, and testbench, systemC models into a library, and then linking it
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# all together into the simulation executable.
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#
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# The major advantage of the cycle-accurate model is that it is quicker, in
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# terms of simulated cycles/second, when compared with event-driven simulators.
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# It is, of course, less accurate in that it cannot model propegation delays.
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# However this is usually not an issue for simulating a design which is known
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# to synthesize and run OK. It is very useful for running complex software,
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# such as the linux kernel and real-time OS applications, which generally
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# result in long simulation times.
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#
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# Currently the cycle-accurate model being used doesn't contain much more than
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# the processor and a UART, however it's exepected in future this will be
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# expanded on and more complex software test suites will be implemented to put
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# the system through its paces.
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#
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#
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#
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# Name of the directory we're currently in
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CUR_DIR=$(shell pwd)
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# The root path of the whole project
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PROJECT_ROOT ?=$(CUR_DIR)/../..
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# Tests is only defined if it wasn't already defined when make was called
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# This is the default list of every test that is currently possible
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TESTS ?= basic-nocache cbasic-nocache-O2 dhry-nocache-O2 except-nocache mmu-nocache mul-nocache-O2 syscall-nocache tick-nocache uart-nocache basic-icdc cbasic-icdc-O2 dhry-icdc-O2 except-icdc mmu-icdc mul-icdc-O2 syscall-icdc tick-icdc uart-icdc
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# Paths to other important parts of this test suite
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SIM_DIR ?=$(PROJECT_ROOT)/sim
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SIM_RUN_DIR=$(SIM_DIR)/run
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SIM_BIN_DIR=$(SIM_DIR)/bin
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SIM_RESULTS_DIR=$(SIM_DIR)/results
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SIM_VLT_DIR=$(SIM_DIR)/vlt
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BENCH_DIR=$(PROJECT_ROOT)/bench
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BACKEND_DIR ?=$(PROJECT_ROOT)/backend
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BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
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BENCH_TOP_VERILOG_DIR ?= $(BENCH_DIR)/verilog
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BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
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BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
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BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
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RTL_VERILOG_DIR=$(PROJECT_ROOT)/rtl/verilog
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SW_DIR=$(PROJECT_ROOT)/sw
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ICARUS=iverilog
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ICARUS_VVP=vvp
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VSIM_COMP=vlog
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VSIM=vsim
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NCVERILOG=ncverilog
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ICARUS_COMMAND_FILE=icarus.scr
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VLT_COMMAND_FILE=verilator.scr
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SIM_SUCCESS_MESSAGE=deaddead
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MGC_COMMAND_FILE=modelsim.scr
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ARCH_SIM_EXE=or32-elf-sim
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ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
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# Set V=1 when calling make to enable verbose output
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# mainly for debugging purposes.
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ifeq ($(V), 1)
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Q=
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else
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Q=@
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endif
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# If USE_SDRAM is defined we'll add it to the simulator's defines on the
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# command line becuase it's used by many different modules and it's easier
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# to do it this way than make them all include a file.
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ifdef USE_SDRAM
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EVENT_SIM_FLAGS +=USE_SDRAM=$(USE_SDRAM)
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endif
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# Enable ethernet if defined on the command line
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ifdef USE_ETHERNET
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EVENT_SIM_FLAGS +=USE_ETHERNET=$(USE_ETHERNET) USE_ETHERNET_IO=$(USE_ETHERNET)
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# Extra tests we do if ethernet is enabled
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TESTS += eth-basic eth-int
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endif
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DASH_D_EVENT_SIM_FLAGS=$(shell for flag in $(EVENT_SIM_FLAGS); do echo "-D "$$flag; done)
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PLUS_DEFINE_EVENT_SIM_FLAGS=$(shell for flag in $(EVENT_SIM_FLAGS); do echo "+define+"$$flag; done)
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#Default simulator is Icarus Verilog
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# Set SIMULATOR=vsim to use Modelsim
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# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog
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SIMULATOR ?= $(ICARUS)
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# Set the command file to use, simulator dependent
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ifeq ($(SIMULATOR), $(ICARUS))
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# Icarus Verilog Simulator
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SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
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endif
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ifeq ($(SIMULATOR), $(VSIM))
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# Modelsim has own command file (it's a little more stupid than Icarus & NC)
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SIM_COMMANDFILE=$(MGC_COMMAND_FILE)
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endif
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ifeq ($(SIMULATOR), $(NCVERILOG))
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# NCVerilog uses same command file as Icarus
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SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE)
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endif
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55 |
julius |
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated
|
322 |
51 |
julius |
|
323 |
55 |
julius |
# When Modelsim is selected as simulator, we compile
|
324 |
|
|
# the ORPSoC system into one library called orpsoc and
|
325 |
|
|
# then simply re-compile the testbench and or1200_monitor
|
326 |
|
|
# whenever we run the simulation, so just that part is
|
327 |
|
|
# recompiled for every test, instead of the whole thing.
|
328 |
|
|
MGC_ORPSOC_LIB=orpsoc
|
329 |
|
|
MGC_ORPSOC_LIB_DIR=$(SIM_RUN_DIR)/$(MGC_ORPSOC_LIB)
|
330 |
|
|
|
331 |
|
|
# If VCD dump is desired, tell Modelsim not to optimise
|
332 |
|
|
# away everything.
|
333 |
|
|
ifeq ($(VCD), 1)
|
334 |
|
|
VOPT_ARGS=-voptargs="+acc=rnp"
|
335 |
|
|
endif
|
336 |
|
|
|
337 |
67 |
julius |
# RTL testbench toplevel name
|
338 |
|
|
RTL_TESTBENCH_TOP ?= orpsoc_testbench
|
339 |
|
|
|
340 |
55 |
julius |
# Simulation compile and run commands, depending on your
|
341 |
58 |
julius |
# simulator.
|
342 |
|
|
|
343 |
|
|
# Icarus Verilog
|
344 |
|
|
ifeq ($(SIMULATOR), $(ICARUS))
|
345 |
|
|
# Icarus Verilog Simulator compile and run commands
|
346 |
68 |
julius |
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(DASH_D_EVENT_SIM_FLAGS)
|
347 |
58 |
julius |
# Icarus Verilog run command
|
348 |
|
|
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out
|
349 |
|
|
endif
|
350 |
|
|
|
351 |
|
|
# Modelsim
|
352 |
|
|
ifeq ($(SIMULATOR), $(VSIM))
|
353 |
55 |
julius |
# Line to compile the orpsoc design into a modelsim library.
|
354 |
68 |
julius |
SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work $(MGC_ORPSOC_LIB) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(PLUS_DEFINE_EVENT_SIM_FLAGS); fi
|
355 |
55 |
julius |
# Final modelsim compile, done each time, pulling in or1200
|
356 |
|
|
# monitor and the new test_defines.v file:
|
357 |
68 |
julius |
VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) -y $(BENCH_VERILOG_DIR) +libext+.v +incdir+$(BENCH_TOP_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(PLUS_DEFINE_EVENT_SIM_FLAGS) $(BENCH_TOP_VERILOG_DIR)/$(RTL_TESTBENCH_TOP).v
|
358 |
55 |
julius |
# Simulation run command:
|
359 |
67 |
julius |
SIM_COMMANDRUN=$(VSIM_COMPILE_TB); $(VSIM) -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" $(RTL_TESTBENCH_TOP)
|
360 |
55 |
julius |
endif
|
361 |
|
|
|
362 |
58 |
julius |
# NCVerilog
|
363 |
|
|
ifeq ($(SIMULATOR), $(NCVERILOG))
|
364 |
|
|
SIM_COMMANDCOMPILE=echo
|
365 |
|
|
SIM_COMMANDRUN=$(NCVERILOG) -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) -Q -l $(SIM_RESULTS_DIR)/$$TEST-$(NCVERILOG)-out.log $(EVENT_SIM_FLAGS)
|
366 |
6 |
julius |
endif
|
367 |
|
|
|
368 |
58 |
julius |
# Names of memory files used in simulation
|
369 |
6 |
julius |
SIM_FLASH_MEM_FILE="flash.in"
|
370 |
|
|
FLASH_MEM_FILE_SUFFIX="-twobyte-sizefirst.hex"
|
371 |
|
|
SIM_SRAM_MEM_FILE="sram.vmem"
|
372 |
|
|
|
373 |
|
|
TESTS_PASSED=0
|
374 |
|
|
TESTS_PERFORMED=0;
|
375 |
|
|
|
376 |
|
|
################################################################################
|
377 |
58 |
julius |
# Event-driven simulator build rules
|
378 |
6 |
julius |
################################################################################
|
379 |
|
|
|
380 |
51 |
julius |
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
|
381 |
|
|
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
|
382 |
6 |
julius |
|
383 |
57 |
julius |
.PHONY: prepare-rtl
|
384 |
|
|
prepare-rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
385 |
6 |
julius |
|
386 |
55 |
julius |
$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)
|
387 |
57 |
julius |
$(Q)sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \
|
388 |
55 |
julius |
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
389 |
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
390 |
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
391 |
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d ; \
|
392 |
|
|
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
393 |
|
|
if [ ! -z $$VCD ]; \
|
394 |
|
|
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
395 |
58 |
julius |
if [ $(SIMULATOR) = $(NCVERILOG) ]; \
|
396 |
|
|
then echo "+access+r" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
397 |
|
|
fi; \
|
398 |
55 |
julius |
fi; \
|
399 |
|
|
if [ ! -z $$UART_PRINTF ]; \
|
400 |
|
|
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
401 |
58 |
julius |
fi; \
|
402 |
|
|
if [ $(SIMULATOR) = $(NCVERILOG) ]; \
|
403 |
|
|
then echo "+nocopyright" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
404 |
|
|
echo "+nowarn+MACRDF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \
|
405 |
55 |
julius |
fi
|
406 |
51 |
julius |
|
407 |
6 |
julius |
ifdef UART_PRINTF
|
408 |
44 |
julius |
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
|
409 |
6 |
julius |
endif
|
410 |
|
|
|
411 |
57 |
julius |
.PHONY: prepare-sw
|
412 |
|
|
prepare-sw:
|
413 |
|
|
$(Q)$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
|
414 |
|
|
$(Q)$(MAKE) -C $(SW_DIR)/utils all
|
415 |
6 |
julius |
|
416 |
|
|
# A rule with UART_PRINTF hard defined ... used by verilator make sw
|
417 |
57 |
julius |
prepare-sw-uart-printf:
|
418 |
|
|
$(Q)$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
|
419 |
|
|
$(Q)$(MAKE) -C $(SW_DIR)/utils all
|
420 |
6 |
julius |
|
421 |
57 |
julius |
prepare-dirs:
|
422 |
|
|
$(Q)if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
423 |
6 |
julius |
|
424 |
55 |
julius |
#
|
425 |
|
|
# Rough guide to how event driven simulation test loop works:
|
426 |
|
|
#
|
427 |
|
|
# 1. Compile software support programs.
|
428 |
|
|
# 2. Generate RTL compilation script file
|
429 |
|
|
# 3. For each test listed in $(TESTS), loop and
|
430 |
|
|
# a) Compile software
|
431 |
|
|
# b) Create appropriate image to be loaded into sim
|
432 |
|
|
# c) Create a verilog file to be included by top level
|
433 |
|
|
# d) Compile the RTL design
|
434 |
|
|
# e) Run the RTL design in the chosen simulator
|
435 |
|
|
# f) Check the output (files in ../results)
|
436 |
|
|
#
|
437 |
|
|
# Default setup is:
|
438 |
|
|
# * Event-driven simulation with Icarus Verilog
|
439 |
|
|
# * Internal SRAM memory, preloaded with application
|
440 |
|
|
# * Ethernet disabled
|
441 |
|
|
# * VCD generation disabled
|
442 |
|
|
# * printf() via UART disabled
|
443 |
|
|
# * Logging enabled
|
444 |
|
|
#
|
445 |
|
|
# Options:
|
446 |
|
|
# SIMULATOR=vsim
|
447 |
|
|
# Use Mentor Graphics Modelsim simulator
|
448 |
58 |
julius |
# SIMULATOR=ncverilog
|
449 |
|
|
# Use Cadence's NC-Verilog
|
450 |
55 |
julius |
# USE_SDRAM=1
|
451 |
|
|
# Enable use of SDRAM - changes boot sequence and takes
|
452 |
|
|
# a lot longer due to application being loaded out of
|
453 |
|
|
# external FLASH memory and into SDRAM before execution
|
454 |
|
|
# from the SDRAM.
|
455 |
|
|
# VCD=1
|
456 |
|
|
# Enable VCD generation. These files are output to
|
457 |
|
|
# ../results
|
458 |
|
|
# USE_ETHERNET=1
|
459 |
|
|
# Turns on ethernet core inclusion. There are currently
|
460 |
|
|
# some tests, but not included by default. Check the sw
|
461 |
|
|
# directory
|
462 |
|
|
# UART_PRINTF=1
|
463 |
|
|
# Make the software use the UART core to print out
|
464 |
|
|
# printf() calls.
|
465 |
|
|
# NO_SIM_LOGGING=1
|
466 |
|
|
# Turn off generation of logging files in the ../results
|
467 |
|
|
# directory.
|
468 |
|
|
#
|
469 |
57 |
julius |
rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare-sw prepare-rtl prepare-dirs
|
470 |
6 |
julius |
@echo
|
471 |
|
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
472 |
|
|
@echo
|
473 |
57 |
julius |
$(Q)for TEST in $(TESTS); do \
|
474 |
6 |
julius |
echo "################################################################################"; \
|
475 |
|
|
echo; \
|
476 |
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
477 |
|
|
echo "\t#### Compiling software ####"; echo; \
|
478 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
479 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS); \
|
480 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
481 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
482 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
483 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
484 |
55 |
julius |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \
|
485 |
|
|
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \
|
486 |
6 |
julius |
if [ ! -z $$VCD ]; \
|
487 |
55 |
julius |
then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \
|
488 |
6 |
julius |
fi; \
|
489 |
|
|
if [ ! -z $$UART_PRINTF ]; \
|
490 |
55 |
julius |
then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \
|
491 |
6 |
julius |
fi; \
|
492 |
44 |
julius |
if echo $$TEST | grep -q -i ^eth; then \
|
493 |
|
|
echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \
|
494 |
|
|
echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \
|
495 |
|
|
fi; \
|
496 |
43 |
julius |
if [ -z $$NO_SIM_LOGGING ]; then \
|
497 |
6 |
julius |
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \
|
498 |
|
|
fi; \
|
499 |
|
|
echo ; \
|
500 |
|
|
echo "\t#### Compiling RTL ####"; \
|
501 |
55 |
julius |
$(SIM_COMMANDCOMPILE); \
|
502 |
6 |
julius |
echo; \
|
503 |
|
|
echo "\t#### Beginning simulation ####"; \
|
504 |
55 |
julius |
time -p $(SIM_COMMANDRUN) ; \
|
505 |
6 |
julius |
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
506 |
|
|
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \
|
507 |
|
|
echo; echo "\t####"; \
|
508 |
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
509 |
|
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
510 |
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
511 |
|
|
fi; \
|
512 |
|
|
echo "\t####"; echo; \
|
513 |
|
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
514 |
|
|
done; \
|
515 |
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
516 |
|
|
|
517 |
|
|
################################################################################
|
518 |
40 |
julius |
# RTL simulation in Icarus with GDB stub via VPI for debugging
|
519 |
|
|
################################################################################
|
520 |
|
|
# This compiles a version of the system which starts up the dhrystone nocache
|
521 |
|
|
# test, and launches the simulator with a VPI module that provides a GDB stub
|
522 |
|
|
# allowing the OpenRISC compatible GDB to connect and debug the system.
|
523 |
|
|
# The launched test can be changed by defining VPI_TEST_SW on the make line
|
524 |
|
|
VPI_DIR=$(BENCH_VERILOG_DIR)/vpi
|
525 |
|
|
VPI_C_DIR=$(VPI_DIR)/c
|
526 |
|
|
VPI_VERILOG_DIR=$(VPI_DIR)/verilog
|
527 |
|
|
VPI_LIB_NAME=jp_vpi
|
528 |
|
|
ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)
|
529 |
|
|
VPI_TEST_SW ?= dhry-nocache-O2
|
530 |
|
|
|
531 |
57 |
julius |
prepare-vpi:
|
532 |
40 |
julius |
## Build the VPI library
|
533 |
|
|
$(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)
|
534 |
|
|
|
535 |
49 |
julius |
clean-vpi:
|
536 |
40 |
julius |
$(MAKE) -C $(VPI_C_DIR) clean
|
537 |
|
|
|
538 |
57 |
julius |
rtl-debug: prepare-sw-uart-printf prepare-rtl prepare-vpi prepare-dirs
|
539 |
40 |
julius |
## Prepare the software for the test
|
540 |
|
|
@echo "\t#### Compiling software ####"; echo; \
|
541 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \
|
542 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $(VPI_TEST_SW) $(TEST_SW_MAKE_OPTS); \
|
543 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
544 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
545 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
|
546 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)
|
547 |
|
|
## Generate the icarus script we'll compile with
|
548 |
57 |
julius |
$(Q)sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
|
549 |
40 |
julius |
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
550 |
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
551 |
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
552 |
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d
|
553 |
|
|
## Add a couple of extra defines to the icarus compile script
|
554 |
57 |
julius |
$(Q)echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
|
555 |
40 |
julius |
## The define that enables the VPI debug module
|
556 |
57 |
julius |
$(Q)echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
|
557 |
|
|
$(Q)if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi
|
558 |
40 |
julius |
## Unless NO_UART_PRINTF=1 we use printf via the UART
|
559 |
57 |
julius |
$(Q)if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi
|
560 |
|
|
$(Q)echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
|
561 |
|
|
$(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
|
562 |
|
|
$(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
|
563 |
40 |
julius |
@echo
|
564 |
|
|
@echo "\t#### Compiling RTL ####"
|
565 |
57 |
julius |
$(Q)rm -f $(SIM_RUN_DIR)/a.out
|
566 |
67 |
julius |
$(Q)$(ICARUS) -s$(RTL_TESTBENCH_TOP) -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
|
567 |
40 |
julius |
@echo
|
568 |
|
|
@echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
|
569 |
57 |
julius |
$(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
|
570 |
40 |
julius |
|
571 |
|
|
################################################################################
|
572 |
6 |
julius |
# Verilator model build rules
|
573 |
|
|
################################################################################
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
|
577 |
|
|
|
578 |
|
|
|
579 |
|
|
# List of System C models - use this list to link the sources into the Verilator
|
580 |
|
|
# build directory
|
581 |
51 |
julius |
SYSC_MODELS=OrpsocAccess MemoryLoad
|
582 |
6 |
julius |
|
583 |
49 |
julius |
ifdef VLT_DEBUG
|
584 |
|
|
VLT_DEBUG_COMPILE_FLAGS = -g
|
585 |
|
|
# Enabling the following generates a TON of debugging
|
586 |
|
|
# when running verilator. Not so helpful.
|
587 |
|
|
#VLT_DEBUG_OPTIONS = --debug --dump-tree
|
588 |
|
|
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
|
589 |
6 |
julius |
endif
|
590 |
|
|
|
591 |
49 |
julius |
# If set on the command line we build the cycle accurate model which will generate verilator-specific profiling information. This is useful for checking the efficiency of the model - not really useful for checking code or the function of the model.
|
592 |
|
|
ifdef VLT_ORPSOC_PROFILING
|
593 |
63 |
julius |
VLT_CPPFLAGS +=-pg
|
594 |
49 |
julius |
VLT_DEBUG_OPTIONS +=-profile-cfuncs
|
595 |
|
|
else
|
596 |
63 |
julius |
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
|
597 |
53 |
julius |
#VLT_CPPFLAGS=-Wall
|
598 |
49 |
julius |
endif
|
599 |
|
|
|
600 |
63 |
julius |
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model executable in GDB to check suspect behavior. This also removes optimisation.
|
601 |
|
|
ifdef VLT_IN_GDB
|
602 |
|
|
VLT_CPPFLAGS +=-g -O0
|
603 |
|
|
else
|
604 |
|
|
# The default optimisation flag applied to all of the cycle accurate model files
|
605 |
|
|
VLT_CPPFLAGS +=-O3
|
606 |
|
|
endif
|
607 |
|
|
|
608 |
49 |
julius |
ifdef VLT_DO_PROFILING
|
609 |
63 |
julius |
VLT_CPPFLAGS +=-ftest-coverage -fprofile-arcs -fprofile-generate
|
610 |
49 |
julius |
endif
|
611 |
|
|
|
612 |
|
|
# VCD Enabled by default when building, enable it at runtime
|
613 |
|
|
#ifdef VCD
|
614 |
|
|
VLT_FLAGS +=-trace
|
615 |
|
|
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
|
616 |
|
|
#endif
|
617 |
|
|
|
618 |
6 |
julius |
# Only need the trace target if we are tracing
|
619 |
49 |
julius |
#ifneq (,$(findstring -trace, $(VLT_FLAGS)))
|
620 |
6 |
julius |
VLT_TRACEOBJ = SpTraceVcdC
|
621 |
49 |
julius |
#endif
|
622 |
6 |
julius |
|
623 |
|
|
# This is the list of extra models we'll issue make commands for
|
624 |
|
|
# Included is the SystemPerl trace model
|
625 |
|
|
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
|
626 |
|
|
|
627 |
63 |
julius |
prepare-vlt: prepare-rtl vlt-model-links $(SIM_VLT_DIR)/Vorpsoc_top
|
628 |
54 |
julius |
@echo;echo "\tCycle-accurate model compiled successfully"
|
629 |
|
|
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo
|
630 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top -h
|
631 |
|
|
@echo;echo
|
632 |
6 |
julius |
|
633 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o
|
634 |
|
|
# Final linking of the simulation executable. Order of libraries here is important!
|
635 |
|
|
@echo; echo "\tGenerating simulation executable"; echo
|
636 |
49 |
julius |
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o Vorpsoc_top -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) OrpsocMain.o -lVorpsoc_top -lmodules -lsystemc
|
637 |
6 |
julius |
|
638 |
51 |
julius |
# Now compile the top level systemC "testbench" module from the systemC source path
|
639 |
|
|
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
640 |
6 |
julius |
@echo; echo "\tCompiling top level SystemC testbench"; echo
|
641 |
49 |
julius |
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
|
642 |
6 |
julius |
|
643 |
57 |
julius |
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt-modules-compile $(SIM_VLT_DIR)/verilated.o
|
644 |
6 |
julius |
# Now archive all of the libraries from verilator witht he other modules we might have
|
645 |
|
|
@echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
|
646 |
57 |
julius |
$(Q)cd $(SIM_VLT_DIR) && \
|
647 |
6 |
julius |
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
|
648 |
|
|
ar rcs libVorpsoc_top.a verilated.o; \
|
649 |
|
|
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
650 |
|
|
ar rcs libVorpsoc_top.a $$SYSCMODEL.o; \
|
651 |
|
|
done
|
652 |
|
|
|
653 |
|
|
$(SIM_VLT_DIR)/verilated.o:
|
654 |
|
|
@echo; echo "\tCompiling verilated.o"; echo
|
655 |
57 |
julius |
$(Q)cd $(SIM_VLT_DIR) && \
|
656 |
49 |
julius |
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
657 |
|
|
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
658 |
|
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
659 |
6 |
julius |
$(MAKE) -f Vorpsoc_top.mk verilated.o
|
660 |
|
|
|
661 |
57 |
julius |
.PHONY: vlt-modules-compile
|
662 |
|
|
vlt-modules-compile:
|
663 |
6 |
julius |
# Compile the module files
|
664 |
|
|
@echo; echo "\tCompiling SystemC models"
|
665 |
57 |
julius |
$(Q)cd $(SIM_VLT_DIR) && \
|
666 |
6 |
julius |
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
|
667 |
|
|
echo;echo "\t$$SYSCMODEL"; echo; \
|
668 |
49 |
julius |
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
|
669 |
51 |
julius |
export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
|
670 |
49 |
julius |
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
671 |
|
|
$(MAKE) -f Vorpsoc_top.mk $$SYSCMODEL.o; \
|
672 |
|
|
done
|
673 |
6 |
julius |
|
674 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
|
675 |
|
|
@echo; echo "\tCompiling main design"; echo
|
676 |
57 |
julius |
$(Q)cd $(SIM_VLT_DIR) && \
|
677 |
49 |
julius |
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
678 |
|
|
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
|
679 |
6 |
julius |
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
|
680 |
|
|
|
681 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top.mk: $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated $(SIM_VLT_DIR)/libmodules.a
|
682 |
|
|
# Now call verilator to generate the .mk files
|
683 |
|
|
@echo; echo "\tGenerating makefiles with Verilator"; echo
|
684 |
|
|
cd $(SIM_VLT_DIR) && \
|
685 |
49 |
julius |
verilator -language 1364-2001 -Wno-lint --top-module orpsoc_top $(VLT_DEBUG_OPTIONS) -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(VLT_COMMAND_FILE).generated
|
686 |
6 |
julius |
|
687 |
|
|
# SystemC modules library
|
688 |
|
|
$(SIM_VLT_DIR)/libmodules.a:
|
689 |
|
|
@echo; echo "\tCompiling SystemC modules"; echo
|
690 |
57 |
julius |
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
|
691 |
49 |
julius |
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
|
692 |
6 |
julius |
|
693 |
|
|
|
694 |
51 |
julius |
ALL_VLOG=$(shell find $(RTL_VERILOG_DIR) -name "*.v")
|
695 |
|
|
|
696 |
6 |
julius |
# Verilator command script
|
697 |
51 |
julius |
# Generate the compile script to give Verilator - make it sensitive to the RTL
|
698 |
|
|
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated: $(ALL_VLOG)
|
699 |
6 |
julius |
@echo; echo "\tGenerating verilator compile script"; echo
|
700 |
57 |
julius |
$(Q)sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
|
701 |
6 |
julius |
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
|
702 |
|
|
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
|
703 |
|
|
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
|
704 |
|
|
-e \\!^//.*\$$!d -e \\!^\$$!d;
|
705 |
|
|
|
706 |
63 |
julius |
.PHONY: vlt-model-links
|
707 |
|
|
vlt-model-links:
|
708 |
6 |
julius |
# Link all the required system C model files into the verilator work dir
|
709 |
|
|
@echo; echo "\tLinking SystemC model source to verilator build path"; echo
|
710 |
|
|
@if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
|
711 |
57 |
julius |
$(Q)cd $(SIM_VLT_DIR) && \
|
712 |
6 |
julius |
for SYSCMODEL in $(SYSC_MODELS); do \
|
713 |
|
|
if [ ! -e $$SYSCMODEL.cpp ]; then \
|
714 |
|
|
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
|
715 |
|
|
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h .; \
|
716 |
|
|
fi; \
|
717 |
|
|
done
|
718 |
|
|
|
719 |
|
|
|
720 |
|
|
################################################################################
|
721 |
|
|
# Verilator test loop
|
722 |
|
|
################################################################################
|
723 |
|
|
|
724 |
|
|
# Verilator defaults to internal memories
|
725 |
66 |
julius |
vlt-tests: prepare-sw prepare-rtl prepare-dirs prepare-vlt
|
726 |
6 |
julius |
@echo
|
727 |
|
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
728 |
|
|
@echo
|
729 |
57 |
julius |
$(Q)for TEST in $(TESTS); do \
|
730 |
6 |
julius |
echo "################################################################################"; \
|
731 |
|
|
echo; \
|
732 |
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
733 |
|
|
echo "\t#### Compiling software ####"; echo; \
|
734 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
735 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
736 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
737 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
738 |
|
|
echo "\t#### Beginning simulation ####"; \
|
739 |
|
|
time -p $(SIM_VLT_DIR)/Vorpsoc_top $$TEST; \
|
740 |
|
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
741 |
|
|
TEST_RESULT=1; \
|
742 |
|
|
echo; echo "\t####"; \
|
743 |
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
744 |
|
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
745 |
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
746 |
|
|
fi; \
|
747 |
|
|
echo "\t####"; echo; \
|
748 |
|
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
749 |
|
|
done; \
|
750 |
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
751 |
|
|
|
752 |
49 |
julius |
###############################################################################
|
753 |
|
|
# Verilator profiled module make
|
754 |
|
|
###############################################################################
|
755 |
57 |
julius |
# To run this, first run a "make prepare-vlt VLT_DO_PROFILING=1" then do a
|
756 |
|
|
# "make clean" and then a "make prepare-vlt_profiled"
|
757 |
49 |
julius |
# This new make target copies athe results of the profiling back to the right
|
758 |
|
|
# paths before we create everything again
|
759 |
|
|
###############################################################################
|
760 |
63 |
julius |
.PHONY: prepare-vlt-profiled
|
761 |
|
|
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda clean vlt-restore-profileoutput prepare-rtl vlt-model-links $(SIM_VLT_DIR)/Vorpsoc_top
|
762 |
6 |
julius |
|
763 |
63 |
julius |
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/Vorpsoc_top-for-profiling prepare-sw-uart-printf
|
764 |
|
|
$(MAKE) -C $(SW_DIR)/dhry dhry-nocache-O2 NUM_RUNS=200
|
765 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top -f $(SW_DIR)/dhry/dhry-nocache-O2.or32 -v -l sim.log --crash-monitor
|
766 |
|
|
|
767 |
|
|
.PHONY: $(SIM_VLT_DIR)/Vorpsoc_top-for-profiling
|
768 |
|
|
$(SIM_VLT_DIR)/Vorpsoc_top-for-profiling:
|
769 |
|
|
$(MAKE) prepare-vlt VLT_DO_PROFILING=1
|
770 |
|
|
|
771 |
|
|
.PHONY: vlt-restore-profileoutput
|
772 |
57 |
julius |
vlt-restore-profileoutput:
|
773 |
49 |
julius |
@echo;echo "\tRestoring profiling outputs"; echo
|
774 |
57 |
julius |
$(Q)mkdir -p ../vlt
|
775 |
|
|
$(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
|
776 |
|
|
$(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
|
777 |
6 |
julius |
|
778 |
|
|
################################################################################
|
779 |
|
|
# Architectural simulator test loop
|
780 |
|
|
################################################################################
|
781 |
|
|
|
782 |
|
|
# Verilator defaults to internal memories
|
783 |
66 |
julius |
sim-tests: prepare-sw
|
784 |
6 |
julius |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
|
785 |
|
|
@echo
|
786 |
|
|
@echo "Beginning loop that will complete the following tests: $(TESTS)"
|
787 |
|
|
@echo
|
788 |
57 |
julius |
$(Q)for TEST in $(TESTS); do \
|
789 |
6 |
julius |
echo "################################################################################"; \
|
790 |
|
|
echo; \
|
791 |
|
|
echo "\t#### Current test: $$TEST ####"; echo; \
|
792 |
|
|
echo "\t#### Compiling software ####"; echo; \
|
793 |
|
|
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $$TEST | cut -d "-" -f 1`; \
|
794 |
|
|
$(MAKE) -C $$CURRENT_TEST_SW_DIR $$TEST $(TEST_SW_MAKE_OPTS) UART_PRINTF=1; \
|
795 |
|
|
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \
|
796 |
|
|
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.or32 $(SIM_RUN_DIR)/.; \
|
797 |
|
|
echo;echo "\t#### Launching architectural simulator ####"; \
|
798 |
|
|
time -p $(ARCH_SIM_EXE) --nosrv -f $(SIM_BIN_DIR)/$(ARCH_SIM_CFG_FILE) $$TEST.or32 > $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log 2>&1; \
|
799 |
|
|
if [ $$? -gt 0 ]; then exit $$?; fi; \
|
800 |
|
|
if [ `tail -n 10 $(SIM_RESULTS_DIR)/$$TEST-or1ksim.log | grep -c $(SIM_SUCCESS_MESSAGE)` -gt 0 ]; then \
|
801 |
|
|
TEST_RESULT=1; \
|
802 |
|
|
fi; \
|
803 |
|
|
echo; echo "\t####"; \
|
804 |
|
|
if [ $$TEST_RESULT -gt 0 ]; then \
|
805 |
|
|
echo "\t#### Test $$TEST PASSED ####";TESTS_PASSED=`expr $$TESTS_PASSED + 1`;\
|
806 |
|
|
else echo "\t#### Test $$TEST FAILED ####";\
|
807 |
|
|
fi; \
|
808 |
|
|
echo "\t####"; echo; \
|
809 |
|
|
TESTS_PERFORMED=`expr $$TESTS_PERFORMED + 1`;\
|
810 |
|
|
unlink $(SIM_RUN_DIR)/$$TEST.or32; \
|
811 |
|
|
done; \
|
812 |
|
|
echo "Test results: "$$TESTS_PASSED" out of "$$TESTS_PERFORMED" tests passed"; echo
|
813 |
|
|
|
814 |
|
|
|
815 |
|
|
|
816 |
|
|
################################################################################
|
817 |
|
|
# Cleaning rules
|
818 |
|
|
################################################################################
|
819 |
|
|
|
820 |
69 |
julius |
dist-clean: clean
|
821 |
|
|
$(MAKE) -C $(SW_DIR)/utils clean
|
822 |
|
|
|
823 |
49 |
julius |
clean: clean-sw clean-sim clean-sysc clean-rtl clean-vpi
|
824 |
6 |
julius |
|
825 |
|
|
clean-sw:
|
826 |
69 |
julius |
@for SWDIR in `ls $(SW_DIR) | grep -v utils`; do \
|
827 |
44 |
julius |
echo $$SWDIR; \
|
828 |
|
|
$(MAKE) -C $(SW_DIR)/$$SWDIR clean; \
|
829 |
6 |
julius |
done
|
830 |
|
|
|
831 |
|
|
clean-sim:
|
832 |
49 |
julius |
#backup any profiling output files
|
833 |
51 |
julius |
@if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo;echo "\tBacking up verilator profiling output to /tmp"; echo; \
|
834 |
49 |
julius |
cp $(SIM_VLT_DIR)/*.gc* /tmp; \
|
835 |
|
|
cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi
|
836 |
55 |
julius |
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR) $(MGC_ORPSOC_LIB_DIR) $(SIM_RUN_DIR)/work $(SIM_RUN_DIR)/transcript
|
837 |
36 |
julius |
|
838 |
|
|
clean-sysc:
|
839 |
|
|
# Clean away dependency files generated by verilator
|
840 |
42 |
julius |
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make clean
|
841 |
36 |
julius |
|
842 |
|
|
clean-rtl:
|
843 |
|
|
# Clean away temporary verilog source files
|
844 |
44 |
julius |
rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
|
845 |
|
|
|