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[/] [openrisc/] [trunk/] [orpsocv2/] [sim/] [bin/] [Makefile] - Blame information for rev 484

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1 6 julius
######################################################################
2
####                                                              ####
3
####  ORPSoCv2 Testbenches Makefile                               ####
4
####                                                              ####
5
####  Description                                                 ####
6
####  ORPSoCv2 Testbenches Makefile, containing rules for         ####
7
####  configuring and running different tests on the current      ####
8
####  ORPSoC(v2) design.                                          ####
9
####                                                              ####
10
####  To do:                                                      ####
11
####                                                              ####
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####  Author(s):                                                  ####
13 360 julius
####      - Julius Baxter, julius@opencores.org                   ####
14 6 julius
####                                                              ####
15
####                                                              ####
16
######################################################################
17
####                                                              ####
18 348 julius
#### Copyright (C) 2009,2010 Authors and OPENCORES.ORG            ####
19 6 julius
####                                                              ####
20
#### This source file may be used and distributed without         ####
21
#### restriction provided that this copyright statement is not    ####
22
#### removed from the file and that any derivative work contains  ####
23
#### the original copyright notice and the associated disclaimer. ####
24
####                                                              ####
25
#### This source file is free software; you can redistribute it   ####
26
#### and/or modify it under the terms of the GNU Lesser General   ####
27
#### Public License as published by the Free Software Foundation; ####
28
#### either version 2.1 of the License, or (at your option) any   ####
29
#### later version.                                               ####
30
####                                                              ####
31
#### This source is distributed in the hope that it will be       ####
32
#### useful, but WITHOUT ANY WARRANTY; without even the implied   ####
33
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ####
34
#### PURPOSE.  See the GNU Lesser General Public License for more ####
35
#### details.                                                     ####
36
####                                                              ####
37
#### You should have received a copy of the GNU Lesser General    ####
38
#### Public License along with this source; if not, download it   ####
39
#### from http://www.opencores.org/lgpl.shtml                     ####
40
####                                                              ####
41
######################################################################
42
 
43 360 julius
# Name of the directory we're currently in
44
CUR_DIR=$(shell pwd)
45 6 julius
 
46 360 julius
# The root path of the whole project
47
PROJECT_ROOT ?=$(CUR_DIR)/../..
48 6 julius
 
49 362 julius
DESIGN_NAME=orpsoc
50
RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench
51
# Top level files for DUT and testbench
52
DUT_TOP=$(RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v
53
BENCH_TOP=$(BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v
54
 
55 360 julius
# Need this for individual test variables to not break
56
TEST ?= or1200-simple
57 6 julius
 
58 468 julius
TESTS ?= or1200-simple \
59
        or1200-basic \
60
        or1200-cbasic \
61
        or1200-dctest \
62
        or1200-float \
63
        or1200-mmu  \
64
        or1200-except \
65
        or1200-mac \
66
        or1200-ffl1 \
67
        or1200-linkregtest \
68
        or1200-tick \
69
        or1200-ticksyscall \
70
        uart-simple
71 6 julius
 
72 360 julius
# Gets turned into verilog `define
73
SIM_TYPE=RTL
74 6 julius
 
75 360 julius
# Paths to other important parts of this test suite
76
RTL_DIR = $(PROJECT_ROOT)/rtl
77
RTL_VERILOG_DIR = $(RTL_DIR)/verilog
78
RTL_VERILOG_INCLUDE_DIR = $(RTL_VERILOG_DIR)/include
79
#RTL_VHDL_DIR = $(RTL_DIR)/vhdl
80 6 julius
 
81 360 julius
PROJECT_VERILOG_DEFINES=$(RTL_VERILOG_INCLUDE_DIR)/$(DESIGN_NAME)-defines.v
82
# Detect technology to use for the simulation
83 468 julius
DESIGN_DEFINES=$(shell cat $(PROJECT_VERILOG_DEFINES) | \
84
        sed s://.*::g | sed s:\`:\#:g | sed 's:^[ ]*::' | \
85
        awk '{print};/^\#define/{printf "_%s=%s\n",$$2,$$2}' | \
86
        grep -v PERIOD | cpp -P | sed s:^_::g | sed s:=$$::g )
87 6 julius
 
88 360 julius
# Rule to look at what defines are being extracted from main file
89
print-defines:
90
        @echo echo; echo "\t### Design defines ###"; echo
91
        @echo "\tParsing "$(PROJECT_VERILOG_DEFINES)" and exporting:"
92
        @echo $(DESIGN_DEFINES)
93 6 julius
 
94 360 julius
# Simulation directories
95
SIM_DIR ?=$(PROJECT_ROOT)/sim
96 362 julius
SIM_VLT_DIR ?=$(SIM_DIR)/vlt
97 360 julius
RTL_SIM_DIR=$(SIM_DIR)
98
RTL_SIM_RUN_DIR=$(RTL_SIM_DIR)/run
99
RTL_SIM_BIN_DIR=$(RTL_SIM_DIR)/bin
100
RTL_SIM_SRC_DIR=$(RTL_SIM_DIR)/src
101
RTL_SIM_RESULTS_DIR=$(RTL_SIM_DIR)/out
102 6 julius
 
103 360 julius
# Testbench paths
104 6 julius
BENCH_DIR=$(PROJECT_ROOT)/bench
105
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog
106 403 julius
BENCH_VERILOG_INCLUDE_DIR=$(BENCH_VERILOG_DIR)/include
107 360 julius
#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl
108 362 julius
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc
109
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src
110
BENCH_SYSC_INCLUDE_DIR=$(BENCH_SYSC_DIR)/include
111 360 julius
 
112 362 julius
 
113 360 julius
# System software dir
114 6 julius
SW_DIR=$(PROJECT_ROOT)/sw
115 360 julius
# BootROM code, which generates a verilog array select values
116
BOOTROM_FILE=bootrom.v
117
BOOTROM_SW_DIR=$(SW_DIR)/bootrom
118
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE))
119
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE)
120
$(BOOTROM_VERILOG): $(BOOTROM_SRC)
121
        $(Q)echo; echo "\t### Generating bootup ROM ###"; echo
122
        $(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE)
123 6 julius
 
124 360 julius
# Suffix of file to check after each test for the string
125
TEST_OUT_FILE_SUFFIX=-general.log
126
TEST_OK_STRING=8000000d
127 6 julius
 
128 360 julius
# Dynamically generated verilog file defining configuration for various things
129
TEST_DEFINES_VLG=test-defines.v
130 57 julius
# Set V=1 when calling make to enable verbose output
131
# mainly for debugging purposes.
132
ifeq ($(V), 1)
133
Q=
134 360 julius
QUIET=
135 57 julius
else
136 360 julius
Q ?=@
137
QUIET=-quiet
138 57 julius
endif
139
 
140 360 julius
# Modelsim variables
141
MGC_VSIM=vsim
142
MGC_VLOG_COMP=vlog
143
MGC_VHDL_COMP=vcom
144
MODELSIM=modelsim
145 6 julius
 
146 360 julius
# Icarus variables
147
ICARUS_COMPILE=iverilog
148
ICARUS_RUN=vvp
149
ICARUS_SCRIPT=icarus.scr
150
ICARUS_SIM_EXE=vlogsim.elf
151
ICARUS=icarus
152 58 julius
 
153 360 julius
#Default simulator is Icarus Verilog
154
# Set SIMULATOR=modelsim to use Modelsim
155
# Set SIMULATOR=ncverilog to use Cadence's NC-Verilog - TODO
156
# Set SIMULATOR=icarus to use Icarus Verilog (Default)
157 68 julius
 
158 58 julius
SIMULATOR ?= $(ICARUS)
159
 
160 360 julius
# VPI debugging interface variables
161
VPI_SRC_C_DIR=$(BENCH_VERILOG_DIR)/vpi/c
162 397 julius
VPI_SRC_VERILOG_DIR=$(BENCH_VERILOG_DIR)/vpi/verilog
163 360 julius
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch])
164 58 julius
 
165 360 julius
# Modelsim VPI compile variables
166
MODELTECH_VPILIB=msim_jp_vpi.sl
167
# Icarus VPI compile target
168
ICARUS_VPILIB=jp_vpi
169 58 julius
 
170 360 julius
#
171
# Modelsim-specific settings
172
#
173
VOPT_ARGS=$(QUIET) -suppress 2241
174 55 julius
# If VCD dump is desired, tell Modelsim not to optimise
175
# away everything.
176
ifeq ($(VCD), 1)
177 484 julius
# If certain versions of modelsim don't have the vopt executable, define
178
# MGC_NO_VOPT=1 when running.
179
ifeq ($(MGC_NO_VOPT), 1)
180
MGC_VSIM_ARGS +=-voptargs="+acc=rnp"
181
MGC_VOPT_CMD=echo
182
MGC_VSIM_TGT=orpsoc_testbench
183
else
184 360 julius
VOPT_ARGS=+acc=rnpqv
185 484 julius
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
186
MGC_VSIM_TGT=tb
187 55 julius
endif
188 484 julius
 
189
else
190
 
191
ifeq ($(MGC_NO_VOPT), 1)
192
MGC_VSIM_ARGS += -vopt
193
MGC_VOPT_CMD=echo
194
MGC_VSIM_TGT=orpsoc_testbench
195
else
196
VOPT_ARGS=+acc=rnpqv
197
MGC_VOPT_CMD= vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb
198
MGC_VSIM_TGT=tb
199
endif
200
 
201
 
202
endif
203 360 julius
# VSIM commands
204
# Suppressed warnings - 3009: Failed to open $readmemh() file
205 475 julius
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale
206
#                       directive in effect, but previous modules do.
207
# Suppressed warnings - 8598: Non-positive replication multiplier inside
208
#                       concat. Replication will be ignored
209 484 julius
MGC_VSIM_ARGS +=  -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) \
210 475 julius
                -do "set StdArithNoWarnings 1; run -all; exit"
211 397 julius
# Options required when VPI option used
212 360 julius
ifeq ($(VPI), 1)
213 397 julius
MGC_VPI_LIB=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
214
MGC_VSIM_ARGS += -pli $(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB)
215
 
216
ICARUS_VPI_LIB=$(VPI_SRC_C_DIR)/$(ICARUS_VPILIB)
217
ICARUS_VPI_ARGS=-M$(VPI_SRC_C_DIR) -m$(ICARUS_VPILIB)
218 58 julius
endif
219 397 julius
# Rule to make the VPI library for Modelsim
220
$(MGC_VPI_LIB): $(VPI_SRCS)
221 360 julius
        $(MAKE) -C $(VPI_SRC_C_DIR) $(MODELTECH_VPILIB)
222 58 julius
 
223 397 julius
# Rule to make VPI library for Icarus Verilog
224
$(ICARUS_VPI_LIB): $(VPI_SRCS)
225 360 julius
        $(MAKE) -C $(VPI_SRC_C_DIR) $(ICARUS_VPILIB)
226 77 rherveille
 
227 397 julius
# Manually add the VPI bench verilog path
228
BENCH_VERILOG_SRC_SUBDIRS += $(VPI_SRC_VERILOG_DIR)
229
 
230 360 julius
#
231
# Verilog DUT source variables
232
#
233
# A list of paths under rtl/verilog we wish to exclude for module searching
234
VERILOG_MODULES_EXCLUDE=  include components
235 475 julius
VERILOG_MODULES_EXCLUDE_LIST_E=$(shell for exclude in \
236
                $(VERILOG_MODULES_EXCLUDE); do echo "-e $$exclude"; done)
237
RTL_VERILOG_MODULES=$(shell ls $(RTL_VERILOG_DIR) | grep -v \
238
                        $(VERILOG_MODULES_EXCLUDE_LIST_E) )
239 360 julius
# Specific files to exclude, currently none.
240
#VERILOG_EXCLUDE=
241 475 julius
#VERILOG_EXCLUDE_LIST_E=$(shell for exclude in $(VERILOG_EXCLUDE); \
242
                do echo "-e $$exclude"; done)
243 360 julius
# List of verilog source files, minus excluded files
244 475 julius
#RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
245
        if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
246
                ls $(RTL_VERILOG_DIR)/$$module/*.v | grep -v \
247
                        $(VERILOG_EXCLUDE_LIST_E); \
248
        fi; done)
249 360 julius
# List of verilog source files, ignoring excludes
250 475 julius
RTL_VERILOG_SRC=$(shell for module in $(RTL_VERILOG_MODULES); do \
251
        if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
252
                ls $(RTL_VERILOG_DIR)/$$module/*.v; \
253
        fi; done)
254 6 julius
 
255 360 julius
# List of verilog includes
256
RTL_VERILOG_INCLUDES=$(shell ls $(RTL_VERILOG_INCLUDE_DIR)/*.*)
257 6 julius
 
258 360 julius
print-verilog-src:
259
        @echo echo; echo "\t### Verilog source ###"; echo
260
        @echo $(RTL_VERILOG_SRC)
261 51 julius
 
262 360 julius
# Rules to make RTL we might need
263
# Expects modules, if they need making, to have their top verilog file to
264
# correspond to their module name, and the directory should have a make file
265
# and rule which works for this command.
266
# Add name of module to this list, currently only does verilog ones.
267
# Rule 'rtl' is called just before generating DUT modelsim compilation script
268
RTL_TO_CHECK=
269
rtl:
270
        $(Q)for module in $(RTL_TO_CHECK); do \
271
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module $$module.v; \
272
        done
273 6 julius
 
274 55 julius
#
275 360 julius
# VHDL DUT source variables
276 55 julius
#
277 360 julius
# VHDL modules
278
#RTL_VHDL_MODULES=$(shell ls $(RTL_VHDL_DIR))
279
# VHDL sources
280 475 julius
#RTL_VHDL_SRC=$(shell for module in $(RTL_VHDL_MODULES); do \
281
        if [ -d $(RTL_VHDL_DIR)/$$module ]; then \
282
                ls $(RTL_VHDL_DIR)/$$module/*.vhd; \
283
        fi; done)
284 360 julius
#print-vhdl-src:
285
#       @echo echo; echo "\t### VHDL modules and source ###"; echo
286
#       @echo "modules: "; echo $(RTL_VHDL_MODULES); echo
287
#       @echo "source: "$(RTL_VHDL_SRC)
288 6 julius
 
289 40 julius
 
290 360 julius
# Testbench verilog source
291 475 julius
BENCH_VERILOG_SRC=$(shell ls $(BENCH_VERILOG_DIR)/*.v | grep -v \
292
        $(DESIGN_NAME)_testbench )
293 40 julius
 
294 362 julius
print-bench-src:
295
        $(Q)echo "\tBench verilog source"; \
296
        echo $(BENCH_VERILOG_SRC)
297
 
298 360 julius
# Testbench source subdirectory detection
299 475 julius
BENCH_VERILOG_SRC_SUBDIRS +=$(shell for file in `ls $(BENCH_VERILOG_DIR)`; do \
300
        if [ -d $(BENCH_VERILOG_DIR)/$$file ]; then \
301
                echo $(BENCH_VERILOG_DIR)/$$file; \
302
        fi; done)
303 40 julius
 
304 360 julius
# Compile script generation rules:
305 40 julius
 
306 475 julius
modelsim_dut.scr: rtl $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
307
                        $(BOOTROM_VERILOG)
308 360 julius
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
309
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
310
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
311 403 julius
        $(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@;
312 360 julius
        $(Q)echo "+libext+.v" >> $@;
313 475 julius
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
314
                if [ -d $(RTL_VERILOG_DIR)/$$module ]; then \
315
                        echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
316
                fi; done
317 360 julius
        $(Q)echo >> $@
318 6 julius
 
319 360 julius
modelsim_bench.scr: $(BENCH_VERILOG_SRC)
320
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) > $@;
321 475 julius
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
322
                echo "+incdir+"$$path >> $@; \
323
        done
324
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
325
                echo "-y "$$path >> $@; \
326
        done
327 360 julius
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) >> $@;
328
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
329
        $(Q)echo "+libext+.v" >> $@;
330
        $(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
331
        $(Q)for vsrc in $(BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
332
        $(Q)echo >> $@
333 6 julius
 
334 360 julius
# Compile DUT into "work" library
335
work: modelsim_dut.scr #$(RTL_VHDL_SRC)
336
        $(Q)if [ ! -e $@ ]; then vlib $@; fi
337
#       $(Q)echo; echo "\t### Compiling VHDL design library ###"; echo
338
#       $(Q)vcom -93 $(QUIET) $(RTL_VHDL_SRC)
339
        $(Q)echo; echo "\t### Compiling Verilog design library ###"; echo
340
        $(Q)vlog $(QUIET) -f $< $(DUT_TOP)
341 6 julius
 
342 360 julius
# Single compile rule
343
.PHONY : $(MODELSIM)
344 397 julius
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(MGC_VPI_LIB) work
345 360 julius
        $(Q)echo; echo "\t### Compiling testbench ###"; echo
346 362 julius
        $(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $<
347 484 julius
        $(Q)$(MGC_VOPT_CMD)
348 360 julius
        $(Q)echo; echo "\t### Launching simulation ###"; echo
349 484 julius
        $(Q)vsim $(VOPT_ARGS) $(MGC_VSIM_ARGS) $(MGC_VSIM_TGT)
350 6 julius
 
351 360 julius
#
352
# Icarus Verilog simulator build and run rules
353
#
354
.PHONY: $(ICARUS_SCRIPT)
355 475 julius
$(ICARUS_SCRIPT):  $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
356
                $(BOOTROM_VERILOG) $(BENCH_VERILOG_SRC)
357 360 julius
        $(Q)echo "# Icarus Verilog simulation script" > $@
358
        $(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
359
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
360
        $(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@;
361
        $(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@;
362
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
363 475 julius
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
364
                echo "+incdir+"$$path >> $@; \
365
        done
366
        $(Q)for path in $(BENCH_VERILOG_SRC_SUBDIRS); do \
367
                echo "-y "$$path >> $@; \
368
        done
369
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
370
                echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
371
        done
372 360 julius
        $(Q)echo "-y" $(RTL_SIM_SRC_DIR) >> $@;
373 362 julius
        $(Q)echo "-y" $(BENCH_VERILOG_DIR) >> $@;
374
        $(Q)echo $(BENCH_TOP) >> $@;
375 360 julius
        $(Q) echo >> $@
376 6 julius
 
377 360 julius
# Icarus design compilation rule
378
$(ICARUS_SIM_EXE): $(ICARUS_SCRIPT) $(TEST_DEFINES_VLG)
379
        $(Q)echo; echo "\t### Compiling ###"; echo
380
        $(Q) $(ICARUS_COMPILE) -s$(RTL_TESTBENCH_TOP) -c $< -o $@
381 49 julius
 
382 360 julius
# Icarus simulation run rule
383
$(ICARUS): $(ICARUS_SIM_EXE) $(ICARUS_VPI_LIB)
384
        $(Q)echo; echo "\t### Launching simulation ###"; echo
385
        $(Q) $(ICARUS_RUN) $(ICARUS_VPI_ARGS) -l ../out/$(ICARUS_RUN).log $<
386 63 julius
 
387 49 julius
 
388
 
389 360 julius
.PHONY: rtl-test
390 425 julius
rtl-test: clean-sim-test-sw sw-vmem clean-test-defines $(TEST_DEFINES_VLG) \
391 360 julius
        $(SIMULATOR)
392 6 julius
 
393 360 julius
# Run an RTL test followed by checking of generated results
394
rtl-test-with-check: rtl-test
395
        $(Q)$(MAKE) check-test-log; \
396
        if [ $$? -ne 0 ]; then \
397
                echo; echo "\t### "$(TEST)" test FAIL ###"; echo; \
398
        else \
399
                echo; echo "\t### "$(TEST)" test OK ###"; echo; \
400
        fi
401 6 julius
 
402 360 julius
# Do check, don't print anything out
403
rtl-test-with-check-no-print: rtl-test check-test-log
404 6 julius
 
405 360 julius
# Main RTL test loop
406
rtl-tests:
407
        $(Q)for test in $(TESTS); do \
408
                export TEST=$$test; \
409
                $(MAKE) rtl-test-with-check-no-print; \
410
                if [ $$? -ne 0 ]; then break; fi; \
411
                echo; echo "\t### $$test test OK ###"; echo; \
412 6 julius
        done
413
 
414
 
415 360 julius
.PHONY: check-test-log
416
check-test-log:
417
        $(Q)echo "#!/bin/bash" > $@
418
        $(Q)echo "function check-test-log { if [ \`grep -c -i "$(TEST_OK_STRING)" "$(RTL_SIM_RESULTS_DIR)"/"$(TEST)$(TEST_OUT_FILE_SUFFIX)"\` -gt 0 ]; then return 0; else return 1; fi; }" >> $@
419
        $(Q)echo "check-test-log" >> $@
420
        $(Q)chmod +x $@
421
        $(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo;
422
        $(Q)./$@
423 6 julius
 
424 403 julius
# Include the test-defines.v generation rule
425
include ../bin/definesgen.inc
426 6 julius
 
427 403 julius
#
428
# Software make rules (called recursively)
429
#
430 51 julius
 
431 403 julius
# Path for the current test
432 393 julius
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
433 6 julius
 
434 468 julius
# This file name corresponds to the VMEM file the RAM models will attempt to
435
# load via $readmemh().
436
SIM_VMEM_IMAGE ?=sram.vmem
437 6 julius
 
438 468 julius
ifeq ($(USER_ELF),)
439
ELF_FILE=$(TEST_SW_DIR)/$(TEST).elf
440
else
441
ELF_FILE=$(USER_ELF)
442
ELF_FILE_NOTDIR=$(notdir $(USER_ELF))
443
ELF_FILE_NOTDIR_BASENAME=$(basename $(ELF_FILE_NOTDIR))
444
endif
445 6 julius
 
446 468 julius
# Rules allowing user to specify a pre-existing VMEM file to load into the
447
# simulation, instead of compiling a test.
448
ifeq ($(USER_VMEM),)
449
VMEM_FILE=$(TEST_SW_DIR)/$(TEST).vmem
450
.PHONY: $(VMEM_FILE)
451
 
452
 
453
# If USER_ELF was specified, then we need a slightly different way of
454
# generating the VMEM file from it than a usual test
455
ifeq ($(USER_ELF),)
456
$(SIM_VMEM_IMAGE): $(VMEM_FILE)
457 360 julius
        $(Q)if [ -L $@ ]; then unlink $@; fi
458 468 julius
        $(Q)if [ -e $@ ]; then rm $@; fi
459 360 julius
        $(Q)ln -s $< $@
460 468 julius
else
461
$(SIM_VMEM_IMAGE): $(USER_ELF)
462
        $(Q)$(MAKE) -C $(SW_DIR)/lib \
463
        USER_ELF_BIN=`pwd`/$(ELF_FILE_NOTDIR_BASENAME).bin \
464
        USER_ELF_VMEM=`pwd`/$(ELF_FILE_NOTDIR_BASENAME).vmem \
465
        gen-user-elf-vmem
466
        $(Q)cp -v $(ELF_FILE_NOTDIR_BASENAME).vmem $@
467 6 julius
 
468 468 julius
TEST=$(ELF_FILE_NOTDIR_BASENAME)
469
endif
470
 
471
else
472
VMEM_FILE=$(USER_VMEM)
473
USER_VMEM_NOTDIR=$(notdir $(USER_VMEM))
474
TEST=$(basename $(USER_VMEM_NOTDIR))
475
 
476
$(SIM_VMEM_IMAGE): $(VMEM_FILE)
477
        cp -v $< $@
478
 
479
endif
480
 
481
 
482
 
483
 
484
.PHONY : sw-vmem sw-elf
485
sw-vmem: $(SIM_VMEM_IMAGE)
486
 
487 360 julius
$(TEST_SW_DIR)/$(TEST).vmem:
488
        $(Q) echo; echo "\t### Compiling software ###"; echo;
489
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
490 63 julius
 
491 425 julius
# Compile ELF and copy it here
492 468 julius
sw-elf: $(ELF_FILE)
493 425 julius
        $(Q)cp -v $< .
494
 
495
$(TEST_SW_DIR)/$(TEST).elf:
496
        $(Q) echo; echo "\t### Compiling software ###"; echo;
497
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).elf
498
 
499
 
500 397 julius
# Rule to force generation of the processed orpsoc-defines.h file
501
processed-verilog-headers-in-c-for-vlt:
502
        $(Q)$(MAKE) -C $(SW_DIR)/lib processed-verilog-headers
503
# Now copy the file into the Verilated model build path
504
        $(Q)cp $(SW_DIR)/lib/include/orpsoc-defines.h $(SIM_VLT_DIR)
505
 
506 435 julius
# Create test software disassembly
507
 
508
sw-dis: $(TEST_SW_DIR)/$(TEST).dis
509
        $(Q)cp -v $< .
510
 
511
$(TEST_SW_DIR)/$(TEST).dis:
512
        $(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).dis
513
 
514
 
515 360 julius
#
516
# Cleaning rules
517
#
518 362 julius
clean: clean-sim clean-sim-test-sw clean-bootrom clean-vlt clean-out clean-sw
519 63 julius
 
520 360 julius
clean-sim:
521
        $(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo;
522
        $(Q)rm -rf *.* lib_* work transcript check-test-log
523 468 julius
        $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then \
524
                $(MAKE) -C $(VPI_SRC_C_DIR) clean; \
525
        fi
526 6 julius
 
527 360 julius
clean-bootrom:
528
        $(MAKE) -C $(BOOTROM_SW_DIR) clean
529 6 julius
 
530 360 julius
clean-out:
531
        $(Q)rm -rf $(RTL_SIM_RESULTS_DIR)/*.*
532 6 julius
 
533 363 julius
# Clean away verilator build path and objects in SystemC path
534 362 julius
clean-vlt:
535
        $(Q)rm -rf $(SIM_VLT_DIR)
536 475 julius
        $(Q)$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f \
537
                $(BENCH_SYSC_SRC_DIR)/Modules.make clean
538 362 julius
 
539 360 julius
clean-test-defines:
540
        $(Q)rm -f $(TEST_DEFINES_VLG)
541 6 julius
 
542 360 julius
clean-sim-test-sw:
543 468 julius
        $(Q)if [ -L $(SIM_VMEM_IMAGE) ]; then unlink $(SIM_VMEM_IMAGE); fi
544 6 julius
 
545
clean-sw:
546 360 julius
        $(Q) echo; echo "\t### Cleaning simulation sw directories ###"; echo;
547 449 julius
        $(Q) $(MAKE) -C $(SW_DIR)/lib distclean
548 6 julius
 
549 36 julius
clean-rtl:
550 360 julius
        $(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
551
        for module in $(RTL_TO_CHECK); do \
552
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module clean; \
553
        done
554 44 julius
 
555 360 julius
# Removes any checked out RTL
556
distclean: clean
557
        $(Q) echo; echo "\t### Cleaning generated verilog RTL ###"; echo;
558
        $(Q)for module in $(RTL_TO_CHECK); do \
559
                $(MAKE) -C $(RTL_VERILOG_DIR)/$$module distclean; \
560
        done
561 362 julius
 
562
################################################################################
563
# Verilator model build rules
564
################################################################################
565
 
566
VLT_EXE=Vorpsoc_top
567
VLT_SCRIPT=verilator.scr
568
 
569
# Script for Verilator
570 475 julius
$(SIM_VLT_DIR)/$(VLT_SCRIPT): $(RTL_VERILOG_SRC) $(RTL_VERILOG_INCLUDES) \
571
                                $(BOOTROM_VERILOG)
572 362 julius
        $(Q)echo "\tGenerating Verilator script"
573
        $(Q)echo "# Verilator sources script" > $@
574
        $(Q)echo "# Auto generated. Any alterations will be written over!" >> $@
575
        $(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@;
576
        $(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@;
577
        $(Q)echo "+incdir+"$(SIM_RUN_DIR) >> $@;
578 475 julius
        $(Q)for module in $(RTL_VERILOG_MODULES); do \
579
                echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; \
580
        done
581 362 julius
        $(Q)echo $(DUT_TOP) >> $@;
582
        $(Q) echo >> $@
583
 
584
 
585
SYSC_LIB_ARCH_DIR=$(shell ls $$SYSTEMC | grep "lib-")
586
 
587
 
588
# List of System C models - use this list to link the sources into the Verilator
589
# build directory
590
SYSC_MODELS=OrpsocAccess MemoryLoad
591
 
592 363 julius
ifdef VLT_LINT
593
VLT_FLAGS +=--lint-only
594
endif
595
 
596 362 julius
ifdef VLT_DEBUG
597
VLT_DEBUG_COMPILE_FLAGS = -g
598
# Enabling the following generates a TON of debugging
599
# when running verilator. Not so helpful.
600 363 julius
#VLT_FLAGS = --debug --dump-tree
601 362 julius
VLT_SYSC_DEBUG_DEFINE = VLT_DEBUG=1
602
endif
603
 
604 363 julius
# This will build a verilator model that will generate profiling information
605
# suitable for gprof
606
# Run it through gprof after exection with: gprof Vorpsoc_top > gprof.out
607
# then run this through the Verilator tool with:
608
# verilator_profcfunc gprof.out > vprof.out
609
ifdef VLT_EXECUTION_PROFILE_BUILD
610
VLT_CPPFLAGS +=-g -pg
611
# Maybe add these to VLT_CPPFLAGS: -ftest-coverage -fprofile-arcs
612
VLT_FLAGS +=-profile-cfuncs
613
endif
614
 
615
# If set on the command line we build the cycle accurate model which will
616
# generate verilator-specific profiling information. This is useful for
617
# checking the efficiency of the model - not really useful for checking code
618
# or the function of the model.
619
ifdef VLT_DO_PERFORMANCE_PROFILE_BUILD
620 475 julius
VLT_CPPFLAGS += -fprofile-generate -fbranch-probabilities -fvpt \
621
                -funroll-loops -fpeel-loops -ftracer
622 362 julius
else
623
VLT_CPPFLAGS +=-fprofile-use -Wcoverage-mismatch
624
endif
625
 
626 363 julius
# Set VLT_IN_GDB=1 when making if going to run the cycle accurate model
627
# executable in GDB.
628 362 julius
ifdef VLT_IN_GDB
629
VLT_CPPFLAGS +=-g -O0
630
else
631
# The default optimisation flag applied to all of the cycle accurate model files
632
VLT_CPPFLAGS +=-O3
633
endif
634
 
635
# VCD Enabled by default when building, enable it at runtime
636
VLT_FLAGS +=-trace
637
TRACE_FLAGS=-DVM_TRACE=1 -I${SYSTEMPERL}/src
638
 
639 363 julius
# Verilator tuning
640
# Inlining:
641
VLT_FLAGS +=--inline-mult 1
642
# Optimisation option for Verilator scripts
643
VLT_FLAGS +=-O3
644 475 julius
# X-assign - at reset, all signals are set to random values, helps find
645
# reset bugs
646 363 julius
VLT_FLAGS +=-x-assign unique
647
 
648 362 julius
VLT_TRACEOBJ = verilated_vcd_c
649
 
650 363 julius
 
651 362 julius
# This is the list of extra models we'll issue make commands for
652
# Included is the SystemPerl trace model
653
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
654
 
655
# List of sources for rule sensitivity
656
SYSC_MODEL_SOURCES=$(shell ls $(BENCH_SYSC_SRC_DIR)/*.cpp)
657
SYSC_MODEL_SOURCES +=$(shell ls $(BENCH_SYSC_INCLUDE_DIR)/*.h)
658
 
659 475 julius
VLT_MODULES_OBJS=$(shell for mod in $(SYSC_MODELS_BUILD); do \
660
                echo $(SIM_VLT_DIR)/$$mod.o; \
661
        done)
662 362 julius
 
663 475 julius
VLT_MODEL_LINKS=$(shell for SYSCMODEL in $(SYSC_MODELS); do \
664
                echo $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
665
        done)
666 362 julius
 
667
# Make Verilator build path if it doesn't exist
668
$(SIM_VLT_DIR):
669
        mkdir -p $@
670
 
671
# Dummy files the RTL requires: timescale.v
672
DUMMY_FILES_FOR_VLT=$(SIM_VLT_DIR)/timescale.v
673
$(DUMMY_FILES_FOR_VLT):
674
        $(Q)for file in $@; do if [ ! -e $$file ]; then touch $$file; fi; done
675
 
676 397 julius
build-vlt: rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
677
        processed-verilog-headers-in-c-for-vlt  $(SIM_VLT_DIR)/$(VLT_EXE)
678 362 julius
 
679
# Main Cycle-accurate build rule
680
prepare-vlt: build-vlt
681
        @echo;echo "\tCycle-accurate model compiled successfully"
682
        @echo;echo "\tRun the executable with the -h option for usage instructions:";echo
683
        $(SIM_VLT_DIR)/$(VLT_EXE) -h
684
        @echo;echo
685
 
686 475 julius
$(SIM_VLT_DIR)/$(VLT_EXE): $(SIM_VLT_DIR)/lib$(VLT_EXE).a \
687
                                $(SIM_VLT_DIR)/OrpsocMain.o
688
# Final linking of the simulation executable. Order of libraries here is
689
# important!
690 362 julius
        $(Q)echo; echo "\tGenerating simulation executable"; echo
691 475 julius
        $(Q)cd $(SIM_VLT_DIR) && \
692
                g++ $(VLT_DEBUG_COMPILE_FLAGS) \
693
                $(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
694
                -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -o $(VLT_EXE) \
695
                -L. -L$(BENCH_SYSC_SRC_DIR) -L$(SYSTEMC)/$(SYSC_LIB_ARCH_DIR) \
696
                OrpsocMain.o -l$(VLT_EXE) -lmodules -lsystemc
697 362 julius
 
698 475 julius
# Now compile the top level systemC "testbench" module from the systemC source
699
# path
700 362 julius
$(SIM_VLT_DIR)/OrpsocMain.o: $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
701
        @echo; echo "\tCompiling top level SystemC testbench"; echo
702 475 julius
        cd $(SIM_VLT_DIR) && \
703
        g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) \
704
        -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) \
705
        -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c \
706
        $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
707 362 julius
 
708 475 julius
$(SIM_VLT_DIR)/lib$(VLT_EXE).a: $(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a \
709
                $(VLT_MODULES_OBJS) $(SIM_VLT_DIR)/verilated.o
710
# Now archive all of the libraries from verilator witht he other modules we
711
# might have
712 362 julius
        @echo; echo "\tArchiving libraries into lib"$(VLT_EXE)".a"; echo
713
        $(Q)cd $(SIM_VLT_DIR) && \
714
        cp $(VLT_EXE)__ALL.a lib$(VLT_EXE).a && \
715
        ar rcs lib$(VLT_EXE).a verilated.o; \
716
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
717
                ar rcs lib$(VLT_EXE).a $$SYSCMODEL.o; \
718
        done
719
 
720
$(SIM_VLT_DIR)/verilated.o: $(SYSC_MODEL_SOURCES)
721
        @echo; echo "\tCompiling verilated.o"; echo
722
        $(Q)cd $(SIM_VLT_DIR) && \
723
        export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
724
        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
725
        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
726
        $(MAKE) -f $(VLT_EXE).mk verilated.o
727
 
728
print-sysmod-objs:
729
        $(Q)echo $(VLT_MODULES_OBJS):
730
 
731
$(VLT_MODULES_OBJS):
732
# Compile the module files
733
        @echo; echo "\tCompiling SystemC models"
734
        $(Q)cd $(SIM_VLT_DIR) && \
735
        for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
736
                echo;echo "\t$$SYSCMODEL"; echo; \
737
                export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
738
                export USER_CPPFLAGS="$(VLT_CPPFLAGS) -I$(BENCH_SYSC_INCLUDE_DIR)"; \
739
                export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
740
                 $(MAKE) -f $(VLT_EXE).mk $$SYSCMODEL.o; \
741
        done
742
 
743 475 julius
$(SIM_VLT_DIR)/$(VLT_EXE)__ALL.a: $(SIM_VLT_DIR)/$(VLT_EXE).mk \
744
                $(SYSC_MODEL_SOURCES)
745 362 julius
        @echo; echo "\tCompiling main design"; echo
746
        $(Q)cd $(SIM_VLT_DIR) && \
747
        export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
748
        export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
749
        $(MAKE) -f $(VLT_EXE).mk $(VLT_EXE)__ALL.a
750
 
751 475 julius
$(SIM_VLT_DIR)/$(VLT_EXE).mk: $(SIM_VLT_DIR)/$(VLT_SCRIPT) \
752
                $(BENCH_SYSC_SRC_DIR)/libmodules.a
753 362 julius
# Now call verilator to generate the .mk files
754
        $(Q)echo; echo "\tGenerating makefiles with Verilator"; echo
755
        $(Q)cd $(SIM_VLT_DIR) && \
756 475 julius
        verilator -language 1364-2001 --top-module orpsoc_top -Mdir . -sc \
757
        $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) \
758
        -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
759 362 julius
 
760
# SystemC modules library
761
$(BENCH_SYSC_SRC_DIR)/libmodules.a:
762
        @echo; echo "\tCompiling SystemC modules"; echo
763
        $(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
764 475 julius
        $(MAKE) -C $(BENCH_SYSC_SRC_DIR) \
765
        -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
766 362 julius
 
767
print-vlt-model-link-paths:
768
        $(Q)echo $(VLT_MODEL_LINKS)
769
 
770
$(VLT_MODEL_LINKS):
771
# Link all the required system C model files into the verilator work dir
772 476 julius
        $(Q)for SYSCMODEL in $(SYSC_MODELS); do \
773 362 julius
                if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \
774 476 julius
                echo \
775
        "\tLinking SystemC model $$SYSCMODEL  Verilator model build path"; \
776 475 julius
                        ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp \
777
                                $(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \
778
                        ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h \
779
                                $(SIM_VLT_DIR)/$$SYSCMODEL.h; \
780 362 julius
                fi; \
781
        done
782
 
783
 
784
################################################################################
785
# Verilator model test rules
786
################################################################################
787
 
788 425 julius
vlt-test: build-vlt clean-sim-test-sw sw-vmem
789 362 julius
        $(SIM_VLT_DIR)/$(VLT_EXE) $(TEST)
790
 
791
vlt-tests:
792
        $(Q)for test in $(TESTS); do \
793
                export TEST=$$test; \
794
                $(MAKE) vlt-test; \
795
                if [ $$? -ne 0 ]; then break; fi; \
796
                echo; echo "\t### $$test test OK ###"; echo; \
797
        done
798
 
799
 
800
 
801
###############################################################################
802
# Verilator profiled model build rules
803
###############################################################################
804 476 julius
# To run this, first run a "make prepare-vlt-profiled"
805 362 julius
# This new make target copies athe results of the profiling back to the right
806
# paths before we create everything again
807
###############################################################################
808
.PHONY: prepare-vlt-profiled
809 363 julius
prepare-vlt-profiled: $(SIM_VLT_DIR)/OrpsocMain.gcda \
810
        clean-vlt-after-profile-run \
811
        rtl $(SIM_VLT_DIR) $(DUMMY_FILES_FOR_VLT) $(VLT_MODEL_LINKS) \
812
        $(SIM_VLT_DIR)/$(VLT_EXE)
813 362 julius
 
814
$(SIM_VLT_DIR)/OrpsocMain.gcda: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
815 397 julius
        $(MAKE) -C $(SW_DIR)/apps/dhry dhry.elf NUM_RUNS=5000
816
        $(SIM_VLT_DIR)/$(VLT_EXE) -f $(SW_DIR)/apps/dhry/dhry.elf
817 362 julius
 
818 363 julius
# Clean all compiled things
819
clean-vlt-after-profile-run:
820
        $(Q)echo "\tCleaning away compiled cycle-accurate files"
821
        $(Q)rm -f $(SIM_VLT_DIR)/*.[oa] $(SIM_VLT_DIR)/$(VLT_EXE)
822
        $(Q)rm -f $(BENCH_SYSC_SRC_DIR)/*.[oa]
823
 
824
#.PHONY: $(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling
825 362 julius
$(SIM_VLT_DIR)/$(VLT_EXE)-for-profiling:
826 363 julius
        $(MAKE) build-vlt VLT_DO_PERFORMANCE_PROFILE_BUILD=1
827 362 julius
 
828
.PHONY: vlt-restore-profileoutput
829
vlt-restore-profileoutput:
830
        @echo;echo "\tRestoring profiling outputs"; echo
831
        $(Q)mkdir -p ../vlt
832
        $(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
833
        $(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
834 363 julius
 
835
 
836
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
837
        $(Q)echo; echo "\tLinting design with Verilator"; echo
838
        $(Q)cd $(SIM_VLT_DIR) && \
839 475 julius
        verilator -language 1364-2001 --top-module orpsoc_top --lint-only \
840
        -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) \
841
        -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
842 425 julius
 
843
################################################################################
844
# Architectural simulator test rules
845
################################################################################
846
 
847
ARCH_SIM_EXE ?=or32-elf-sim
848 475 julius
ARCH_SIM_CFG ?= ../bin/refdesign-or1ksim.cfg
849 425 julius
ARCH_SIM_OPTS ?= -q
850
 
851
.PHONY: rtl-test
852
sim-test: clean-sim-test-sw sw-elf
853 431 julius
        $(Q)echo; echo "\t### Launching simulation ###"; echo
854 425 julius
        $(Q)$(ARCH_SIM_EXE) $(ARCH_SIM_OPTS) -f $(ARCH_SIM_CFG) $(TEST).elf > \
855
        $(RTL_SIM_RESULTS_DIR)/$(TEST)$(TEST_OUT_FILE_SUFFIX)
856
 
857
# Run tests in simulation, check output
858
sim-test-with-check: sim-test check-test-log
859
 
860
# Main architectural simulations test loop
861
sim-tests:
862
        $(Q)for test in $(TESTS); do \
863
                export TEST=$$test; \
864
                $(MAKE) sim-test-with-check; \
865
                if [ $$? -ne 0 ]; then break; fi; \
866
                echo; echo "\t### $$test test OK ###"; echo; \
867
        done

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