Subversion Repositories openrisc_2011-10-31

section memory

  pattern = 0x00

  type = unknown /* Fastest */

  name = "RAM"

  ce = 1

  mc = 0

  baseaddr = 0x00000000

  size = 0x02000000

  delayr = 1

  delayw = 1

end

/* IMMU SECTION

    This section configures the Instruction Memory Manangement Unit

    enabled = 0/1

       '0': disabled

       '1': enabled

       (NOTE: UPR bit is set)

    nsets = 

       number of ITLB sets; must be power of two

    nways = 

       number of ITLB ways

    pagesize = 

       instruction page size; must be power of two

    entrysize = 

       instruction entry size in bytes

    ustates = 

       number of ITLB usage states (2, 3, 4 etc., max is 4)

    hitdelay = 

       number of cycles immu hit costs

    missdelay = 

       number of cycles immu miss costs

*/

section immu

  enabled = 1

  nsets = 64

  nways = 1

  pagesize = 8192

end

/* DMMU SECTION

    This section configures the Data Memory Manangement Unit

    enabled = 0/1

       '0': disabled

       '1': enabled

       (NOTE: UPR bit is set)

    nsets = 

       number of DTLB sets; must be power of two

    nways = 

       number of DTLB ways

    pagesize = 

       data page size; must be power of two

    entrysize = 

       data entry size in bytes

    ustates = 

       number of DTLB usage states (2, 3, 4 etc., max is 4)

    hitdelay = 

       number of cycles dmmu hit costs

    missdelay = 

       number of cycles dmmu miss costs

*/

section dmmu

  enabled = 1

  nsets = 64

  nways = 1

  pagesize = 8192

end

/* IC SECTION

   This section configures the Instruction Cache

   enabled = 0/1

       '0': disabled

       '1': enabled

      (NOTE: UPR bit is set)

   nsets = 

      number of IC sets; must be power of two

   nways = 

      number of IC ways

   blocksize = 

      IC block size in bytes; must be power of two

   ustates = 

      number of IC usage states (2, 3, 4 etc., max is 4)

   hitdelay = 

      number of cycles ic hit costs

    missdelay = 

      number of cycles ic miss costs

*/

section ic

  enabled = 0

  nsets = 512

  nways = 1

  blocksize = 16

  hitdelay = 1

  missdelay = 10

end

/* DC SECTION

   This section configures the Data Cache

   enabled = 0/1

       '0': disabled

       '1': enabled

      (NOTE: UPR bit is set)

   nsets = 

      number of DC sets; must be power of two

   nways = 

      number of DC ways

   blocksize = 

      DC block size in bytes; must be power of two

   ustates = 

      number of DC usage states (2, 3, 4 etc., max is 4)

   load_hitdelay = 

      number of cycles dc load hit costs

   load_missdelay = 

      number of cycles dc load miss costs

   store_hitdelay = 

      number of cycles dc load hit costs

   store_missdelay = 

      number of cycles dc load miss costs

*/

section dc

  enabled = 0

  nsets = 512

  nways = 1

  blocksize = 16

end

/* SIM SECTION

  This section specifies how or1ksim should behave.

  verbose = 0/1

       '0': don't print extra messages

       '1': print extra messages

  debug = 0-9

      1-9: debug message level.

           higher numbers produce more messages

  profile = 0/1

      '0': don't generate profiling file 'sim.profile'

      '1': don't generate profiling file 'sim.profile'

  prof_fn = ""

      optional filename for the profiling file.

      valid only if 'profile' is set

  mprofile = 0/1

      '0': don't generate memory profiling file 'sim.mprofile'

      '1': generate memory profiling file 'sim.mprofile'

  mprof_fn = ""

      optional filename for the memory profiling file.

      valid only if 'mprofile' is set

  history = 0/1

      '0': don't track execution flow

      '1': track execution flow

      Execution flow can be tracked for the simulator's

      'hist' command. Useful for back-trace debugging.

  iprompt = 0/1

     '0': start in  (so what do we start in ???)

     '1': start in interactive prompt.

  exe_log = 0/1

      '0': don't generate execution log.

      '1': generate execution log.

  exe_log = default/hardware/simple/software

      type of execution log, default is used when not specified

  exe_log_start = 

      index of first instruction to start logging, default = 0

  exe_log_end = 

      index of last instruction to end logging; not limited, if omitted

  exe_log_marker = 

       specifies number of instructions before horizontal marker is

      printed; if zero, markers are disabled (default)

  exe_log_fn = ""

      filename for the exection log file.

      valid only if 'exe_log' is set

  clkcycle = [ps|ns|us|ms]

      specifies time measurement for one cycle

*/

section sim

  verbose = 0

  debug = 0

  profile = 0

  prof_fn = "sim.profile"

  history = 1

  /* iprompt = 0 */

  exe_log = 0

  exe_log_type = hardware

  exe_log_fn = "executed.log"

  clkcycle = 20ns

end

/* CPU SECTION

   This section specifies various CPU parameters.

   ver = 

   rev = 

      specifies version and revision of the CPU used

   upr = 

      changes the upr register

   sr = 

      sets the initial Supervision Register value

   superscalar = 0/1

      '0': CPU is scalar

      '1': CPU is superscalar

      (modify cpu/or32/execute.c to tune superscalar model)

   hazards = 0/1

      '0': don't track data hazards in superscalar CPU

      '1': track data hazards in superscalar CPU

      If tracked, data hazards can be displayed using the

      simulator's 'r' command.

   dependstats = 0/1

      '0': don't calculate inter-instruction dependencies.

      '1': calculate inter-instruction dependencies.

      If calculated, inter-instruction dependencies can be

      displayed using the simulator's 'stat' command.

   sbuf_len = 

      length of store buffer (<= 256), 0 = disabled

*/

section cpu

  ver = 0x12

  rev = 0x0008

  /* upr = */

  superscalar = 0

  hazards = 1

  dependstats = 1

  sbuf_len = 1

end

/* PM SECTION

   This section specifies Power Management parameters

   enabled = 0/1

      '0': disable power management

      '1': enable power management

*/

section pm

  enabled = 0

end

section pic

  enabled = 1

  edge_trigger = 1

end

/* UART SECTION

   This section configures the UARTs

     enabled = <0|1>

        Enable/disable the peripheral.  By default if it is enabled.

     baseaddr = 

        address of first UART register for this device

     channel = :

        The channel parameter indicates the source of received UART characters

        and the sink for transmitted UART characters.

        The  can be either "file", "xterm", "tcp", "fd", or "tty"

        (without quotes).

          A) To send/receive characters from a pair of files, use a file

             channel:

               channel=file:,

          B) To create an interactive terminal window, use an xterm channel:

               channel=xterm:[]*

          C) To create a bidirectional tcp socket which one could, for example,

             access via telnet, use a tcp channel:

               channel=tcp:

          D) To cause the UART to read/write from existing numeric file

             descriptors, use an fd channel:

               channel=fd:,

          E) To connect the UART to a physical serial port, create a tty

             channel:

               channel=tty:device=/dev/ttyS0,baud=9600

     irq = 

        irq number for this device

     16550 = 0/1

        '0': this device is a UART16450

        '1': this device is a UART16550

     jitter = 

        in msecs... time to block, -1 to disable it

     vapi_id = 

        VAPI id of this instance

*/

section uart

  enabled = 1

  baseaddr = 0x90000000

  irq = 2

  /*channel = "file:uart0.rx,uart0.tx"*/

  channel = "tcp:10084"

  jitter = -1                     /* async behaviour */

  16550 = 1

end