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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [board/] [include/] [board.h] - Blame information for rev 485

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#ifndef _BOARD_H_
#define _BOARD_H_
 
#define IN_CLK                50000000 // Hz
 
 
//
// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
//
#define RAM_BASE            0x00000000
 
#define UART0_BASE          0x90000000
#define UART0_IRQ                    2
#define UART0_BAUD_RATE         115200
 
#define SPI0_BASE 0xb0000000
 
//
// OR1200 tick timer period define
//
#define TICKS_PER_SEC   100
 
 
//
// UART driver configuration
// 
#define UART_NUM_CORES 1
#define UART_BASE_ADDRESSES_CSV UART0_BASE
#define UART_BAUD_RATES_CSV UART0_BAUD_RATE
 
 
#endif

Line No.	Rev	Author	Line
1	349	julius	`#ifndef _BOARD_H_`
2			`#define _BOARD_H_`
3
4	354	julius	`#define IN_CLK 50000000 // Hz`
5	349	julius
6	403	julius
7	349	julius	`//`
8			`// Defines for each core (memory map base, OR1200 interrupt line number, etc.)`
9			`//`
10	361	julius	`#define RAM_BASE 0x00000000`
11	349	julius
12			`#define UART0_BASE 0x90000000`
13			`#define UART0_IRQ 2`
14			`#define UART0_BAUD_RATE 115200`
15
16	373	julius	`#define SPI0_BASE 0xb0000000`
17
18	349	julius	`//`
19			`// OR1200 tick timer period define`
20			`//`
21			`#define TICKS_PER_SEC 100`
22
23	485	julius
24			`//`
25			`// UART driver configuration`
26			`//`
27			`#define UART_NUM_CORES 1`
28			`#define UART_BASE_ADDRESSES_CSV UART0_BASE`
29			`#define UART_BAUD_RATES_CSV UART0_BAUD_RATE`
30
31
32	349	julius	`#endif`

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [board/] [include/] [board.h] - Blame information for rev 485