URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [bootrom.S] - Blame information for rev 441

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
///                                                               ////
/// bootrom                                                       ////
///                                                               ////
/// Assembly programs to be embedded inside system to aid boot    ////
///                                                               ////
/// Julius Baxter, julius@opencores.org                           ////
///                                                               ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// Defines for which bootrom app to use are in board.h - TODO: use the
// processed orspoc-defines.v file for this define. It makes more sense
// as this software ends up as gates.
 
#include "board.h"
 
#ifdef BOOTROM_SPI_FLASH
 
        /* Assembly program to go into the boot ROM */
        /* For use with simple_spi SPI master core and standard SPI flash
           interface-compatible parts (ST M25P16 for example.)*/
        /* Currently just loads a program from SPI flash into RAM */
        /* Assuming address at RAM_LOAD_BASE gets clobbered, we need
           a byte writable address somewhere!*/
 
#define SPI_BASE SPI0_BASE
/* simple_spi driver */
#define SPI_SPCR 0x0
#define SPI_SPSR 0x1
#define SPI_SPDR 0x2
#define SPI_SPER 0x3
#define SPI_SPSS 0x4
 
#define SPI_SPCR_XFER_GO 0x51
#define SPI_SPSS_INIT 0x1
#define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/
 
#define RAM_LOAD_BASE SDRAM_BASE
#define RESET_ADDR 0x100
 
boot_init:
        l.movhi r0, 0
        l.movhi r1, RAM_LOAD_BASE
        l.movhi r4, hi(SPI_BASE)
 
spi_init:
        l.ori   r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */
        l.sb    SPI_SPCR(r4), r2
        l.sb    SPI_SPSS(r4), r0         /* Clear SPI slave selects */
        l.ori   r6, r0, SPI_SPSS_INIT
        l.sb    SPI_SPSS(r4), r6         /* Set appropriate slave select */
        l.jal   spi_xfer
        l.ori   r3, r0, 0x3              /* READ command opcode for SPI device*/
        l.jal   spi_xfer
#ifdef BOOTROM_ADDR_BYTE2
        l.ori   r3, r0, BOOTROM_ADDR_BYTE2 /* Use addr if defined. MSB first */
#else
        l.or    r3, r0, r0
#endif
        l.jal   spi_xfer
#ifdef BOOTROM_ADDR_BYTE1
        l.ori   r3, r0, BOOTROM_ADDR_BYTE1
#else
        l.or    r3, r0, r0
#endif
        l.jal   spi_xfer
#ifdef BOOTROM_ADDR_BYTE0
        l.ori   r3, r0, BOOTROM_ADDR_BYTE0
#else
        l.or    r3, r0, r0
#endif
        l.movhi r6, 0
        l.movhi r7, 0xffff
 
copy:
        l.jal   spi_xfer         /* Read a byte into r3 */
        l.add   r8, r1, r6       /* Calculate store address */
        l.sb    0(r8), r3        /* Write byte to memory */
        l.addi  r6, r6, 1        /* Increment counter */
        l.sfeqi r6, 0x4          /* Is this the first word ?*/
        l.bf    store_sizeword   /* put sizeword in the register */
        l.sfeq  r6, r7           /* Check if we've finished loading the words */
        l.bnf   copy             /* Continue copying if not last word */
        l.nop
 
goto_reset:
        l.ori   r1, r1, RESET_ADDR
        l.jr    r1
        l.sb    SPI_SPSS(r4), r0 /* Clear SPI slave selects */
 
store_sizeword:
#ifdef SPI_RETRY_IF_INSANE_SIZEWORD
        l.lwz   r7, 0(r1)        /* Size word is in first word of SDRAM */
        l.srli  r10, r7, 16      /* Chop the sizeword we read in half */
        l.sfgtui r10, 0x0200     /* It's unlikely we'll ever load > 32MB */
        l.bf    boot_init
        l.nop
        l.j     copy
        l.nop
 
#else
        l.j     copy
        l.lwz   r7, 0(r1)         /* Size word is in first word of SDRAM */
#endif
 
spi_xfer:
        l.sb    SPI_SPDR(r4), r3  /* Dummy write what's in r3 */
        l.ori   r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */
spi_xfer_poll:
        l.andi  r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */
        l.sfeqi r3, SPI_SPSR_RX_CHECK    /* is bit set? ... */
        l.bf    spi_xfer_poll     /* ... if so, rxfifo empty, keep polling */
        l.lbz   r3, SPI_SPSR(r4) /* Read SPSR */
        l.jr    r9
        l.lbz   r3, SPI_SPDR(r4) /* Get data byte */
 
 
#endif
 
#ifdef BOOTROM_GOTO_RESET
        /* Jump to reset vector in the SDRAM */
        l.movhi r0, 0
        l.movhi r4, SDRAM_BASE
        l.ori   r4, r4, 0x100
        l.jr    r4
        l.nop
 
#endif
 
#ifdef BOOTROM_LOOP_AT_ZERO
 
        /* Don't load app via SPI, instead just put an infinite loop into bottom
        of memory and jump there.
        */
        l.movhi r0, 0
        l.movhi r4, SDRAM_BASE
        l.sw    0x0(r4), r0
        l.movhi r5, hi(0x15000001) /* A l.nop 1 so sim exits if this enabled */
        l.ori   r5, r5, lo(0x15000001)
        l.sw    0x4(r4), r5
        l.sw    0x8(r4), r5
        l.sw    0xc(r4), r5
        l.jr    r4
        l.nop
 
 
 
#endif
 
#ifdef BOOTROM_LOOP_IN_ROM
 
        /* Don't load app via SPI, instead just put an infinite loop into bottom
        of memory and jump there.
        */
        l.movhi r0, 0
        l.nop   0x1
        l.j     0
        l.nop
        l.nop
#endif

Line No.	Rev	Author	Line
1	361	julius	`//////////////////////////////////////////////////////////////////////`
2			`/// ////`
3			`/// bootrom ////`
4			`/// ////`
5			`/// Assembly programs to be embedded inside system to aid boot ////`
6			`/// ////`
7			`/// Julius Baxter, julius@opencores.org ////`
8			`/// ////`
9			`//////////////////////////////////////////////////////////////////////`
10			`//// ////`
11			`//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////`
12			`//// ////`
13			`//// This source file may be used and distributed without ////`
14			`//// restriction provided that this copyright statement is not ////`
15			`//// removed from the file and that any derivative work contains ////`
16			`//// the original copyright notice and the associated disclaimer. ////`
17			`//// ////`
18			`//// This source file is free software; you can redistribute it ////`
19			`//// and/or modify it under the terms of the GNU Lesser General ////`
20			`//// Public License as published by the Free Software Foundation; ////`
21			`//// either version 2.1 of the License, or (at your option) any ////`
22			`//// later version. ////`
23			`//// ////`
24			`//// This source is distributed in the hope that it will be ////`
25			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
26			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
27			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
28			`//// details. ////`
29			`//// ////`
30			`//// You should have received a copy of the GNU Lesser General ////`
31			`//// Public License along with this source; if not, download it ////`
32			`//// from http://www.opencores.org/lgpl.shtml ////`
33			`//// ////`
34			`//////////////////////////////////////////////////////////////////////`
35
36			`// Defines for which bootrom app to use are in board.h - TODO: use the`
37			`// processed orspoc-defines.v file for this define. It makes more sense`
38			`// as this software ends up as gates.`
39
40			`#include "board.h"`
41
42	403	julius	`#ifdef BOOTROM_SPI_FLASH`
43	361	julius
44			`/* Assembly program to go into the boot ROM */`
45	415	julius	`/* For use with simple_spi SPI master core and standard SPI flash`
46			`interface-compatible parts (ST M25P16 for example.)*/`
47	361	julius	`/* Currently just loads a program from SPI flash into RAM */`
48			`/* Assuming address at RAM_LOAD_BASE gets clobbered, we need`
49			`a byte writable address somewhere!*/`
50
51			`#define SPI_BASE SPI0_BASE`
52			`/* simple_spi driver */`
53			`#define SPI_SPCR 0x0`
54			`#define SPI_SPSR 0x1`
55			`#define SPI_SPDR 0x2`
56			`#define SPI_SPER 0x3`
57			`#define SPI_SPSS 0x4`
58
59			`#define SPI_SPCR_XFER_GO 0x51`
60			`#define SPI_SPSS_INIT 0x1`
61			`#define SPI_SPSR_RX_CHECK 0x01 /* Check bit 0 is cleared, fifo !empty*/`
62
63			`#define RAM_LOAD_BASE SDRAM_BASE`
64			`#define RESET_ADDR 0x100`
65
66			`boot_init:`
67			`l.movhi r0, 0`
68			`l.movhi r1, RAM_LOAD_BASE`
69			`l.movhi r4, hi(SPI_BASE)`
70
71			`spi_init:`
72	415	julius	`l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */`
73			`l.sb SPI_SPCR(r4), r2`
74			`l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */`
75			`l.ori r6, r0, SPI_SPSS_INIT`
76			`l.sb SPI_SPSS(r4), r6 /* Set appropriate slave select */`
77			`l.jal spi_xfer`
78			`l.ori r3, r0, 0x3 /* READ command opcode for SPI device*/`
79			`l.jal spi_xfer`
80			`#ifdef BOOTROM_ADDR_BYTE2`
81			`l.ori r3, r0, BOOTROM_ADDR_BYTE2 /* Use addr if defined. MSB first */`
82			`#else`
83			`l.or r3, r0, r0`
84			`#endif`
85			`l.jal spi_xfer`
86			`#ifdef BOOTROM_ADDR_BYTE1`
87			`l.ori r3, r0, BOOTROM_ADDR_BYTE1`
88			`#else`
89			`l.or r3, r0, r0`
90			`#endif`
91			`l.jal spi_xfer`
92			`#ifdef BOOTROM_ADDR_BYTE0`
93			`l.ori r3, r0, BOOTROM_ADDR_BYTE0`
94			`#else`
95			`l.or r3, r0, r0`
96			`#endif`
97	361	julius	`l.movhi r6, 0`
98			`l.movhi r7, 0xffff`
99
100			`copy:`
101	415	julius	`l.jal spi_xfer /* Read a byte into r3 */`
102			`l.add r8, r1, r6 /* Calculate store address */`
103			`l.sb 0(r8), r3 /* Write byte to memory */`
104			`l.addi r6, r6, 1 /* Increment counter */`
105			`l.sfeqi r6, 0x4 /* Is this the first word ?*/`
106			`l.bf store_sizeword /* put sizeword in the register */`
107			`l.sfeq r6, r7 /* Check if we've finished loading the words */`
108			`l.bnf copy /* Continue copying if not last word */`
109	361	julius	`l.nop`
110
111			`goto_reset:`
112	415	julius	`l.ori r1, r1, RESET_ADDR`
113			`l.jr r1`
114			`l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */`
115	361	julius
116			`store_sizeword:`
117	415	julius	`#ifdef SPI_RETRY_IF_INSANE_SIZEWORD`
118			`l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */`
119			`l.srli r10, r7, 16 /* Chop the sizeword we read in half */`
120			`l.sfgtui r10, 0x0200 /* It's unlikely we'll ever load > 32MB */`
121			`l.bf boot_init`
122			`l.nop`
123			`l.j copy`
124			`l.nop`
125
126			`#else`
127			`l.j copy`
128			`l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */`
129			`#endif`
130	361	julius
131			`spi_xfer:`
132	415	julius	`l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */`
133			`l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */`
134	361	julius	`spi_xfer_poll:`
135	415	julius	`l.andi r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */`
136	361	julius	`l.sfeqi r3, SPI_SPSR_RX_CHECK /* is bit set? ... */`
137	415	julius	`l.bf spi_xfer_poll /* ... if so, rxfifo empty, keep polling */`
138			`l.lbz r3, SPI_SPSR(r4) /* Read SPSR */`
139			`l.jr r9`
140			`l.lbz r3, SPI_SPDR(r4) /* Get data byte */`
141	361	julius
142
143			`#endif`
144
145	403	julius	`#ifdef BOOTROM_GOTO_RESET`
146	361	julius	`/* Jump to reset vector in the SDRAM */`
147			`l.movhi r0, 0`
148			`l.movhi r4, SDRAM_BASE`
149	415	julius	`l.ori r4, r4, 0x100`
150			`l.jr r4`
151	361	julius	`l.nop`
152
153			`#endif`
154
155	403	julius	`#ifdef BOOTROM_LOOP_AT_ZERO`
156	361	julius
157			`/* Don't load app via SPI, instead just put an infinite loop into bottom`
158			`of memory and jump there.`
159			`*/`
160			`l.movhi r0, 0`
161			`l.movhi r4, SDRAM_BASE`
162	415	julius	`l.sw 0x0(r4), r0`
163	361	julius	`l.movhi r5, hi(0x15000001) /* A l.nop 1 so sim exits if this enabled */`
164	415	julius	`l.ori r5, r5, lo(0x15000001)`
165			`l.sw 0x4(r4), r5`
166			`l.sw 0x8(r4), r5`
167			`l.sw 0xc(r4), r5`
168			`l.jr r4`
169	361	julius	`l.nop`
170
171
172
173			`#endif`
174
175	403	julius	`#ifdef BOOTROM_LOOP_IN_ROM`
176	361	julius
177			`/* Don't load app via SPI, instead just put an infinite loop into bottom`
178			`of memory and jump there.`
179			`*/`
180			`l.movhi r0, 0`
181	415	julius	`l.nop 0x1`
182			`l.j 0`
183	361	julius	`l.nop`
184			`l.nop`
185			`#endif`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [bootrom/] [bootrom.S] - Blame information for rev 441