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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [cfi-ctrl/] [cfi_ctrl.c] - Blame information for rev 852

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/* Driver functions for cfi_ctrl module which is to control
   CFI flash devices.
*/
 
#include "board.h"
#include "cpu-utils.h"
#include "cfi_ctrl.h"
 
#ifndef CFI_CTRL_BASE
#define CFI_CTRL_BASE -1
#endif
 
void cfi_ctrl_reset_flash(void)
{
  //REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) = CFI_CTRL_SCR_RESET_DEVICE;
  // Put in array read mode, like reset would
  REG16(CFI_CTRL_BASE) = 0x00ff;
 
}
 
int cfi_ctrl_busy(void)
{
  //  return REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) & 
  //CFI_CTRL_SCR_CONTROLLER_BUSY;
  return 0;
}
 
void cfi_ctrl_clear_status(void)
{
  //REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) = CFI_CTRL_SCR_CLEAR_FSR;
  REG16(CFI_CTRL_BASE) = 0x0050;
}
 
unsigned char cfi_ctrl_get_status(void)
{
  //return (unsigned char) (REG32((CFI_CTRL_BASE + CFI_CTRL_FSR_OFFSET)) & 0xff);
  REG16(CFI_CTRL_BASE) = 0x0070;
  return (unsigned char) REG16(CFI_CTRL_BASE);
}
 
void cfi_ctrl_unlock_block(unsigned int addr)
{
  //REG32((CFI_CTRL_BASE + CFI_CTRL_UNLOCKBLOCK_OFFSET + addr)) = 0;
  REG16(CFI_CTRL_BASE + addr) = 0x0060;
  REG16(CFI_CTRL_BASE + addr) = 0x00d0;
}
 
int cfi_ctrl_erase_block(unsigned int addr)
{
  cfi_ctrl_clear_status();
 
  /* Unlock block first */
  cfi_ctrl_unlock_block(addr);
 
  //REG32((CFI_CTRL_BASE + CFI_CTRL_ERASEBLOCK_OFFSET + addr)) = 0;
  REG16(CFI_CTRL_BASE + addr) = 0x0020;
  REG16(CFI_CTRL_BASE + addr) = 0x00d0;
 
  /* Wait for device to be finished erasing */
  while(!(cfi_ctrl_get_status() & CFI_FSR_DWS));
 
  /* Check if programming was successful */
  return !!(cfi_ctrl_get_status() & CFI_FSR_ES);
 
}
 
void cfi_ctrl_erase_block_no_wait(unsigned int addr)
{
  cfi_ctrl_clear_status();
 
  /* Unlock block first */
  cfi_ctrl_unlock_block(addr);
 
  /* Now erase the block */
  REG16(CFI_CTRL_BASE + addr) = 0x0020;
  REG16(CFI_CTRL_BASE + addr) = 0x00d0;
  //  REG32((CFI_CTRL_BASE + CFI_CTRL_ERASEBLOCK_OFFSET + addr)) = 0;
 
  return;
 
}
 
int cfi_ctrl_write_short(short data, unsigned int addr)
{
 
  cfi_ctrl_clear_status();
 
  REG16(CFI_CTRL_BASE + addr) = 0x0040;
  REG16(CFI_CTRL_BASE + addr) = data;
 
  /* Wait for device to write */
  while(!(cfi_ctrl_get_status() & CFI_FSR_DWS));
 
  /* Check if programming was successful */
  return !!(cfi_ctrl_get_status() & CFI_FSR_PS);
}
 
void cfi_ctrl_enable_data_read(void)
{
  REG16(CFI_CTRL_BASE) = 0x00ff;
}
 
short cfi_ctrl_read_identifier(unsigned int addr)
{
  //return REG16(CFI_CTRL_BASE + CFI_CTRL_DEVICEIDENT_OFFSET + (addr<<1));
  REG16(CFI_CTRL_BASE) = 0x0090;
  return REG16(CFI_CTRL_BASE + (addr<<1));
}
 
short cfi_ctrl_query_info(unsigned int addr)
{
  REG16(CFI_CTRL_BASE) = 0x0098;
  return REG16(CFI_CTRL_BASE + (addr<<1));
}
 
 

Line No.	Rev	Author	Line
1	655	julius	`/* Driver functions for cfi_ctrl module which is to control`
2			`CFI flash devices.`
3			`*/`
4
5			`#include "board.h"`
6			`#include "cpu-utils.h"`
7			`#include "cfi_ctrl.h"`
8
9	656	julius	`#ifndef CFI_CTRL_BASE`
10			`#define CFI_CTRL_BASE -1`
11			`#endif`
12
13	655	julius	`void cfi_ctrl_reset_flash(void)`
14			`{`
15			`//REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) = CFI_CTRL_SCR_RESET_DEVICE;`
16			`// Put in array read mode, like reset would`
17			`REG16(CFI_CTRL_BASE) = 0x00ff;`
18
19			`}`
20
21			`int cfi_ctrl_busy(void)`
22			`{`
23			`// return REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) &`
24			`//CFI_CTRL_SCR_CONTROLLER_BUSY;`
25			`return 0;`
26			`}`
27
28			`void cfi_ctrl_clear_status(void)`
29			`{`
30			`//REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) = CFI_CTRL_SCR_CLEAR_FSR;`
31			`REG16(CFI_CTRL_BASE) = 0x0050;`
32			`}`
33
34			`unsigned char cfi_ctrl_get_status(void)`
35			`{`
36			`//return (unsigned char) (REG32((CFI_CTRL_BASE + CFI_CTRL_FSR_OFFSET)) & 0xff);`
37			`REG16(CFI_CTRL_BASE) = 0x0070;`
38			`return (unsigned char) REG16(CFI_CTRL_BASE);`
39			`}`
40
41			`void cfi_ctrl_unlock_block(unsigned int addr)`
42			`{`
43			`//REG32((CFI_CTRL_BASE + CFI_CTRL_UNLOCKBLOCK_OFFSET + addr)) = 0;`
44			`REG16(CFI_CTRL_BASE + addr) = 0x0060;`
45			`REG16(CFI_CTRL_BASE + addr) = 0x00d0;`
46			`}`
47
48			`int cfi_ctrl_erase_block(unsigned int addr)`
49			`{`
50			`cfi_ctrl_clear_status();`
51
52			`/* Unlock block first */`
53			`cfi_ctrl_unlock_block(addr);`
54
55			`//REG32((CFI_CTRL_BASE + CFI_CTRL_ERASEBLOCK_OFFSET + addr)) = 0;`
56			`REG16(CFI_CTRL_BASE + addr) = 0x0020;`
57			`REG16(CFI_CTRL_BASE + addr) = 0x00d0;`
58
59			`/* Wait for device to be finished erasing */`
60			`while(!(cfi_ctrl_get_status() & CFI_FSR_DWS));`
61
62			`/* Check if programming was successful */`
63			`return !!(cfi_ctrl_get_status() & CFI_FSR_ES);`
64
65			`}`
66
67			`void cfi_ctrl_erase_block_no_wait(unsigned int addr)`
68			`{`
69			`cfi_ctrl_clear_status();`
70
71			`/* Unlock block first */`
72			`cfi_ctrl_unlock_block(addr);`
73
74			`/* Now erase the block */`
75			`REG16(CFI_CTRL_BASE + addr) = 0x0020;`
76			`REG16(CFI_CTRL_BASE + addr) = 0x00d0;`
77			`// REG32((CFI_CTRL_BASE + CFI_CTRL_ERASEBLOCK_OFFSET + addr)) = 0;`
78
79			`return;`
80
81			`}`
82
83			`int cfi_ctrl_write_short(short data, unsigned int addr)`
84			`{`
85
86			`cfi_ctrl_clear_status();`
87
88			`REG16(CFI_CTRL_BASE + addr) = 0x0040;`
89			`REG16(CFI_CTRL_BASE + addr) = data;`
90
91			`/* Wait for device to write */`
92			`while(!(cfi_ctrl_get_status() & CFI_FSR_DWS));`
93
94			`/* Check if programming was successful */`
95			`return !!(cfi_ctrl_get_status() & CFI_FSR_PS);`
96			`}`
97
98			`void cfi_ctrl_enable_data_read(void)`
99			`{`
100			`REG16(CFI_CTRL_BASE) = 0x00ff;`
101			`}`
102
103			`short cfi_ctrl_read_identifier(unsigned int addr)`
104			`{`
105			`//return REG16(CFI_CTRL_BASE + CFI_CTRL_DEVICEIDENT_OFFSET + (addr<<1));`
106			`REG16(CFI_CTRL_BASE) = 0x0090;`
107			`return REG16(CFI_CTRL_BASE + (addr<<1));`
108			`}`
109
110			`short cfi_ctrl_query_info(unsigned int addr)`
111			`{`
112			`REG16(CFI_CTRL_BASE) = 0x0098;`
113			`return REG16(CFI_CTRL_BASE + (addr<<1));`
114			`}`
115
116

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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [cfi-ctrl/] [cfi_ctrl.c] - Blame information for rev 852