URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [ethmac/] [include/] [ethmac.h] - Blame information for rev 853

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Ethernet MAC driver functions                               ////
////                                                              ////
////  Description                                                 ////
////  A collection of functions to help control the OpenCores     ////
////  10/100 ethernet mac (ethmac) core.                          ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Julius Baxter, julius@opencores.org                   ////
////      - Parts taken from Linux kernel's open_eth driver.      ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
#ifndef _ETHMAC_H_
#define _ETHMAC_H
typedef unsigned int uint;
 
/* Ethernet configuration registers */
typedef struct _oeth_regs {
        uint    moder;          /* Mode Register */
        uint    int_src;        /* Interrupt Source Register */
        uint    int_mask;       /* Interrupt Mask Register */
        uint    ipgt;           /* Back to Bak Inter Packet Gap Register */
        uint    ipgr1;          /* Non Back to Back Inter Packet Gap Register 1 */
        uint    ipgr2;          /* Non Back to Back Inter Packet Gap Register 2 */
        uint    packet_len;     /* Packet Length Register (min. and max.) */
        uint    collconf;       /* Collision and Retry Configuration Register */
        uint    tx_bd_num;      /* Transmit Buffer Descriptor Number Register */
        uint    ctrlmoder;      /* Control Module Mode Register */
        uint    miimoder;       /* MII Mode Register */
        uint    miicommand;     /* MII Command Register */
        uint    miiaddress;     /* MII Address Register */
        uint    miitx_data;     /* MII Transmit Data Register */
        uint    miirx_data;     /* MII Receive Data Register */
        uint    miistatus;      /* MII Status Register */
        uint    mac_addr0;      /* MAC Individual Address Register 0 */
        uint    mac_addr1;      /* MAC Individual Address Register 1 */
        uint    hash_addr0;     /* Hash Register 0 */
        uint    hash_addr1;     /* Hash Register 1 */
        uint    txctrl;         /* Transmit control frame Register */
        uint    rxctrl;         /* Rx control frame Register */
        uint    wbdbg;          /* Wishbone state machine debug information */
 
} oeth_regs;
 
/* Ethernet buffer descriptor */
typedef struct _oeth_bd {
#if 0
        ushort  len;            /* Buffer length */
        ushort  status;         /* Buffer status */
#else
        uint    len_status;
#endif
        uint    addr;           /* Buffer address */
} oeth_bd;
 
// From board.h
#define ETH_BASE_ADD    ETH0_BASE
 
#define OETH_REG_BASE           ETH_BASE_ADD
#define OETH_BD_BASE            (ETH_BASE_ADD + 0x400)
#define OETH_TOTAL_BD           128
#define OETH_MAXBUF_LEN         0x600
 
/* Tx BD */
#define OETH_TX_BD_READY        0x8000 /* Tx BD Ready */
#define OETH_TX_BD_IRQ          0x4000 /* Tx BD IRQ Enable */
#define OETH_TX_BD_WRAP         0x2000 /* Tx BD Wrap (last BD) */
#define OETH_TX_BD_PAD          0x1000 /* Tx BD Pad Enable */
#define OETH_TX_BD_CRC          0x0800 /* Tx BD CRC Enable */
 
#define OETH_TX_BD_UNDERRUN     0x0100 /* Tx BD Underrun Status */
#define OETH_TX_BD_RETRY        0x00F0 /* Tx BD Retry Status */
#define OETH_TX_BD_RETLIM       0x0008 /* Tx BD Retransmission Limit Status */
#define OETH_TX_BD_LATECOL      0x0004 /* Tx BD Late Collision Status */
#define OETH_TX_BD_DEFER        0x0002 /* Tx BD Defer Status */
#define OETH_TX_BD_CARRIER      0x0001 /* Tx BD Carrier Sense Lost Status */
#define OETH_TX_BD_STATS        (OETH_TX_BD_UNDERRUN            | \
                                OETH_TX_BD_RETRY                | \
                                OETH_TX_BD_RETLIM               | \
                                OETH_TX_BD_LATECOL              | \
                                OETH_TX_BD_DEFER                | \
                                OETH_TX_BD_CARRIER)
 
/* Rx BD */
#define OETH_RX_BD_EMPTY        0x8000 /* Rx BD Empty */
#define OETH_RX_BD_IRQ          0x4000 /* Rx BD IRQ Enable */
#define OETH_RX_BD_WRAP         0x2000 /* Rx BD Wrap (last BD) */
 
#define OETH_RX_BD_MISS         0x0080 /* Rx BD Miss Status */
#define OETH_RX_BD_OVERRUN      0x0040 /* Rx BD Overrun Status */
#define OETH_RX_BD_INVSIMB      0x0020 /* Rx BD Invalid Symbol Status */
#define OETH_RX_BD_DRIBBLE      0x0010 /* Rx BD Dribble Nibble Status */
#define OETH_RX_BD_TOOLONG      0x0008 /* Rx BD Too Long Status */
#define OETH_RX_BD_SHORT        0x0004 /* Rx BD Too Short Frame Status */
#define OETH_RX_BD_CRCERR       0x0002 /* Rx BD CRC Error Status */
#define OETH_RX_BD_LATECOL      0x0001 /* Rx BD Late Collision Status */
#define OETH_RX_BD_STATS        (OETH_RX_BD_MISS                | \
                                OETH_RX_BD_OVERRUN              | \
                                OETH_RX_BD_INVSIMB              | \
                                OETH_RX_BD_DRIBBLE              | \
                                OETH_RX_BD_TOOLONG              | \
                                OETH_RX_BD_SHORT                | \
                                OETH_RX_BD_CRCERR               | \
                                OETH_RX_BD_LATECOL)
 
/* MODER Register */
#define OETH_MODER_RXEN         0x00000001 /* Receive Enable  */
#define OETH_MODER_TXEN         0x00000002 /* Transmit Enable */
#define OETH_MODER_NOPRE        0x00000004 /* No Preamble  */
#define OETH_MODER_BRO          0x00000008 /* Reject Broadcast */
#define OETH_MODER_IAM          0x00000010 /* Use Individual Hash */
#define OETH_MODER_PRO          0x00000020 /* Promiscuous (receive all) */
#define OETH_MODER_IFG          0x00000040 /* Min. IFG not required */
#define OETH_MODER_LOOPBCK      0x00000080 /* Loop Back */
#define OETH_MODER_NOBCKOF      0x00000100 /* No Backoff */
#define OETH_MODER_EXDFREN      0x00000200 /* Excess Defer */
#define OETH_MODER_FULLD        0x00000400 /* Full Duplex */
#define OETH_MODER_RST          0x00000800 /* Reset MAC */
#define OETH_MODER_DLYCRCEN     0x00001000 /* Delayed CRC Enable */
#define OETH_MODER_CRCEN        0x00002000 /* CRC Enable */
#define OETH_MODER_HUGEN        0x00004000 /* Huge Enable */
#define OETH_MODER_PAD          0x00008000 /* Pad Enable */
#define OETH_MODER_RECSMALL     0x00010000 /* Receive Small */
 
/* Interrupt Source Register */
#define OETH_INT_TXB            0x00000001 /* Transmit Buffer IRQ */
#define OETH_INT_TXE            0x00000002 /* Transmit Error IRQ */
#define OETH_INT_RXF            0x00000004 /* Receive Frame IRQ */
#define OETH_INT_RXE            0x00000008 /* Receive Error IRQ */
#define OETH_INT_BUSY           0x00000010 /* Busy IRQ */
#define OETH_INT_TXC            0x00000020 /* Transmit Control Frame IRQ */
#define OETH_INT_RXC            0x00000040 /* Received Control Frame IRQ */
 
/* Interrupt Mask Register */
#define OETH_INT_MASK_TXB       0x00000001 /* Transmit Buffer IRQ Mask */
#define OETH_INT_MASK_TXE       0x00000002 /* Transmit Error IRQ Mask */
#define OETH_INT_MASK_RXF       0x00000004 /* Receive Frame IRQ Mask */
#define OETH_INT_MASK_RXE       0x00000008 /* Receive Error IRQ Mask */
#define OETH_INT_MASK_BUSY      0x00000010 /* Busy IRQ Mask */
#define OETH_INT_MASK_TXC       0x00000020 /* Transmit Control Frame IRQ Mask */
#define OETH_INT_MASK_RXC       0x00000040 /* Received Control Frame IRQ Mask */
 
/* Control Module Mode Register */
#define OETH_CTRLMODER_PASSALL  0x00000001 /* Pass Control Frames */
#define OETH_CTRLMODER_RXFLOW   0x00000002 /* Receive Control Flow Enable */
#define OETH_CTRLMODER_TXFLOW   0x00000004 /* Transmit Control Flow Enable */
 
/* MII Mode Register */
#define OETH_MIIMODER_CLKDIV    0x000000FF /* Clock Divider */
#define OETH_MIIMODER_NOPRE     0x00000100 /* No Preamble */
#define OETH_MIIMODER_RST       0x00000200 /* MIIM Reset */
 
/* MII Command Register */
#define OETH_MIICOMMAND_SCANSTAT  0x00000001 /* Scan Status */
#define OETH_MIICOMMAND_RSTAT     0x00000002 /* Read Status */
#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
 
/* MII Address Register */
#define OETH_MIIADDRESS_FIAD    0x0000001F /* PHY Address */
#define OETH_MIIADDRESS_RGAD    0x00001F00 /* RGAD Address */
 
/* MII Status Register */
#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
#define OETH_MIISTATUS_BUSY     0x00000002 /* MII Busy */
#define OETH_MIISTATUS_NVALID   0x00000004 /* Data in MII Status Register is invalid */
 
/* Dummy function for now, just to make the driver compile */
void ethmac_init();
 
#endif

Line No.	Rev	Author	Line
1	409	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Ethernet MAC driver functions ////`
4			`//// ////`
5			`//// Description ////`
6			`//// A collection of functions to help control the OpenCores ////`
7			`//// 10/100 ethernet mac (ethmac) core. ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// - Julius Baxter, julius@opencores.org ////`
12			`//// - Parts taken from Linux kernel's open_eth driver. ////`
13			`//// ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41	408	julius
42	409	julius	`#ifndef _ETHMAC_H_`
43			`#define _ETHMAC_H`
44	408	julius	`typedef unsigned int uint;`
45
46			`/* Ethernet configuration registers */`
47			`typedef struct _oeth_regs {`
48			`uint moder; /* Mode Register */`
49			`uint int_src; /* Interrupt Source Register */`
50			`uint int_mask; /* Interrupt Mask Register */`
51			`uint ipgt; /* Back to Bak Inter Packet Gap Register */`
52			`uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */`
53			`uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */`
54			`uint packet_len; /* Packet Length Register (min. and max.) */`
55			`uint collconf; /* Collision and Retry Configuration Register */`
56			`uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */`
57			`uint ctrlmoder; /* Control Module Mode Register */`
58			`uint miimoder; /* MII Mode Register */`
59			`uint miicommand; /* MII Command Register */`
60			`uint miiaddress; /* MII Address Register */`
61			`uint miitx_data; /* MII Transmit Data Register */`
62			`uint miirx_data; /* MII Receive Data Register */`
63			`uint miistatus; /* MII Status Register */`
64			`uint mac_addr0; /* MAC Individual Address Register 0 */`
65			`uint mac_addr1; /* MAC Individual Address Register 1 */`
66			`uint hash_addr0; /* Hash Register 0 */`
67	530	julius	`uint hash_addr1; /* Hash Register 1 */`
68			`uint txctrl; /* Transmit control frame Register */`
69			`uint rxctrl; /* Rx control frame Register */`
70			`uint wbdbg; /* Wishbone state machine debug information */`
71
72	408	julius	`} oeth_regs;`
73
74			`/* Ethernet buffer descriptor */`
75			`typedef struct _oeth_bd {`
76			`#if 0`
77			`ushort len; /* Buffer length */`
78			`ushort status; /* Buffer status */`
79			`#else`
80			`uint len_status;`
81			`#endif`
82			`uint addr; /* Buffer address */`
83			`} oeth_bd;`
84
85			`// From board.h`
86			`#define ETH_BASE_ADD ETH0_BASE`
87
88			`#define OETH_REG_BASE ETH_BASE_ADD`
89			`#define OETH_BD_BASE (ETH_BASE_ADD + 0x400)`
90			`#define OETH_TOTAL_BD 128`
91			`#define OETH_MAXBUF_LEN 0x600`
92
93			`/* Tx BD */`
94			`#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */`
95			`#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */`
96			`#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */`
97			`#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */`
98			`#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */`
99
100			`#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */`
101			`#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */`
102			`#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */`
103			`#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */`
104			`#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */`
105			`#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */`
106			`#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN \| \`
107			`OETH_TX_BD_RETRY \| \`
108			`OETH_TX_BD_RETLIM \| \`
109			`OETH_TX_BD_LATECOL \| \`
110			`OETH_TX_BD_DEFER \| \`
111			`OETH_TX_BD_CARRIER)`
112
113			`/* Rx BD */`
114			`#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */`
115			`#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */`
116			`#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */`
117
118			`#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */`
119			`#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */`
120			`#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */`
121			`#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */`
122			`#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */`
123			`#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */`
124			`#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */`
125			`#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */`
126			`#define OETH_RX_BD_STATS (OETH_RX_BD_MISS \| \`
127			`OETH_RX_BD_OVERRUN \| \`
128			`OETH_RX_BD_INVSIMB \| \`
129			`OETH_RX_BD_DRIBBLE \| \`
130			`OETH_RX_BD_TOOLONG \| \`
131			`OETH_RX_BD_SHORT \| \`
132			`OETH_RX_BD_CRCERR \| \`
133			`OETH_RX_BD_LATECOL)`
134
135			`/* MODER Register */`
136			`#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */`
137			`#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */`
138			`#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */`
139			`#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */`
140			`#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */`
141			`#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */`
142			`#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */`
143			`#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */`
144			`#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */`
145			`#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */`
146			`#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */`
147			`#define OETH_MODER_RST 0x00000800 /* Reset MAC */`
148			`#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */`
149			`#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */`
150			`#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */`
151			`#define OETH_MODER_PAD 0x00008000 /* Pad Enable */`
152			`#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */`
153
154			`/* Interrupt Source Register */`
155			`#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */`
156			`#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */`
157			`#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */`
158			`#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */`
159			`#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */`
160			`#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */`
161			`#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */`
162
163			`/* Interrupt Mask Register */`
164			`#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */`
165			`#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */`
166			`#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */`
167			`#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */`
168			`#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */`
169			`#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */`
170			`#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */`
171
172			`/* Control Module Mode Register */`
173			`#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */`
174			`#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */`
175			`#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */`
176
177			`/* MII Mode Register */`
178			`#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */`
179			`#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */`
180			`#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */`
181
182			`/* MII Command Register */`
183			`#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */`
184			`#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */`
185			`#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */`
186
187			`/* MII Address Register */`
188			`#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */`
189			`#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */`
190
191			`/* MII Status Register */`
192			`#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */`
193			`#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */`
194			`#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */`
195
196	409	julius	`/* Dummy function for now, just to make the driver compile */`
197			`void ethmac_init();`
198
199	408	julius	`#endif`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [ethmac/] [include/] [ethmac.h] - Blame information for rev 853