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[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [i2c_master_slave/] [include/] [i2c_master_slave.h] - Blame information for rev 522

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1 393 julius
/*************************************************************
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 * I2C functions for Herveille i2c master_slave core         *
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 *                                                           *
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 * Provides functions to read from and write to the I2C bus. *
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 * Master and slave mode are both supported                  *
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 *                                                           *
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 *                                                           *
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 ************************************************************/
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#ifndef _I2C_MASTER_SLAVE_H_
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#define _I2C_MASTER_SLAVE_H_
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//Memory mapping adresses
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#define I2C_MASTER_SLAVE_PRERlo 0x0     // Clock prescaler register
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#define I2C_MASTER_SLAVE_PRERhi 0x1     // Clock prescaler register
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#define I2C_MASTER_SLAVE_CTR    0x2     // Control register
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#define I2C_MASTER_SLAVE_TXR    0x3     // Transmit register
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#define I2C_MASTER_SLAVE_RXR    0x3     // Recive register
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#define I2C_MASTER_SLAVE_CR     0x4     // Control register
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#define I2C_MASTER_SLAVE_SR     0x4     // Status register
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#define I2C_MASTER_SLAVE_SLADR  0x7     // Slave address register
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#define I2C_MASTER_SLAVE_CTR_CORE_ENABLE 0x80
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#define I2C_MASTER_SLAVE_CTR_INTR_ENABLE 0x40
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#define I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE 0x20
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#define I2C_MASTER_SLAVE_CR_START        0x80
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#define I2C_MASTER_SLAVE_CR_STOP         0x40
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#define I2C_MASTER_SLAVE_CR_READ         0x20
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#define I2C_MASTER_SLAVE_CR_WRITE        0x10
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#define I2C_MASTER_SLAVE_CR_ACK          0x08
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#define I2C_MASTER_SLAVE_CR_SL_CONT      0x02
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#define I2C_MASTER_SLAVE_CR_IACK         0x01
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#define I2C_MASTER_SLAVE_SR_RXACK            0x80
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#define I2C_MASTER_SLAVE_SR_BUSY             0x40
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#define I2C_MASTER_SLAVE_SR_ARB_LOST         0x20
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#define I2C_MASTER_SLAVE_SR_SLAVE_MODE       0x10
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#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_AVAIL 0x08
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#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_REQ   0x04
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#define I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG  0x02
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#define I2C_MASTER_SLAVE_SR_IRQ_FLAG         0x01
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int i2c_master_slave_init_core(int core, unsigned short prescaler,
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                               int interrupt_enable);
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int i2c_master_slave_deact_core(int core);
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int i2c_master_slave_init_as_slave(int core, char addr);
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int i2c_master_slave_deact_as_slave(int core);
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int i2c_master_slave_master_start(int core, unsigned char addr, int read);
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int i2c_master_slave_master_write(int core, unsigned char data,
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                                  int check_prev_ack, int stop);
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int i2c_master_slave_master_stop(int core);
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int i2c_master_slave_master_read(int core, int check_prev_ack, int stop,
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                                 char *data);
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int i2c_master_slave_ack_interrupt(int core);
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#endif

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