OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [i2c_master_slave/] [include/] [i2c_master_slave.h] - Blame information for rev 820

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 393 julius
/*************************************************************
2
 * I2C functions for Herveille i2c master_slave core         *
3
 *                                                           *
4
 * Provides functions to read from and write to the I2C bus. *
5
 * Master and slave mode are both supported                  *
6
 *                                                           *
7
 *                                                           *
8
 ************************************************************/
9
 
10
#ifndef _I2C_MASTER_SLAVE_H_
11
#define _I2C_MASTER_SLAVE_H_
12
 
13
//Memory mapping adresses
14
 
15 403 julius
#define I2C_MASTER_SLAVE_PRERlo 0x0     // Clock prescaler register
16
#define I2C_MASTER_SLAVE_PRERhi 0x1     // Clock prescaler register
17
#define I2C_MASTER_SLAVE_CTR    0x2     // Control register
18
#define I2C_MASTER_SLAVE_TXR    0x3     // Transmit register
19
#define I2C_MASTER_SLAVE_RXR    0x3     // Recive register
20
#define I2C_MASTER_SLAVE_CR     0x4     // Control register
21
#define I2C_MASTER_SLAVE_SR     0x4     // Status register
22
#define I2C_MASTER_SLAVE_SLADR  0x7     // Slave address register
23 393 julius
 
24 403 julius
#define I2C_MASTER_SLAVE_CTR_CORE_ENABLE 0x80
25
#define I2C_MASTER_SLAVE_CTR_INTR_ENABLE 0x40
26
#define I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE 0x20
27 393 julius
 
28 403 julius
#define I2C_MASTER_SLAVE_CR_START        0x80
29
#define I2C_MASTER_SLAVE_CR_STOP         0x40
30
#define I2C_MASTER_SLAVE_CR_READ         0x20
31
#define I2C_MASTER_SLAVE_CR_WRITE        0x10
32
#define I2C_MASTER_SLAVE_CR_ACK          0x08
33
#define I2C_MASTER_SLAVE_CR_SL_CONT      0x02
34
#define I2C_MASTER_SLAVE_CR_IACK         0x01
35 393 julius
 
36 403 julius
#define I2C_MASTER_SLAVE_SR_RXACK            0x80
37
#define I2C_MASTER_SLAVE_SR_BUSY             0x40
38
#define I2C_MASTER_SLAVE_SR_ARB_LOST         0x20
39
#define I2C_MASTER_SLAVE_SR_SLAVE_MODE       0x10
40
#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_AVAIL 0x08
41
#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_REQ   0x04
42
#define I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG  0x02
43
#define I2C_MASTER_SLAVE_SR_IRQ_FLAG         0x01
44 393 julius
 
45 403 julius
int i2c_master_slave_init_core(int core, unsigned short prescaler,
46
                               int interrupt_enable);
47
int i2c_master_slave_deact_core(int core);
48
int i2c_master_slave_init_as_slave(int core, char addr);
49
int i2c_master_slave_deact_as_slave(int core);
50
int i2c_master_slave_master_start(int core, unsigned char addr, int read);
51
int i2c_master_slave_master_write(int core, unsigned char data,
52
                                  int check_prev_ack, int stop);
53
int i2c_master_slave_master_stop(int core);
54
int i2c_master_slave_master_read(int core, int check_prev_ack, int stop,
55
                                 char *data);
56
int i2c_master_slave_ack_interrupt(int core);
57 393 julius
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.