URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Blame information for rev 479

Go to most recent revision | Details | Compare with Previous | View Log


#include "spr-defs.h"
#include "board.h"
 
/* ======================================================= [ macros ] === */
 
#define REDZONE 128
#define EXCEPTION_STACK_SIZE (128 + REDZONE)
 
#define CLEAR_GPR(gpr) \
        l.or    gpr, r0, r0
 
#define ENTRY(symbol)    \
        .global symbol ; \
symbol:
 
#define LOAD_SYMBOL_2_GPR(gpr,symbol)  \
        .global symbol ;               \
        l.movhi gpr, hi(symbol) ;      \
        l.ori   gpr, gpr, lo(symbol)
 
        // Really goes to configurable interrupt handler
#define EXCEPTION_HANDLER            \
        l.addi  r1, r1, -EXCEPTION_STACK_SIZE;          \
        l.sw    4(r1), r3;             \
        l.sw    8(r1), r4;             \
        l.mfspr r3,r0,SPR_NPC;          \
        l.mfspr r4,r0,SPR_EPCR_BASE;   \
        l.j default_exception_handler; \
        l.nop
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Early Stack initilization */
        LOAD_SYMBOL_2_GPR(r1, _stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
 
        /* Jump to program initialisation code */
        LOAD_SYMBOL_2_GPR(r4, _start)
        l.jr    r4
        l.nop
 
/* ---[ 0x200: BUS exception ]------------------------------------------- */
        .org 0x200
        EXCEPTION_HANDLER
 
/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
        .org 0x300
        EXCEPTION_HANDLER
 
/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
        .org 0x400
        EXCEPTION_HANDLER
 
 
/* ---[ 0x500: Timer exception ]----------------------------------------- */
        .org 0x500
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
        //EXCEPTION_HANDLER
        /* Simply load timer_ticks variable and increment */
        .extern timer_ticks
        l.addi  r1, r1, -136
        l.sw    0(r1), r25
        l.sw    4(r1), r26
        l.movhi r25, hi(timer_ticks)
        l.ori   r25, r25, lo(timer_ticks)
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
        l.addi  r26, r26, 1                     /* Increment variable */
        l.sw    0(r25), r26                     /* Store variable */
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
        l.lwz   r25, 0(r1)
        l.lwz   r26, 4(r1)
        l.addi  r1, r1, 136
        l.rfe
 
/* ---[ 0x600: Aligment exception ]-------------------------------------- */
        .org 0x600
        EXCEPTION_HANDLER
 
/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
        .org 0x700
        EXCEPTION_HANDLER
 
/* ---[ 0x800: External interrupt exception ]---------------------------- */
        .org 0x800
        EXCEPTION_HANDLER
 
/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
        .org 0x900
        EXCEPTION_HANDLER
 
/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
        .org 0xa00
        EXCEPTION_HANDLER
 
/* ---[ 0xb00: Range exception ]----------------------------------------- */
        .org 0xb00
        EXCEPTION_HANDLER
 
/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
        .org 0xc00
        EXCEPTION_HANDLER
 
/* ---[ 0xd00: FPU exception ]------------------------------------------- */
        .org 0xd00
        EXCEPTION_HANDLER
 
/* ---[ 0xe00: Trap exception ]------------------------------------------ */
        .org 0xe00
        EXCEPTION_HANDLER
 
/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */
/*
        .org 0xf00
        EXCEPTION_HANDLER
 
        .org 0x1000
        EXCEPTION_HANDLER
 
        .org 0x1100
        EXCEPTION_HANDLER
 
        .org 0x1200
        EXCEPTION_HANDLER
 
        .org 0x1300
        EXCEPTION_HANDLER
 
        .org 0x1400
        EXCEPTION_HANDLER
 
*/
/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */
/*
        .org 0x1500
        EXCEPTION_HANDLER
 
        .org 0x1600
        EXCEPTION_HANDLER
 
        .org 0x1700
        EXCEPTION_HANDLER
 
        .org 0x1800
        EXCEPTION_HANDLER
*/
/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */
/*
        .org 0x1900
        EXCEPTION_HANDLER
 
        .org 0x1a00
        EXCEPTION_HANDLER
 
        .org 0x1b00
        EXCEPTION_HANDLER
 
        .org 0x1c00
        EXCEPTION_HANDLER
 
        .org 0x1d00
        EXCEPTION_HANDLER
 
        .org 0x1e00
        EXCEPTION_HANDLER
 
        .org 0x1f00
        EXCEPTION_HANDLER
*/
 
/* ========================================================= [ entry ] === */
        .section .text
 
ENTRY(_start)
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
.L10:
 
        /* Initialise stack */
/*      LOAD_SYMBOL_2_GPR(r1, _stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
*/
        /* Clear BSS */
        LOAD_SYMBOL_2_GPR(r28, _bss_start)
        LOAD_SYMBOL_2_GPR(r30, _bss_end)
1:
        l.sw    (0)(r28), r0
        l.sfltu r28, r30
        l.bf    1b
        l.addi  r28, r28, 4
 
 
        /* Initialise UART in a C function */
        /*l.jal    _uart_init
        l.nop*/
 
 
        /* Jump to main program entry point (argc = argv = 0) */
        CLEAR_GPR(r3)
        CLEAR_GPR(r4)
        l.jal   main
        l.nop
 
        /* If program exits, call exit routine */
        l.addi  r3, r11, 0
        l.jal   exit
        l.nop
 
 
/* ====================================== [ default exception handler ] === */
 
default_exception_handler:
        l.sw    0x00(r1), r2
        l.sw    0x0c(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
        l.sw    0x78(r1), r32
 
        l.jal   default_exception_handler_c
        l.nop
 
        l.lwz    r2, 0x00(r1)
        l.lwz    r3, 0x04(r1)
        l.lwz    r4, 0x08(r1)
        l.lwz    r5, 0x0c(r1)
        l.lwz    r6, 0x10(r1)
        l.lwz    r7, 0x14(r1)
        l.lwz    r8, 0x18(r1)
        l.lwz    r9, 0x1c(r1)
        l.lwz    r10, 0x20(r1)
        l.lwz    r11, 0x24(r1)
        l.lwz    r12, 0x28(r1)
        l.lwz    r13, 0x2c(r1)
        l.lwz    r14, 0x30(r1)
        l.lwz    r15, 0x34(r1)
        l.lwz    r16, 0x38(r1)
        l.lwz    r17, 0x3c(r1)
        l.lwz    r18, 0x40(r1)
        l.lwz    r19, 0x44(r1)
        l.lwz    r20, 0x48(r1)
        l.lwz    r21, 0x4c(r1)
        l.lwz    r22, 0x50(r1)
        l.lwz    r23, 0x54(r1)
        l.lwz    r24, 0x58(r1)
        l.lwz    r25, 0x5c(r1)
        l.lwz    r26, 0x60(r1)
        l.lwz    r27, 0x64(r1)
        l.lwz    r28, 0x68(r1)
        l.lwz    r29, 0x6c(r1)
        l.lwz    r30, 0x70(r1)
        l.lwz    r31, 0x74(r1)
        l.lwz    r32, 0x78(r1)
 
        l.addi  r1, r1, EXCEPTION_STACK_SIZE
 
        l.rfe
        l.nop
 

Line No.	Rev	Author	Line
1	349	julius	`#include "spr-defs.h"`
2			`#include "board.h"`
3
4			`/* ======================================================= [ macros ] === */`
5
6	470	julius	`#define REDZONE 128`
7			`#define EXCEPTION_STACK_SIZE (128 + REDZONE)`
8
9	349	julius	`#define CLEAR_GPR(gpr) \`
10			`l.or gpr, r0, r0`
11
12			`#define ENTRY(symbol) \`
13			`.global symbol ; \`
14			`symbol:`
15
16			`#define LOAD_SYMBOL_2_GPR(gpr,symbol) \`
17			`.global symbol ; \`
18			`l.movhi gpr, hi(symbol) ; \`
19			`l.ori gpr, gpr, lo(symbol)`
20
21			`// Really goes to configurable interrupt handler`
22	470	julius	`#define EXCEPTION_HANDLER \`
23			`l.addi r1, r1, -EXCEPTION_STACK_SIZE; \`
24	349	julius	`l.sw 4(r1), r3; \`
25			`l.sw 8(r1), r4; \`
26			`l.mfspr r3,r0,SPR_NPC; \`
27			`l.mfspr r4,r0,SPR_EPCR_BASE; \`
28			`l.j default_exception_handler; \`
29			`l.nop`
30
31			`/* =================================================== [ exceptions ] === */`
32			`.section .vectors, "ax"`
33
34
35			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
36			`.org 0x100`
37			`l.movhi r0, 0`
38			`/* Clear status register, set supervisor mode */`
39			`l.ori r1, r0, SPR_SR_SM`
40			`l.mtspr r0, r1, SPR_SR`
41			`/* Clear timer */`
42			`l.mtspr r0, r0, SPR_TTMR`
43			`/* Early Stack initilization */`
44			`LOAD_SYMBOL_2_GPR(r1, _stack)`
45			`l.addi r2, r0, -3`
46			`l.and r1, r1, r2`
47
48			`/* Jump to program initialisation code */`
49			`LOAD_SYMBOL_2_GPR(r4, _start)`
50			`l.jr r4`
51			`l.nop`
52
53			`/* ---[ 0x200: BUS exception ]------------------------------------------- */`
54			`.org 0x200`
55	470	julius	`EXCEPTION_HANDLER`
56	349	julius
57			`/* ---[ 0x300: Data Page Fault exception ]------------------------------- */`
58			`.org 0x300`
59	470	julius	`EXCEPTION_HANDLER`
60	349	julius
61			`/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */`
62			`.org 0x400`
63	470	julius	`EXCEPTION_HANDLER`
64	349	julius
65	354	julius
66	349	julius	`/* ---[ 0x500: Timer exception ]----------------------------------------- */`
67			`.org 0x500`
68	354	julius	`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
69	470	julius	`//EXCEPTION_HANDLER`
70	354	julius	`/* Simply load timer_ticks variable and increment */`
71	373	julius	`.extern timer_ticks`
72	425	julius	`l.addi r1, r1, -136`
73	354	julius	`l.sw 0(r1), r25`
74			`l.sw 4(r1), r26`
75	373	julius	`l.movhi r25, hi(timer_ticks)`
76			`l.ori r25, r25, lo(timer_ticks)`
77	354	julius	`l.lwz r26, 0(r25) /* Load variable addr.*/`
78			`l.addi r26, r26, 1 /* Increment variable */`
79			`l.sw 0(r25), r26 /* Store variable */`
80			`l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */`
81			`l.ori r25, r25, lo(TIMER_RELOAD_VALUE)`
82			`l.mtspr r0, r25, SPR_TTMR /* Reset timer */`
83			`l.lwz r25, 0(r1)`
84			`l.lwz r26, 4(r1)`
85	425	julius	`l.addi r1, r1, 136`
86	354	julius	`l.rfe`
87	349	julius
88			`/* ---[ 0x600: Aligment exception ]-------------------------------------- */`
89			`.org 0x600`
90	470	julius	`EXCEPTION_HANDLER`
91	349	julius
92			`/* ---[ 0x700: Illegal insn exception ]---------------------------------- */`
93			`.org 0x700`
94	470	julius	`EXCEPTION_HANDLER`
95	349	julius
96			`/* ---[ 0x800: External interrupt exception ]---------------------------- */`
97			`.org 0x800`
98	470	julius	`EXCEPTION_HANDLER`
99	349	julius
100			`/* ---[ 0x900: DTLB miss exception ]------------------------------------- */`
101			`.org 0x900`
102	470	julius	`EXCEPTION_HANDLER`
103	349	julius
104			`/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */`
105			`.org 0xa00`
106	470	julius	`EXCEPTION_HANDLER`
107
108	349	julius	`/* ---[ 0xb00: Range exception ]----------------------------------------- */`
109			`.org 0xb00`
110	470	julius	`EXCEPTION_HANDLER`
111	349	julius
112			`/* ---[ 0xc00: Syscall exception ]--------------------------------------- */`
113			`.org 0xc00`
114	470	julius	`EXCEPTION_HANDLER`
115	349	julius
116	470	julius	`/* ---[ 0xd00: FPU exception ]------------------------------------------- */`
117	349	julius	`.org 0xd00`
118	470	julius	`EXCEPTION_HANDLER`
119	349	julius
120			`/* ---[ 0xe00: Trap exception ]------------------------------------------ */`
121			`.org 0xe00`
122	470	julius	`EXCEPTION_HANDLER`
123	349	julius
124	470	julius	`/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */`
125			`/*`
126	349	julius	`.org 0xf00`
127	470	julius	`EXCEPTION_HANDLER`
128
129	349	julius	`.org 0x1000`
130	470	julius	`EXCEPTION_HANDLER`
131	349	julius
132			`.org 0x1100`
133	470	julius	`EXCEPTION_HANDLER`
134	349	julius
135			`.org 0x1200`
136	470	julius	`EXCEPTION_HANDLER`
137	349	julius
138			`.org 0x1300`
139	470	julius	`EXCEPTION_HANDLER`
140	349	julius
141			`.org 0x1400`
142	470	julius	`EXCEPTION_HANDLER`
143	349	julius
144	470	julius	`*/`
145			`/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */`
146			`/*`
147	349	julius	`.org 0x1500`
148	470	julius	`EXCEPTION_HANDLER`
149	349	julius
150			`.org 0x1600`
151	470	julius	`EXCEPTION_HANDLER`
152	349	julius
153			`.org 0x1700`
154	470	julius	`EXCEPTION_HANDLER`
155	349	julius
156			`.org 0x1800`
157	470	julius	`EXCEPTION_HANDLER`
158			`*/`
159			`/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */`
160			`/*`
161	349	julius	`.org 0x1900`
162	470	julius	`EXCEPTION_HANDLER`
163	349	julius
164			`.org 0x1a00`
165	470	julius	`EXCEPTION_HANDLER`
166	349	julius
167			`.org 0x1b00`
168	470	julius	`EXCEPTION_HANDLER`
169	349	julius
170			`.org 0x1c00`
171	470	julius	`EXCEPTION_HANDLER`
172	349	julius
173			`.org 0x1d00`
174	470	julius	`EXCEPTION_HANDLER`
175	349	julius
176			`.org 0x1e00`
177	470	julius	`EXCEPTION_HANDLER`
178	349	julius
179			`.org 0x1f00`
180	470	julius	`EXCEPTION_HANDLER`
181	349	julius	`*/`
182
183			`/* ========================================================= [ entry ] === */`
184			`.section .text`
185
186			`ENTRY(_start)`
187
188			`/* Instruction cache enable */`
189			`/* Check if IC present and skip enabling otherwise */`
190			`l.mfspr r24,r0,SPR_UPR`
191			`l.andi r26,r24,SPR_UPR_ICP`
192			`l.sfeq r26,r0`
193			`l.bf .L8`
194			`l.nop`
195
196			`/* Disable IC */`
197			`l.mfspr r6,r0,SPR_SR`
198			`l.addi r5,r0,-1`
199			`l.xori r5,r5,SPR_SR_ICE`
200			`l.and r5,r6,r5`
201			`l.mtspr r0,r5,SPR_SR`
202
203			`/* Establish cache block size`
204			`If BS=0, 16;`
205			`If BS=1, 32;`
206			`r14 contain block size`
207			`*/`
208			`l.mfspr r24,r0,SPR_ICCFGR`
209			`l.andi r26,r24,SPR_ICCFGR_CBS`
210			`l.srli r28,r26,7`
211			`l.ori r30,r0,16`
212			`l.sll r14,r30,r28`
213
214			`/* Establish number of cache sets`
215			`r16 contains number of cache sets`
216			`r28 contains log(# of cache sets)`
217			`*/`
218			`l.andi r26,r24,SPR_ICCFGR_NCS`
219			`l.srli r28,r26,3`
220			`l.ori r30,r0,1`
221			`l.sll r16,r30,r28`
222
223			`/* Invalidate IC */`
224			`l.addi r6,r0,0`
225			`l.sll r5,r14,r28`
226
227			`.L7:`
228			`l.mtspr r0,r6,SPR_ICBIR`
229			`l.sfne r6,r5`
230			`l.bf .L7`
231			`l.add r6,r6,r14`
232
233			`/* Enable IC */`
234			`l.mfspr r6,r0,SPR_SR`
235			`l.ori r6,r6,SPR_SR_ICE`
236			`l.mtspr r0,r6,SPR_SR`
237			`l.nop`
238			`l.nop`
239			`l.nop`
240			`l.nop`
241			`l.nop`
242			`l.nop`
243			`l.nop`
244			`l.nop`
245
246			`.L8:`
247			`/* Data cache enable */`
248			`/* Check if DC present and skip enabling otherwise */`
249			`l.mfspr r24,r0,SPR_UPR`
250			`l.andi r26,r24,SPR_UPR_DCP`
251			`l.sfeq r26,r0`
252			`l.bf .L10`
253			`l.nop`
254			`/* Disable DC */`
255			`l.mfspr r6,r0,SPR_SR`
256			`l.addi r5,r0,-1`
257			`l.xori r5,r5,SPR_SR_DCE`
258			`l.and r5,r6,r5`
259			`l.mtspr r0,r5,SPR_SR`
260			`/* Establish cache block size`
261			`If BS=0, 16;`
262			`If BS=1, 32;`
263			`r14 contain block size`
264			`*/`
265			`l.mfspr r24,r0,SPR_DCCFGR`
266			`l.andi r26,r24,SPR_DCCFGR_CBS`
267			`l.srli r28,r26,7`
268			`l.ori r30,r0,16`
269			`l.sll r14,r30,r28`
270			`/* Establish number of cache sets`
271			`r16 contains number of cache sets`
272			`r28 contains log(# of cache sets)`
273			`*/`
274			`l.andi r26,r24,SPR_DCCFGR_NCS`
275			`l.srli r28,r26,3`
276			`l.ori r30,r0,1`
277			`l.sll r16,r30,r28`
278			`/* Invalidate DC */`
279			`l.addi r6,r0,0`
280			`l.sll r5,r14,r28`
281			`.L9:`
282			`l.mtspr r0,r6,SPR_DCBIR`
283			`l.sfne r6,r5`
284			`l.bf .L9`
285			`l.add r6,r6,r14`
286			`/* Enable DC */`
287			`l.mfspr r6,r0,SPR_SR`
288			`l.ori r6,r6,SPR_SR_DCE`
289			`l.mtspr r0,r6,SPR_SR`
290
291			`.L10:`
292
293			`/* Initialise stack */`
294			`/* LOAD_SYMBOL_2_GPR(r1, _stack)`
295			`l.addi r2, r0, -3`
296			`l.and r1, r1, r2`
297			`*/`
298			`/* Clear BSS */`
299	475	julius	`LOAD_SYMBOL_2_GPR(r28, _bss_start)`
300			`LOAD_SYMBOL_2_GPR(r30, _bss_end)`
301	349	julius	`1:`
302			`l.sw (0)(r28), r0`
303			`l.sfltu r28, r30`
304			`l.bf 1b`
305			`l.addi r28, r28, 4`
306
307
308			`/* Initialise UART in a C function */`
309			`/*l.jal _uart_init`
310			`l.nop*/`
311
312
313			`/* Jump to main program entry point (argc = argv = 0) */`
314			`CLEAR_GPR(r3)`
315			`CLEAR_GPR(r4)`
316	373	julius	`l.jal main`
317	349	julius	`l.nop`
318
319			`/* If program exits, call exit routine */`
320			`l.addi r3, r11, 0`
321	373	julius	`l.jal exit`
322	349	julius	`l.nop`
323
324
325			`/* ====================================== [ default exception handler ] === */`
326
327			`default_exception_handler:`
328			`l.sw 0x00(r1), r2`
329			`l.sw 0x0c(r1), r5`
330			`l.sw 0x10(r1), r6`
331			`l.sw 0x14(r1), r7`
332			`l.sw 0x18(r1), r8`
333			`l.sw 0x1c(r1), r9`
334			`l.sw 0x20(r1), r10`
335			`l.sw 0x24(r1), r11`
336			`l.sw 0x28(r1), r12`
337			`l.sw 0x2c(r1), r13`
338			`l.sw 0x30(r1), r14`
339			`l.sw 0x34(r1), r15`
340			`l.sw 0x38(r1), r16`
341			`l.sw 0x3c(r1), r17`
342			`l.sw 0x40(r1), r18`
343			`l.sw 0x44(r1), r19`
344			`l.sw 0x48(r1), r20`
345			`l.sw 0x4c(r1), r21`
346			`l.sw 0x50(r1), r22`
347			`l.sw 0x54(r1), r23`
348			`l.sw 0x58(r1), r24`
349			`l.sw 0x5c(r1), r25`
350			`l.sw 0x60(r1), r26`
351			`l.sw 0x64(r1), r27`
352			`l.sw 0x68(r1), r28`
353			`l.sw 0x6c(r1), r29`
354			`l.sw 0x70(r1), r30`
355			`l.sw 0x74(r1), r31`
356			`l.sw 0x78(r1), r32`
357
358	373	julius	`l.jal default_exception_handler_c`
359	349	julius	`l.nop`
360
361			`l.lwz r2, 0x00(r1)`
362			`l.lwz r3, 0x04(r1)`
363			`l.lwz r4, 0x08(r1)`
364			`l.lwz r5, 0x0c(r1)`
365			`l.lwz r6, 0x10(r1)`
366			`l.lwz r7, 0x14(r1)`
367			`l.lwz r8, 0x18(r1)`
368			`l.lwz r9, 0x1c(r1)`
369			`l.lwz r10, 0x20(r1)`
370			`l.lwz r11, 0x24(r1)`
371			`l.lwz r12, 0x28(r1)`
372			`l.lwz r13, 0x2c(r1)`
373			`l.lwz r14, 0x30(r1)`
374			`l.lwz r15, 0x34(r1)`
375			`l.lwz r16, 0x38(r1)`
376			`l.lwz r17, 0x3c(r1)`
377			`l.lwz r18, 0x40(r1)`
378			`l.lwz r19, 0x44(r1)`
379			`l.lwz r20, 0x48(r1)`
380			`l.lwz r21, 0x4c(r1)`
381			`l.lwz r22, 0x50(r1)`
382			`l.lwz r23, 0x54(r1)`
383			`l.lwz r24, 0x58(r1)`
384			`l.lwz r25, 0x5c(r1)`
385			`l.lwz r26, 0x60(r1)`
386			`l.lwz r27, 0x64(r1)`
387			`l.lwz r28, 0x68(r1)`
388			`l.lwz r29, 0x6c(r1)`
389			`l.lwz r30, 0x70(r1)`
390			`l.lwz r31, 0x74(r1)`
391			`l.lwz r32, 0x78(r1)`
392
393	470	julius	`l.addi r1, r1, EXCEPTION_STACK_SIZE`
394	349	julius
395			`l.rfe`
396			`l.nop`
397

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [drivers/] [or1200/] [crt0.S] - Blame information for rev 479